2009-04-28 06:52:28 +04:00
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/*
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* xHCI host controller driver PCI Bus Glue.
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/pci.h>
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2011-04-25 19:54:28 +04:00
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#include <linux/slab.h>
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2009-04-28 06:52:28 +04:00
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#include "xhci.h"
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2009-08-08 01:04:55 +04:00
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/* Device for a quirk */
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#define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
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#define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
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2009-04-28 06:52:28 +04:00
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static const char hcd_name[] = "xhci_hcd";
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/* called after powerup, by probe or system-pm "wakeup" */
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static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
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{
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/*
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* TODO: Implement finding debug ports later.
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* TODO: see if there are any quirks that need to be added to handle
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* new extended capabilities.
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*/
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/* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
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if (!pci_set_mwi(pdev))
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xhci_dbg(xhci, "MWI active\n");
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xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
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return 0;
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}
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/* called during probe() after chip reset completes */
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static int xhci_pci_setup(struct usb_hcd *hcd)
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{
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-16 22:21:10 +03:00
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struct xhci_hcd *xhci;
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2009-04-28 06:52:28 +04:00
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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int retval;
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2010-07-30 09:13:22 +04:00
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u32 temp;
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2009-04-28 06:52:28 +04:00
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2010-05-19 03:05:21 +04:00
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hcd->self.sg_tablesize = TRBS_PER_SEGMENT - 2;
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2009-08-24 17:44:30 +04:00
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|
|
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-16 22:21:10 +03:00
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if (usb_hcd_is_primary_hcd(hcd)) {
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xhci = kzalloc(sizeof(struct xhci_hcd), GFP_KERNEL);
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if (!xhci)
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return -ENOMEM;
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*((struct xhci_hcd **) hcd->hcd_priv) = xhci;
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xhci->main_hcd = hcd;
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/* Mark the first roothub as being USB 2.0.
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* The xHCI driver will register the USB 3.0 roothub.
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*/
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hcd->speed = HCD_USB2;
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hcd->self.root_hub->speed = USB_SPEED_HIGH;
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/*
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* USB 2.0 roothub under xHCI has an integrated TT,
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* (rate matching hub) as opposed to having an OHCI/UHCI
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* companion controller.
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*/
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hcd->has_tt = 1;
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} else {
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/* xHCI private pointer was set in xhci_pci_probe for the second
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* registered roothub.
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*/
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xhci = hcd_to_xhci(hcd);
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temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
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if (HCC_64BIT_ADDR(temp)) {
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xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
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dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
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} else {
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dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
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}
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return 0;
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}
|
2010-10-26 22:03:44 +04:00
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|
2009-04-28 06:52:28 +04:00
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|
xhci->cap_regs = hcd->regs;
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xhci->op_regs = hcd->regs +
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HC_LENGTH(xhci_readl(xhci, &xhci->cap_regs->hc_capbase));
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xhci->run_regs = hcd->regs +
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(xhci_readl(xhci, &xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
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/* Cache read-only capability registers */
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xhci->hcs_params1 = xhci_readl(xhci, &xhci->cap_regs->hcs_params1);
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xhci->hcs_params2 = xhci_readl(xhci, &xhci->cap_regs->hcs_params2);
|
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|
xhci->hcs_params3 = xhci_readl(xhci, &xhci->cap_regs->hcs_params3);
|
2009-09-04 21:53:20 +04:00
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|
|
xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hc_capbase);
|
|
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|
|
xhci->hci_version = HC_VERSION(xhci->hcc_params);
|
2009-04-28 06:52:28 +04:00
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|
|
xhci->hcc_params = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
|
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xhci_print_registers(xhci);
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|
2009-08-08 01:04:55 +04:00
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/* Look for vendor-specific quirks */
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if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
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pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
|
|
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pdev->revision == 0x0) {
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|
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xhci->quirks |= XHCI_RESET_EP_QUIRK;
|
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|
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xhci_dbg(xhci, "QUIRK: Fresco Logic xHC needs configure"
|
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|
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" endpoint cmd after reset endpoint\n");
|
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|
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}
|
2010-05-25 00:25:28 +04:00
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|
|
if (pdev->vendor == PCI_VENDOR_ID_NEC)
|
|
|
|
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xhci->quirks |= XHCI_NEC_HOST;
|
2009-08-08 01:04:55 +04:00
|
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|
2011-03-22 12:08:14 +03:00
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/* AMD PLL quirk */
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if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
|
|
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xhci->quirks |= XHCI_AMD_PLL_FIX;
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2009-04-28 06:52:28 +04:00
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/* Make sure the HC is halted. */
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retval = xhci_halt(xhci);
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if (retval)
|
2010-10-26 22:03:44 +04:00
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goto error;
|
2009-04-28 06:52:28 +04:00
|
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|
|
|
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|
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xhci_dbg(xhci, "Resetting HCD\n");
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/* Reset the internal HC memory state and registers. */
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retval = xhci_reset(xhci);
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if (retval)
|
2010-10-26 22:03:44 +04:00
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goto error;
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2009-04-28 06:52:28 +04:00
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|
xhci_dbg(xhci, "Reset complete\n");
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|
2010-07-30 09:13:22 +04:00
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temp = xhci_readl(xhci, &xhci->cap_regs->hcc_params);
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if (HCC_64BIT_ADDR(temp)) {
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|
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xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
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|
|
|
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dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64));
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} else {
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dma_set_mask(hcd->self.controller, DMA_BIT_MASK(32));
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}
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|
2009-04-28 06:52:28 +04:00
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|
xhci_dbg(xhci, "Calling HCD init\n");
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|
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/* Initialize HCD and host controller data structures. */
|
|
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|
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retval = xhci_init(hcd);
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|
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if (retval)
|
2010-10-26 22:03:44 +04:00
|
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|
goto error;
|
2009-04-28 06:52:28 +04:00
|
|
|
xhci_dbg(xhci, "Called HCD init\n");
|
|
|
|
|
|
|
|
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pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
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|
|
|
|
xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
|
|
|
|
|
|
|
|
|
|
/* Find any debug ports */
|
2010-10-26 22:03:44 +04:00
|
|
|
retval = xhci_pci_reinit(xhci, pdev);
|
|
|
|
|
if (!retval)
|
|
|
|
|
return retval;
|
|
|
|
|
|
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|
|
|
error:
|
|
|
|
|
kfree(xhci);
|
|
|
|
|
return retval;
|
|
|
|
|
}
|
|
|
|
|
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-16 22:21:10 +03:00
|
|
|
/*
|
|
|
|
|
* We need to register our own PCI probe function (instead of the USB core's
|
|
|
|
|
* function) in order to create a second roothub under xHCI.
|
|
|
|
|
*/
|
|
|
|
|
static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
|
|
|
|
|
{
|
|
|
|
|
int retval;
|
|
|
|
|
struct xhci_hcd *xhci;
|
|
|
|
|
struct hc_driver *driver;
|
|
|
|
|
struct usb_hcd *hcd;
|
|
|
|
|
|
|
|
|
|
driver = (struct hc_driver *)id->driver_data;
|
|
|
|
|
/* Register the USB 2.0 roothub.
|
|
|
|
|
* FIXME: USB core must know to register the USB 2.0 roothub first.
|
|
|
|
|
* This is sort of silly, because we could just set the HCD driver flags
|
|
|
|
|
* to say USB 2.0, but I'm not sure what the implications would be in
|
|
|
|
|
* the other parts of the HCD code.
|
|
|
|
|
*/
|
|
|
|
|
retval = usb_hcd_pci_probe(dev, id);
|
|
|
|
|
|
|
|
|
|
if (retval)
|
|
|
|
|
return retval;
|
|
|
|
|
|
|
|
|
|
/* USB 2.0 roothub is stored in the PCI device now. */
|
|
|
|
|
hcd = dev_get_drvdata(&dev->dev);
|
|
|
|
|
xhci = hcd_to_xhci(hcd);
|
|
|
|
|
xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
|
|
|
|
|
pci_name(dev), hcd);
|
|
|
|
|
if (!xhci->shared_hcd) {
|
|
|
|
|
retval = -ENOMEM;
|
|
|
|
|
goto dealloc_usb2_hcd;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Set the xHCI pointer before xhci_pci_setup() (aka hcd_driver.reset)
|
|
|
|
|
* is called by usb_add_hcd().
|
|
|
|
|
*/
|
|
|
|
|
*((struct xhci_hcd **) xhci->shared_hcd->hcd_priv) = xhci;
|
|
|
|
|
|
|
|
|
|
retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
|
|
|
|
|
IRQF_DISABLED | IRQF_SHARED);
|
|
|
|
|
if (retval)
|
|
|
|
|
goto put_usb3_hcd;
|
|
|
|
|
/* Roothub already marked as USB 3.0 speed */
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
put_usb3_hcd:
|
|
|
|
|
usb_put_hcd(xhci->shared_hcd);
|
|
|
|
|
dealloc_usb2_hcd:
|
|
|
|
|
usb_hcd_pci_remove(dev);
|
|
|
|
|
return retval;
|
|
|
|
|
}
|
|
|
|
|
|
2010-10-26 22:03:44 +04:00
|
|
|
static void xhci_pci_remove(struct pci_dev *dev)
|
|
|
|
|
{
|
|
|
|
|
struct xhci_hcd *xhci;
|
|
|
|
|
|
|
|
|
|
xhci = hcd_to_xhci(pci_get_drvdata(dev));
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-16 22:21:10 +03:00
|
|
|
if (xhci->shared_hcd) {
|
|
|
|
|
usb_remove_hcd(xhci->shared_hcd);
|
|
|
|
|
usb_put_hcd(xhci->shared_hcd);
|
|
|
|
|
}
|
2010-10-26 22:03:44 +04:00
|
|
|
usb_hcd_pci_remove(dev);
|
|
|
|
|
kfree(xhci);
|
2009-04-28 06:52:28 +04:00
|
|
|
}
|
|
|
|
|
|
2010-10-14 18:23:06 +04:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
|
static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
|
|
|
|
|
{
|
|
|
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
|
|
|
int retval = 0;
|
|
|
|
|
|
2011-03-07 22:24:07 +03:00
|
|
|
if (hcd->state != HC_STATE_SUSPENDED ||
|
|
|
|
|
xhci->shared_hcd->state != HC_STATE_SUSPENDED)
|
2010-10-14 18:23:06 +04:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
retval = xhci_suspend(xhci);
|
|
|
|
|
|
|
|
|
|
return retval;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
|
|
|
|
|
{
|
|
|
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
|
|
|
int retval = 0;
|
|
|
|
|
|
|
|
|
|
retval = xhci_resume(xhci, hibernated);
|
|
|
|
|
return retval;
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
|
|
2009-04-28 06:52:28 +04:00
|
|
|
static const struct hc_driver xhci_pci_hc_driver = {
|
|
|
|
|
.description = hcd_name,
|
|
|
|
|
.product_desc = "xHCI Host Controller",
|
2010-10-26 22:03:44 +04:00
|
|
|
.hcd_priv_size = sizeof(struct xhci_hcd *),
|
2009-04-28 06:52:28 +04:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* generic hardware linkage
|
|
|
|
|
*/
|
2009-04-28 06:53:56 +04:00
|
|
|
.irq = xhci_irq,
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-16 22:21:10 +03:00
|
|
|
.flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
|
2009-04-28 06:52:28 +04:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* basic lifecycle operations
|
|
|
|
|
*/
|
|
|
|
|
.reset = xhci_pci_setup,
|
|
|
|
|
.start = xhci_run,
|
2010-10-14 18:23:06 +04:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
|
.pci_suspend = xhci_pci_suspend,
|
|
|
|
|
.pci_resume = xhci_pci_resume,
|
|
|
|
|
#endif
|
2009-04-28 06:52:28 +04:00
|
|
|
.stop = xhci_stop,
|
|
|
|
|
.shutdown = xhci_shutdown,
|
|
|
|
|
|
2009-04-28 06:57:38 +04:00
|
|
|
/*
|
|
|
|
|
* managing i/o requests and associated device resources
|
|
|
|
|
*/
|
2009-04-28 06:58:01 +04:00
|
|
|
.urb_enqueue = xhci_urb_enqueue,
|
|
|
|
|
.urb_dequeue = xhci_urb_dequeue,
|
2009-04-28 06:57:38 +04:00
|
|
|
.alloc_dev = xhci_alloc_dev,
|
|
|
|
|
.free_dev = xhci_free_dev,
|
2010-04-05 21:55:58 +04:00
|
|
|
.alloc_streams = xhci_alloc_streams,
|
|
|
|
|
.free_streams = xhci_free_streams,
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 06:58:38 +04:00
|
|
|
.add_endpoint = xhci_add_endpoint,
|
|
|
|
|
.drop_endpoint = xhci_drop_endpoint,
|
2009-07-27 23:03:15 +04:00
|
|
|
.endpoint_reset = xhci_endpoint_reset,
|
USB: xhci: Bandwidth allocation support
Since the xHCI host controller hardware (xHC) has an internal schedule, it
needs a better representation of what devices are consuming bandwidth on
the bus. Each device is represented by a device context, with data about
the device, endpoints, and pointers to each endpoint ring.
We need to update the endpoint information for a device context before a
new configuration or alternate interface setting is selected. We setup an
input device context with modified endpoint information and newly
allocated endpoint rings, and then submit a Configure Endpoint Command to
the hardware.
The host controller can reject the new configuration if it exceeds the bus
bandwidth, or the host controller doesn't have enough internal resources
for the configuration. If the command fails, we still have the older
device context with the previous configuration. If the command succeeds,
we free the old endpoint rings.
The root hub isn't a real device, so always say yes to any bandwidth
changes for it.
The USB core will enable, disable, and then enable endpoint 0 several
times during the initialization sequence. The device will always have an
endpoint ring for endpoint 0 and bandwidth allocated for that, unless the
device is disconnected or gets a SetAddress 0 request. So we don't pay
attention for when xhci_check_bandwidth() is called for a re-add of
endpoint 0.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2009-04-28 06:58:38 +04:00
|
|
|
.check_bandwidth = xhci_check_bandwidth,
|
|
|
|
|
.reset_bandwidth = xhci_reset_bandwidth,
|
2009-04-28 06:57:38 +04:00
|
|
|
.address_device = xhci_address_device,
|
2009-09-04 21:53:24 +04:00
|
|
|
.update_hub_device = xhci_update_hub_device,
|
2010-10-14 18:22:48 +04:00
|
|
|
.reset_device = xhci_discover_or_reset_device,
|
2009-04-28 06:57:38 +04:00
|
|
|
|
2009-04-28 06:52:28 +04:00
|
|
|
/*
|
|
|
|
|
* scheduling support
|
|
|
|
|
*/
|
|
|
|
|
.get_frame_number = xhci_get_frame,
|
|
|
|
|
|
2009-04-28 06:57:12 +04:00
|
|
|
/* Root hub support */
|
|
|
|
|
.hub_control = xhci_hub_control,
|
|
|
|
|
.hub_status_data = xhci_hub_status_data,
|
2010-10-14 18:23:03 +04:00
|
|
|
.bus_suspend = xhci_bus_suspend,
|
|
|
|
|
.bus_resume = xhci_bus_resume,
|
2009-04-28 06:52:28 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
|
|
|
|
|
|
/* PCI driver selection metadata; PCI hotplugging uses this */
|
|
|
|
|
static const struct pci_device_id pci_ids[] = { {
|
|
|
|
|
/* handle any USB 3.0 xHCI controller */
|
|
|
|
|
PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
|
|
|
|
|
.driver_data = (unsigned long) &xhci_pci_hc_driver,
|
|
|
|
|
},
|
|
|
|
|
{ /* end: all zeroes */ }
|
|
|
|
|
};
|
|
|
|
|
MODULE_DEVICE_TABLE(pci, pci_ids);
|
|
|
|
|
|
|
|
|
|
/* pci driver glue; this is a "new style" PCI driver module */
|
|
|
|
|
static struct pci_driver xhci_pci_driver = {
|
|
|
|
|
.name = (char *) hcd_name,
|
|
|
|
|
.id_table = pci_ids,
|
|
|
|
|
|
xhci: Register second xHCI roothub.
This patch changes the xHCI driver to allocate two roothubs. This touches
the driver initialization and shutdown paths, roothub emulation code, and
port status change event handlers. This is a rather large patch, but it
can't be broken up, or it would break git-bisect.
Make the xHCI driver register its own PCI probe function. This will call
the USB core to create the USB 2.0 roothub, and then create the USB 3.0
roothub. This gets the code for registering a shared roothub out of the
USB core, and allows other HCDs later to decide if and how many shared
roothubs they want to allocate.
Make sure the xHCI's reset method marks the xHCI host controller's primary
roothub as the USB 2.0 roothub. This ensures that the high speed bus will
be processed first when the PCI device is resumed, and any USB 3.0 devices
that have migrated over to high speed will migrate back after being reset.
This ensures that USB persist works with these odd devices.
The reset method will also mark the xHCI USB2 roothub as having an
integrated TT. Like EHCI host controllers with a "rate matching hub" the
xHCI USB 2.0 roothub doesn't have an OHCI or UHCI companion controller.
It doesn't really have a TT, but we'll lie and say it has an integrated
TT. We need to do this because the USB core will reject LS/FS devices
under a HS hub without a TT.
Other details:
-------------
The roothub emulation code is changed to return the correct number of
ports for the two roothubs. For the USB 3.0 roothub, it only reports the
USB 3.0 ports. For the USB 2.0 roothub, it reports all the LS/FS/HS
ports. The code to disable a port now checks the speed of the roothub,
and refuses to disable SuperSpeed ports under the USB 3.0 roothub.
The code for initializing a new device context must be changed to set the
proper roothub port number. Since we've split the xHCI host into two
roothubs, we can't just use the port number in the ancestor hub. Instead,
we loop through the array of hardware port status register speeds and find
the Nth port with a similar speed.
The port status change event handler is updated to figure out whether the
port that reported the change is a USB 3.0 port, or a non-SuperSpeed port.
Once it figures out the port speed, it kicks the proper roothub.
The function to find a slot ID based on the port index is updated to take
into account that the two roothubs will have over-lapping port indexes.
It checks that the virtual device with a matching port index is the same
speed as the passed in roothub.
There's also changes to the driver initialization and shutdown paths:
1. Make sure that the xhci_hcd pointer is shared across the two
usb_hcd structures. The xhci_hcd pointer is allocated and the
registers are mapped in when xhci_pci_setup() is called with the
primary HCD. When xhci_pci_setup() is called with the non-primary
HCD, the xhci_hcd pointer is stored.
2. Make sure to set the sg_tablesize for both usb_hcd structures. Set
the PCI DMA mask for the non-primary HCD to allow for 64-bit or 32-bit
DMA. (The PCI DMA mask is set from the primary HCD further down in
the xhci_pci_setup() function.)
3. Ensure that the host controller doesn't start kicking khubd in
response to port status changes before both usb_hcd structures are
registered. xhci_run() only starts the xHC running once it has been
called with the non-primary roothub. Similarly, the xhci_stop()
function only halts the host controller when it is called with the
non-primary HCD. Then on the second call, it resets and cleans up the
MSI-X irqs.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2010-12-16 22:21:10 +03:00
|
|
|
.probe = xhci_pci_probe,
|
2010-10-26 22:03:44 +04:00
|
|
|
.remove = xhci_pci_remove,
|
2009-04-28 06:52:28 +04:00
|
|
|
/* suspend and resume implemented later */
|
|
|
|
|
|
|
|
|
|
.shutdown = usb_hcd_pci_shutdown,
|
2010-10-14 18:23:06 +04:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
|
|
|
.driver = {
|
|
|
|
|
.pm = &usb_hcd_pci_pm_ops
|
|
|
|
|
},
|
|
|
|
|
#endif
|
2009-04-28 06:52:28 +04:00
|
|
|
};
|
|
|
|
|
|
2010-04-19 19:53:50 +04:00
|
|
|
int xhci_register_pci(void)
|
2009-04-28 06:52:28 +04:00
|
|
|
{
|
|
|
|
|
return pci_register_driver(&xhci_pci_driver);
|
|
|
|
|
}
|
|
|
|
|
|
2010-04-19 19:53:50 +04:00
|
|
|
void xhci_unregister_pci(void)
|
2009-04-28 06:52:28 +04:00
|
|
|
{
|
|
|
|
|
pci_unregister_driver(&xhci_pci_driver);
|
|
|
|
|
}
|
