2018-09-07 04:52:28 +03:00
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/* SPDX-License-Identifier: GPL-2.0+
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clk: shmobile: Add new Renesas CPG/MSSR DT bindings
On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse
Generator) and MSSR (Module Standby and Software Reset) blocks are
intimately connected, and share the same register block.
Hence it makes sense to describe these two blocks using a
single device node in DT, instead of using a hierarchical structure with
multiple nodes, using a mix of generic and SoC-specific bindings.
These new DT bindings are intended to replace the existing DT bindings
for CPG core clocks ("renesas,*-cpg-clocks", "renesas,cpg-div6-clock")
and module clocks ("renesas,*-mstp-clocks"), at least for new SoCs.
This will make it easier to add module reset support later, which is
currently not implemented, and difficult to achieve using the existing
bindings due to the intertwined register layout.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Magnus Damm <damm+renesas@opensource.se>
2015-10-12 12:05:24 +03:00
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*
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2018-09-07 04:52:28 +03:00
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* Copyright (C) 2015 Renesas Electronics Corp.
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clk: shmobile: Add new Renesas CPG/MSSR DT bindings
On Renesas ARM SoCs (SH/R-Mobile, R-Car, RZ), the CPG (Clock Pulse
Generator) and MSSR (Module Standby and Software Reset) blocks are
intimately connected, and share the same register block.
Hence it makes sense to describe these two blocks using a
single device node in DT, instead of using a hierarchical structure with
multiple nodes, using a mix of generic and SoC-specific bindings.
These new DT bindings are intended to replace the existing DT bindings
for CPG core clocks ("renesas,*-cpg-clocks", "renesas,cpg-div6-clock")
and module clocks ("renesas,*-mstp-clocks"), at least for new SoCs.
This will make it easier to add module reset support later, which is
currently not implemented, and difficult to achieve using the existing
bindings due to the intertwined register layout.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Reviewed-by: Magnus Damm <damm+renesas@opensource.se>
2015-10-12 12:05:24 +03:00
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*/
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#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
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#define CPG_CORE 0 /* Core Clock */
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#define CPG_MOD 1 /* Module Clock */
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#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */
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