2008-05-20 03:52:27 +04:00
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/*
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2005-04-17 02:20:36 +04:00
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* linux/arch/sparc64/kernel/setup.c
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*
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* Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/ptrace.h>
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#include <asm/smp.h>
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#include <linux/user.h>
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2006-07-10 15:44:13 +04:00
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#include <linux/screen_info.h>
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2005-04-17 02:20:36 +04:00
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#include <linux/delay.h>
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#include <linux/fs.h>
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#include <linux/seq_file.h>
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#include <linux/syscalls.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/inet.h>
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#include <linux/console.h>
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#include <linux/root_dev.h>
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#include <linux/interrupt.h>
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#include <linux/cpu.h>
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#include <linux/initrd.h>
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2011-07-29 10:31:26 +04:00
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#include <linux/module.h>
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2005-04-17 02:20:36 +04:00
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/oplib.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/idprom.h>
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#include <asm/head.h>
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#include <asm/starfire.h>
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#include <asm/mmu_context.h>
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#include <asm/timer.h>
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#include <asm/sections.h>
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#include <asm/setup.h>
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#include <asm/mmu.h>
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2007-05-26 02:49:59 +04:00
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#include <asm/ns87303.h>
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2009-11-28 04:33:43 +03:00
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#include <asm/btext.h>
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2011-07-29 10:31:26 +04:00
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#include <asm/elf.h>
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#include <asm/mdesc.h>
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2012-03-28 21:30:03 +04:00
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#include <asm/cacheflush.h>
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2005-04-17 02:20:36 +04:00
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#ifdef CONFIG_IP_PNP
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#include <net/ipconfig.h>
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#endif
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2008-03-26 07:51:40 +03:00
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#include "entry.h"
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2008-12-07 11:02:08 +03:00
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#include "kernel.h"
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2008-03-26 07:51:40 +03:00
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2007-05-26 02:49:59 +04:00
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/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
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* operations in asm/ns87303.h
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*/
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DEFINE_SPINLOCK(ns87303_lock);
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2009-01-09 03:58:20 +03:00
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EXPORT_SYMBOL(ns87303_lock);
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2007-05-26 02:49:59 +04:00
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2005-04-17 02:20:36 +04:00
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struct screen_info screen_info = {
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0, 0, /* orig-x, orig-y */
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0, /* unused */
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0, /* orig-video-page */
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0, /* orig-video-mode */
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128, /* orig-video-cols */
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0, 0, 0, /* unused, ega_bx, unused */
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54, /* orig-video-lines */
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0, /* orig-video-isVGA */
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16 /* orig-video-points */
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};
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static void
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prom_console_write(struct console *con, const char *s, unsigned n)
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{
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prom_write(s, n);
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}
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/* Exported for mm/init.c:paging_init. */
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unsigned long cmdline_memory_size = 0;
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2008-02-18 10:22:50 +03:00
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static struct console prom_early_console = {
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.name = "earlyprom",
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2005-04-17 02:20:36 +04:00
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.write = prom_console_write,
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2008-04-24 09:22:29 +04:00
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.flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
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2005-04-17 02:20:36 +04:00
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.index = -1,
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};
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/*
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* Process kernel command line switches that are specific to the
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* SPARC or that require special low-level processing.
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*/
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static void __init process_switch(char c)
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{
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switch (c) {
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case 'd':
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case 's':
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break;
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case 'h':
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prom_printf("boot_flags_init: Halt!\n");
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prom_halt();
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break;
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case 'p':
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2011-09-21 23:48:06 +04:00
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prom_early_console.flags &= ~CON_BOOT;
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2005-04-17 02:20:36 +04:00
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break;
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2005-05-24 02:52:08 +04:00
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case 'P':
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/* Force UltraSPARC-III P-Cache on. */
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if (tlb_type != cheetah) {
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printk("BOOT: Ignoring P-Cache force option.\n");
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break;
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}
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cheetah_pcache_forced_on = 1;
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2013-01-21 10:47:39 +04:00
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add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
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2005-05-24 02:52:08 +04:00
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cheetah_enable_pcache();
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break;
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2005-04-17 02:20:36 +04:00
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default:
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printk("Unknown boot switch (-%c)\n", c);
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break;
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}
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}
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static void __init boot_flags_init(char *commands)
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{
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while (*commands) {
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/* Move to the start of the next "argument". */
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while (*commands && *commands == ' ')
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commands++;
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/* Process any command switches, otherwise skip it. */
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if (*commands == '\0')
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break;
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if (*commands == '-') {
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commands++;
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while (*commands && *commands != ' ')
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process_switch(*commands++);
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continue;
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}
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2007-07-21 03:59:26 +04:00
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if (!strncmp(commands, "mem=", 4)) {
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2005-04-17 02:20:36 +04:00
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/*
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* "mem=XXX[kKmM]" overrides the PROM-reported
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* memory size.
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*/
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cmdline_memory_size = simple_strtoul(commands + 4,
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&commands, 0);
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if (*commands == 'K' || *commands == 'k') {
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cmdline_memory_size <<= 10;
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commands++;
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} else if (*commands=='M' || *commands=='m') {
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cmdline_memory_size <<= 20;
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commands++;
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}
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}
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while (*commands && *commands != ' ')
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commands++;
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}
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}
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extern unsigned short root_flags;
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extern unsigned short root_dev;
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extern unsigned short ram_flags;
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#define RAMDISK_IMAGE_START_MASK 0x07FF
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#define RAMDISK_PROMPT_FLAG 0x8000
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#define RAMDISK_LOAD_FLAG 0x4000
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extern int root_mountflags;
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char reboot_command[COMMAND_LINE_SIZE];
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static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
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2006-05-31 12:24:02 +04:00
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void __init per_cpu_patch(void)
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2006-02-27 10:27:19 +03:00
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{
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struct cpuid_patch_entry *p;
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unsigned long ver;
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int is_jbus;
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if (tlb_type == spitfire && !this_is_starfire)
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return;
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2006-02-09 13:52:44 +03:00
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is_jbus = 0;
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if (tlb_type != hypervisor) {
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__asm__ ("rdpr %%ver, %0" : "=r" (ver));
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2006-02-17 19:38:06 +03:00
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is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
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(ver >> 32UL) == __SERRANO_ID);
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2006-02-09 13:52:44 +03:00
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}
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2006-02-27 10:27:19 +03:00
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p = &__cpuid_patch;
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while (p < &__cpuid_patch_end) {
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unsigned long addr = p->addr;
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unsigned int *insns;
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switch (tlb_type) {
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case spitfire:
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insns = &p->starfire[0];
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break;
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case cheetah:
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case cheetah_plus:
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if (is_jbus)
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insns = &p->cheetah_jbus[0];
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else
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insns = &p->cheetah_safari[0];
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break;
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2006-02-05 02:40:53 +03:00
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case hypervisor:
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insns = &p->sun4v[0];
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break;
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2006-02-27 10:27:19 +03:00
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default:
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prom_printf("Unknown cpu type, halting.\n");
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prom_halt();
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2011-06-03 18:45:23 +04:00
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}
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2006-02-27 10:27:19 +03:00
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*(unsigned int *) (addr + 0) = insns[0];
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2006-02-07 02:52:05 +03:00
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wmb();
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2006-02-27 10:27:19 +03:00
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__asm__ __volatile__("flush %0" : : "r" (addr + 0));
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*(unsigned int *) (addr + 4) = insns[1];
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2006-02-07 02:52:05 +03:00
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wmb();
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2006-02-27 10:27:19 +03:00
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__asm__ __volatile__("flush %0" : : "r" (addr + 4));
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*(unsigned int *) (addr + 8) = insns[2];
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2006-02-07 02:52:05 +03:00
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wmb();
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2006-02-27 10:27:19 +03:00
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__asm__ __volatile__("flush %0" : : "r" (addr + 8));
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*(unsigned int *) (addr + 12) = insns[3];
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2006-02-07 02:52:05 +03:00
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wmb();
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2006-02-27 10:27:19 +03:00
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__asm__ __volatile__("flush %0" : : "r" (addr + 12));
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p++;
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}
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}
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2011-11-18 10:44:58 +04:00
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void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
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struct sun4v_1insn_patch_entry *end)
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2006-02-06 08:29:28 +03:00
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{
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2011-11-18 10:44:58 +04:00
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while (start < end) {
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unsigned long addr = start->addr;
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2006-02-06 08:29:28 +03:00
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2011-11-18 10:44:58 +04:00
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*(unsigned int *) (addr + 0) = start->insn;
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2006-02-07 02:52:05 +03:00
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wmb();
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2006-02-06 08:29:28 +03:00
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__asm__ __volatile__("flush %0" : : "r" (addr + 0));
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2011-11-18 10:44:58 +04:00
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start++;
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2006-02-06 09:27:28 +03:00
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}
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2011-11-18 10:44:58 +04:00
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}
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2006-02-06 09:27:28 +03:00
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2011-11-18 10:44:58 +04:00
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void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
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struct sun4v_2insn_patch_entry *end)
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{
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while (start < end) {
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unsigned long addr = start->addr;
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2006-02-06 09:27:28 +03:00
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2011-11-18 10:44:58 +04:00
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*(unsigned int *) (addr + 0) = start->insns[0];
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2006-02-07 02:52:05 +03:00
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wmb();
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2006-02-06 09:27:28 +03:00
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__asm__ __volatile__("flush %0" : : "r" (addr + 0));
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2011-11-18 10:44:58 +04:00
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*(unsigned int *) (addr + 4) = start->insns[1];
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2006-02-07 02:52:05 +03:00
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wmb();
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2006-02-06 09:27:28 +03:00
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__asm__ __volatile__("flush %0" : : "r" (addr + 4));
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2011-11-18 10:44:58 +04:00
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start++;
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2006-02-06 08:29:28 +03:00
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}
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2011-11-18 10:44:58 +04:00
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}
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void __init sun4v_patch(void)
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{
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extern void sun4v_hvapi_init(void);
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if (tlb_type != hypervisor)
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return;
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sun4v_patch_1insn_range(&__sun4v_1insn_patch,
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&__sun4v_1insn_patch_end);
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sun4v_patch_2insn_range(&__sun4v_2insn_patch,
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&__sun4v_2insn_patch_end);
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2007-05-16 04:03:54 +04:00
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sun4v_hvapi_init();
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2006-02-06 08:29:28 +03:00
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}
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2011-07-29 20:42:07 +04:00
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static void __init popc_patch(void)
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{
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struct popc_3insn_patch_entry *p3;
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2011-08-03 07:23:34 +04:00
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struct popc_6insn_patch_entry *p6;
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2011-07-29 20:42:07 +04:00
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p3 = &__popc_3insn_patch;
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while (p3 < &__popc_3insn_patch_end) {
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2011-08-03 07:23:34 +04:00
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unsigned long i, addr = p3->addr;
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2011-07-29 20:42:07 +04:00
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2011-08-03 07:23:34 +04:00
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for (i = 0; i < 3; i++) {
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*(unsigned int *) (addr + (i * 4)) = p3->insns[i];
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wmb();
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__asm__ __volatile__("flush %0"
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: : "r" (addr + (i * 4)));
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}
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2011-07-29 20:42:07 +04:00
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2011-08-03 07:23:34 +04:00
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p3++;
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}
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2011-07-29 20:42:07 +04:00
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2011-08-03 07:23:34 +04:00
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p6 = &__popc_6insn_patch;
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while (p6 < &__popc_6insn_patch_end) {
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unsigned long i, addr = p6->addr;
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2011-07-29 20:42:07 +04:00
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2011-08-03 07:23:34 +04:00
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for (i = 0; i < 6; i++) {
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*(unsigned int *) (addr + (i * 4)) = p6->insns[i];
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wmb();
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__asm__ __volatile__("flush %0"
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: : "r" (addr + (i * 4)));
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}
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p6++;
|
2011-07-29 20:42:07 +04:00
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}
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}
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2012-10-28 10:00:41 +04:00
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static void __init pause_patch(void)
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{
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struct pause_patch_entry *p;
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|
|
|
|
2012-10-29 00:04:47 +04:00
|
|
|
p = &__pause_3insn_patch;
|
|
|
|
while (p < &__pause_3insn_patch_end) {
|
2012-10-28 10:00:41 +04:00
|
|
|
unsigned long i, addr = p->addr;
|
|
|
|
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
|
|
*(unsigned int *) (addr + (i * 4)) = p->insns[i];
|
|
|
|
wmb();
|
|
|
|
__asm__ __volatile__("flush %0"
|
|
|
|
: : "r" (addr + (i * 4)));
|
|
|
|
}
|
|
|
|
|
|
|
|
p++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2006-05-31 12:24:02 +04:00
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
void __init boot_cpu_id_too_large(int cpu)
|
|
|
|
{
|
|
|
|
prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
|
|
|
|
cpu, NR_CPUS);
|
|
|
|
prom_halt();
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2011-07-29 10:31:26 +04:00
|
|
|
/* On Ultra, we support all of the v8 capabilities. */
|
|
|
|
unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
|
|
|
|
HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
|
|
|
|
HWCAP_SPARC_V9);
|
|
|
|
EXPORT_SYMBOL(sparc64_elf_hwcap);
|
|
|
|
|
|
|
|
static const char *hwcaps[] = {
|
|
|
|
"flush", "stbar", "swap", "muldiv", "v9",
|
|
|
|
"ultra3", "blkinit", "n2",
|
|
|
|
|
|
|
|
/* These strings are as they appear in the machine description
|
|
|
|
* 'hwcap-list' property for cpu nodes.
|
|
|
|
*/
|
|
|
|
"mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
|
|
|
|
"ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
|
2012-08-17 03:41:04 +04:00
|
|
|
"ima", "cspare", "pause", "cbcond",
|
|
|
|
};
|
|
|
|
|
|
|
|
static const char *crypto_hwcaps[] = {
|
|
|
|
"aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
|
|
|
|
"sha512", "mpmul", "montmul", "montsqr", "crc32c",
|
2011-07-29 10:31:26 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
void cpucap_info(struct seq_file *m)
|
|
|
|
{
|
|
|
|
unsigned long caps = sparc64_elf_hwcap;
|
|
|
|
int i, printed = 0;
|
|
|
|
|
|
|
|
seq_puts(m, "cpucaps\t\t: ");
|
|
|
|
for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
|
|
|
|
unsigned long bit = 1UL << i;
|
|
|
|
if (caps & bit) {
|
|
|
|
seq_printf(m, "%s%s",
|
|
|
|
printed ? "," : "", hwcaps[i]);
|
|
|
|
printed++;
|
|
|
|
}
|
|
|
|
}
|
2012-08-17 03:41:04 +04:00
|
|
|
if (caps & HWCAP_SPARC_CRYPTO) {
|
|
|
|
unsigned long cfr;
|
|
|
|
|
|
|
|
__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
|
|
|
|
for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
|
|
|
|
unsigned long bit = 1UL << i;
|
|
|
|
if (cfr & bit) {
|
|
|
|
seq_printf(m, "%s%s",
|
|
|
|
printed ? "," : "", crypto_hwcaps[i]);
|
|
|
|
printed++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2011-07-29 10:31:26 +04:00
|
|
|
seq_putc(m, '\n');
|
|
|
|
}
|
|
|
|
|
2012-08-17 03:41:04 +04:00
|
|
|
static void __init report_one_hwcap(int *printed, const char *name)
|
|
|
|
{
|
|
|
|
if ((*printed) == 0)
|
|
|
|
printk(KERN_INFO "CPU CAPS: [");
|
|
|
|
printk(KERN_CONT "%s%s",
|
|
|
|
(*printed) ? "," : "", name);
|
|
|
|
if (++(*printed) == 8) {
|
|
|
|
printk(KERN_CONT "]\n");
|
|
|
|
*printed = 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __init report_crypto_hwcaps(int *printed)
|
|
|
|
{
|
|
|
|
unsigned long cfr;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
|
|
|
|
unsigned long bit = 1UL << i;
|
|
|
|
if (cfr & bit)
|
|
|
|
report_one_hwcap(printed, crypto_hwcaps[i]);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-07-29 10:31:26 +04:00
|
|
|
static void __init report_hwcaps(unsigned long caps)
|
|
|
|
{
|
|
|
|
int i, printed = 0;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
|
|
|
|
unsigned long bit = 1UL << i;
|
2012-08-17 03:41:04 +04:00
|
|
|
if (caps & bit)
|
|
|
|
report_one_hwcap(&printed, hwcaps[i]);
|
2011-07-29 10:31:26 +04:00
|
|
|
}
|
2012-08-17 03:41:04 +04:00
|
|
|
if (caps & HWCAP_SPARC_CRYPTO)
|
|
|
|
report_crypto_hwcaps(&printed);
|
|
|
|
if (printed != 0)
|
|
|
|
printk(KERN_CONT "]\n");
|
2011-07-29 10:31:26 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static unsigned long __init mdesc_cpu_hwcap_list(void)
|
|
|
|
{
|
|
|
|
struct mdesc_handle *hp;
|
|
|
|
unsigned long caps = 0;
|
|
|
|
const char *prop;
|
|
|
|
int len;
|
|
|
|
u64 pn;
|
|
|
|
|
|
|
|
hp = mdesc_grab();
|
|
|
|
if (!hp)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
|
|
|
|
if (pn == MDESC_NODE_NULL)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
|
|
|
|
if (!prop)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
while (len) {
|
|
|
|
int i, plen;
|
|
|
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
|
|
|
|
unsigned long bit = 1UL << i;
|
|
|
|
|
|
|
|
if (!strcmp(prop, hwcaps[i])) {
|
|
|
|
caps |= bit;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2012-08-17 03:41:04 +04:00
|
|
|
for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
|
|
|
|
if (!strcmp(prop, crypto_hwcaps[i]))
|
|
|
|
caps |= HWCAP_SPARC_CRYPTO;
|
|
|
|
}
|
2011-07-29 10:31:26 +04:00
|
|
|
|
|
|
|
plen = strlen(prop) + 1;
|
|
|
|
prop += plen;
|
|
|
|
len -= plen;
|
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
mdesc_release(hp);
|
|
|
|
return caps;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* This yields a mask that user programs can use to figure out what
|
|
|
|
* instruction set this cpu supports.
|
|
|
|
*/
|
|
|
|
static void __init init_sparc64_elf_hwcap(void)
|
|
|
|
{
|
|
|
|
unsigned long cap = sparc64_elf_hwcap;
|
|
|
|
unsigned long mdesc_caps;
|
|
|
|
|
|
|
|
if (tlb_type == cheetah || tlb_type == cheetah_plus)
|
|
|
|
cap |= HWCAP_SPARC_ULTRA3;
|
|
|
|
else if (tlb_type == hypervisor) {
|
|
|
|
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
|
|
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
2011-09-11 21:42:20 +04:00
|
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
|
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
2013-07-23 15:20:38 +04:00
|
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
|
|
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC64X)
|
2011-07-29 10:31:26 +04:00
|
|
|
cap |= HWCAP_SPARC_BLKINIT;
|
|
|
|
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
2011-09-11 21:42:20 +04:00
|
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
|
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
2013-07-23 15:20:38 +04:00
|
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
|
|
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC64X)
|
2011-07-29 10:31:26 +04:00
|
|
|
cap |= HWCAP_SPARC_N2;
|
|
|
|
}
|
|
|
|
|
|
|
|
cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);
|
|
|
|
|
|
|
|
mdesc_caps = mdesc_cpu_hwcap_list();
|
|
|
|
if (!mdesc_caps) {
|
|
|
|
if (tlb_type == spitfire)
|
|
|
|
cap |= AV_SPARC_VIS;
|
|
|
|
if (tlb_type == cheetah || tlb_type == cheetah_plus)
|
|
|
|
cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
|
2011-08-30 08:14:29 +04:00
|
|
|
if (tlb_type == cheetah_plus) {
|
|
|
|
unsigned long impl, ver;
|
|
|
|
|
|
|
|
__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
|
|
|
|
impl = ((ver >> 32) & 0xffff);
|
|
|
|
if (impl == PANTHER_IMPL)
|
|
|
|
cap |= AV_SPARC_POPC;
|
|
|
|
}
|
2011-07-29 10:31:26 +04:00
|
|
|
if (tlb_type == hypervisor) {
|
|
|
|
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
|
|
|
|
cap |= AV_SPARC_ASI_BLK_INIT;
|
|
|
|
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
|
2011-09-11 21:42:20 +04:00
|
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
|
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
2013-07-23 15:20:38 +04:00
|
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
|
|
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC64X)
|
2011-07-29 10:31:26 +04:00
|
|
|
cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
|
|
|
|
AV_SPARC_ASI_BLK_INIT |
|
|
|
|
AV_SPARC_POPC);
|
2011-09-11 21:42:20 +04:00
|
|
|
if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
|
|
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
|
2013-07-23 15:20:38 +04:00
|
|
|
sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
|
|
|
|
sun4v_chip_type == SUN4V_CHIP_SPARC64X)
|
2011-07-29 10:31:26 +04:00
|
|
|
cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
|
|
|
|
AV_SPARC_FMAF);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
sparc64_elf_hwcap = cap | mdesc_caps;
|
|
|
|
|
|
|
|
report_hwcaps(sparc64_elf_hwcap);
|
2011-07-29 20:42:07 +04:00
|
|
|
|
|
|
|
if (sparc64_elf_hwcap & AV_SPARC_POPC)
|
|
|
|
popc_patch();
|
2012-10-28 10:00:41 +04:00
|
|
|
if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
|
|
|
|
pause_patch();
|
2011-07-29 10:31:26 +04:00
|
|
|
}
|
|
|
|
|
2005-04-17 02:20:36 +04:00
|
|
|
void __init setup_arch(char **cmdline_p)
|
|
|
|
{
|
|
|
|
/* Initialize PROM console and command line. */
|
|
|
|
*cmdline_p = prom_getbootargs();
|
2013-06-09 12:57:58 +04:00
|
|
|
strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
|
2008-03-19 13:54:09 +03:00
|
|
|
parse_early_param();
|
2005-04-17 02:20:36 +04:00
|
|
|
|
2008-02-18 10:22:50 +03:00
|
|
|
boot_flags_init(*cmdline_p);
|
2009-11-28 04:33:43 +03:00
|
|
|
#ifdef CONFIG_EARLYFB
|
|
|
|
if (btext_find_display())
|
|
|
|
#endif
|
|
|
|
register_console(&prom_early_console);
|
2008-02-18 10:22:50 +03:00
|
|
|
|
2006-02-09 13:54:54 +03:00
|
|
|
if (tlb_type == hypervisor)
|
|
|
|
printk("ARCH: SUN4V\n");
|
|
|
|
else
|
|
|
|
printk("ARCH: SUN4U\n");
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
#ifdef CONFIG_DUMMY_CONSOLE
|
|
|
|
conswitchp = &dummy_con;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
idprom_init();
|
|
|
|
|
|
|
|
if (!root_flags)
|
|
|
|
root_mountflags &= ~MS_RDONLY;
|
|
|
|
ROOT_DEV = old_decode_dev(root_dev);
|
2006-03-19 23:46:55 +03:00
|
|
|
#ifdef CONFIG_BLK_DEV_RAM
|
2005-04-17 02:20:36 +04:00
|
|
|
rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
|
|
|
|
rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
|
|
|
|
rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
|
|
|
|
#endif
|
|
|
|
|
2006-01-12 12:05:42 +03:00
|
|
|
task_thread_info(&init_task)->kregs = &fake_swapper_regs;
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
#ifdef CONFIG_IP_PNP
|
|
|
|
if (!ic_set_manually) {
|
2010-10-09 01:18:11 +04:00
|
|
|
phandle chosen = prom_finddevice("/chosen");
|
2005-04-17 02:20:36 +04:00
|
|
|
u32 cl, sv, gw;
|
|
|
|
|
|
|
|
cl = prom_getintdefault (chosen, "client-ip", 0);
|
|
|
|
sv = prom_getintdefault (chosen, "server-ip", 0);
|
|
|
|
gw = prom_getintdefault (chosen, "gateway-ip", 0);
|
|
|
|
if (cl && sv) {
|
|
|
|
ic_myaddr = cl;
|
|
|
|
ic_servaddr = sv;
|
|
|
|
if (gw)
|
|
|
|
ic_gateway = gw;
|
|
|
|
#if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
|
|
|
|
ic_proto_enabled = 0;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2006-02-27 10:24:22 +03:00
|
|
|
/* Get boot processor trap_block[] setup. */
|
[SPARC64]: Get SUN4V SMP working.
The sibling cpu bringup is extremely fragile. We can only
perform the most basic calls until we take over the trap
table from the firmware/hypervisor on the new cpu.
This means no accesses to %g4, %g5, %g6 since those can't be
TLB translated without our trap handlers.
In order to achieve this:
1) Change sun4v_init_mondo_queues() so that it can operate in
several modes.
It can allocate the queues, or install them in the current
processor, or both.
The boot cpu does both in it's call early on.
Later, the boot cpu allocates the sibling cpu queue, starts
the sibling cpu, then the sibling cpu loads them in.
2) init_cur_cpu_trap() is changed to take the current_thread_info()
as an argument instead of reading %g6 directly on the current
cpu.
3) Create a trampoline stack for the sibling cpus. We do our basic
kernel calls using this stack, which is locked into the kernel
image, then go to our proper thread stack after taking over the
trap table.
4) While we are in this delicate startup state, we put 0xdeadbeef
into %g4/%g5/%g6 in order to catch accidental accesses.
5) On the final prom_set_trap_table*() call, we put &init_thread_union
into %g6. This is a hack to make prom_world(0) work. All that
wants to do is restore the %asi register using
get_thread_current_ds().
Longer term we should just do the OBP calls to set the trap table by
hand just like we do for everything else. This would avoid that silly
prom_world(0) issue, then we can remove the init_thread_union hack.
Signed-off-by: David S. Miller <davem@davemloft.net>
2006-02-17 12:29:17 +03:00
|
|
|
init_cur_cpu_trap(current_thread_info());
|
2006-02-27 10:32:33 +03:00
|
|
|
|
|
|
|
paging_init();
|
2011-07-29 10:31:26 +04:00
|
|
|
init_sparc64_elf_hwcap();
|
2005-04-17 02:20:36 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
extern int stop_a_enabled;
|
|
|
|
|
|
|
|
void sun_do_break(void)
|
|
|
|
{
|
|
|
|
if (!stop_a_enabled)
|
|
|
|
return;
|
|
|
|
|
|
|
|
prom_printf("\n");
|
|
|
|
flush_user_windows();
|
|
|
|
|
|
|
|
prom_cmdline();
|
|
|
|
}
|
2009-01-09 03:58:20 +03:00
|
|
|
EXPORT_SYMBOL(sun_do_break);
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
int stop_a_enabled = 1;
|
2009-01-09 03:58:20 +03:00
|
|
|
EXPORT_SYMBOL(stop_a_enabled);
|