2005-11-10 17:26:53 +03:00
|
|
|
/*
|
OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 08:09:12 +03:00
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* OMAP clock: data structure definitions, function prototypes, shared macros
|
2005-11-10 17:26:53 +03:00
|
|
|
*
|
OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 08:09:12 +03:00
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* Copyright (C) 2004-2005, 2008-2010 Nokia Corporation
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* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
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2005-11-10 17:26:53 +03:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ARCH_ARM_OMAP_CLOCK_H
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#define __ARCH_ARM_OMAP_CLOCK_H
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2009-12-09 02:21:29 +03:00
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#include <linux/list.h>
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2005-11-10 17:26:53 +03:00
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struct module;
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2008-03-18 11:35:15 +03:00
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struct clk;
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2008-08-19 12:08:44 +04:00
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struct clockdomain;
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2008-03-18 11:35:15 +03:00
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2010-07-27 02:34:27 +04:00
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/**
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* struct clkops - some clock function pointers
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* @enable: fn ptr that enables the current clock in hardware
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* @disable: fn ptr that enables the current clock in hardware
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* @find_idlest: function returning the IDLEST register for the clock's IP blk
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* @find_companion: function returning the "companion" clk reg for the clock
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2011-02-26 01:49:00 +03:00
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* @allow_idle: fn ptr that enables autoidle for the current clock in hardware
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* @deny_idle: fn ptr that disables autoidle for the current clock in hardware
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2010-07-27 02:34:27 +04:00
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*
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* A "companion" clk is an accompanying clock to the one being queried
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* that must be enabled for the IP module connected to the clock to
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* become accessible by the hardware. Neither @find_idlest nor
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* @find_companion should be needed; that information is IP
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* block-specific; the hwmod code has been created to handle this, but
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* until hwmod data is ready and drivers have been converted to use PM
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* runtime calls in place of clk_enable()/clk_disable(), @find_idlest and
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* @find_companion must, unfortunately, remain.
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*/
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2008-11-04 17:02:46 +03:00
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struct clkops {
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int (*enable)(struct clk *);
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void (*disable)(struct clk *);
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2010-02-24 22:05:54 +03:00
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void (*find_idlest)(struct clk *, void __iomem **,
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u8 *, u8 *);
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void (*find_companion)(struct clk *, void __iomem **,
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u8 *);
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2011-02-26 01:49:00 +03:00
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void (*allow_idle)(struct clk *);
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void (*deny_idle)(struct clk *);
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2008-11-04 17:02:46 +03:00
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};
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2010-02-12 23:26:48 +03:00
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#ifdef CONFIG_ARCH_OMAP2PLUS
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2008-03-18 11:35:15 +03:00
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2010-07-27 02:34:27 +04:00
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/* struct clksel_rate.flags possibilities */
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#define RATE_IN_242X (1 << 0)
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#define RATE_IN_243X (1 << 1)
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OMAP3: clock: clarify usage of struct clksel_rate.flags and struct omap_clk.cpu
Clarify the usage of the struct omap_clk.cpu flags (e.g., CK_*) to use
bits only for individual SoC variants (e.g., CK_3430ES1, CK_3505,
etc.). Superset flags, such as CK_3XXX or CK_AM35XX, are now defined
as disjunctions of individual SoC variant flags. This simplifies the
definition and use of these flags. struct omap_clk record definitions
can now simply specify the bitmask of actual SoCs that the records are
valid for. The clock init code can simply set a single CPU type mask
bit for the SoC that is currently in use, and test against that,
rather than needing to set some combination of flags.
Similarly, clarify the use of struct clksel_rate.flags. The bit
allocated for RATE_IN_3XXX has been reassigned, and RATE_IN_3XXX has
been defined as a disjunction of the 34xx and 36xx rate flags. The
advantages are the same as the above.
Clarify the usage of struct omap_clk.cpu flags such as CK_34XX to only
apply to the SoCs that they name, e.g., OMAP34xx chips. The previous
practice caused significantly different SoCs, such as OMAP36xx, to be
included in CK_34XX. In my opinion, this is much more intuitive.
Similarly, clarify the use of struct clksel_rate.flags, such that
RATE_IN_3430ES2PLUS now only applies to 34xx chips with ES level >= 2
- it does not apply to OMAP36xx.
...
At some point, it probably makes sense to collapse the CK_* and
RATE_IN_* flags together into a single bitfield, and possibly use the
existing CHIP_IS_OMAP* flags for platform detection.
...
This all seems to work fine on OMAP34xx and OMAP36xx Beagle. Not sure
if it works on Sitara or the TI816X, unfortunately I don't have any
here to test with.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-12-22 07:08:14 +03:00
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#define RATE_IN_3430ES1 (1 << 2) /* 3430ES1 rates only */
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#define RATE_IN_3430ES2PLUS (1 << 3) /* 3430 ES >= 2 rates only */
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2010-07-27 02:34:27 +04:00
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#define RATE_IN_36XX (1 << 4)
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#define RATE_IN_4430 (1 << 5)
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2011-02-16 19:31:39 +03:00
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#define RATE_IN_TI816X (1 << 6)
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2011-07-02 06:30:24 +04:00
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#define RATE_IN_4460 (1 << 7)
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2011-12-13 22:46:43 +04:00
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#define RATE_IN_AM33XX (1 << 8)
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2011-12-13 22:46:45 +04:00
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#define RATE_IN_TI814X (1 << 9)
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2010-07-27 02:34:27 +04:00
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#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
|
OMAP3: clock: clarify usage of struct clksel_rate.flags and struct omap_clk.cpu
Clarify the usage of the struct omap_clk.cpu flags (e.g., CK_*) to use
bits only for individual SoC variants (e.g., CK_3430ES1, CK_3505,
etc.). Superset flags, such as CK_3XXX or CK_AM35XX, are now defined
as disjunctions of individual SoC variant flags. This simplifies the
definition and use of these flags. struct omap_clk record definitions
can now simply specify the bitmask of actual SoCs that the records are
valid for. The clock init code can simply set a single CPU type mask
bit for the SoC that is currently in use, and test against that,
rather than needing to set some combination of flags.
Similarly, clarify the use of struct clksel_rate.flags. The bit
allocated for RATE_IN_3XXX has been reassigned, and RATE_IN_3XXX has
been defined as a disjunction of the 34xx and 36xx rate flags. The
advantages are the same as the above.
Clarify the usage of struct omap_clk.cpu flags such as CK_34XX to only
apply to the SoCs that they name, e.g., OMAP34xx chips. The previous
practice caused significantly different SoCs, such as OMAP36xx, to be
included in CK_34XX. In my opinion, this is much more intuitive.
Similarly, clarify the use of struct clksel_rate.flags, such that
RATE_IN_3430ES2PLUS now only applies to 34xx chips with ES level >= 2
- it does not apply to OMAP36xx.
...
At some point, it probably makes sense to collapse the CK_* and
RATE_IN_* flags together into a single bitfield, and possibly use the
existing CHIP_IS_OMAP* flags for platform detection.
...
This all seems to work fine on OMAP34xx and OMAP36xx Beagle. Not sure
if it works on Sitara or the TI816X, unfortunately I don't have any
here to test with.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-12-22 07:08:14 +03:00
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#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
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#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
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2011-07-02 06:30:24 +04:00
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#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
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OMAP3: clock: clarify usage of struct clksel_rate.flags and struct omap_clk.cpu
Clarify the usage of the struct omap_clk.cpu flags (e.g., CK_*) to use
bits only for individual SoC variants (e.g., CK_3430ES1, CK_3505,
etc.). Superset flags, such as CK_3XXX or CK_AM35XX, are now defined
as disjunctions of individual SoC variant flags. This simplifies the
definition and use of these flags. struct omap_clk record definitions
can now simply specify the bitmask of actual SoCs that the records are
valid for. The clock init code can simply set a single CPU type mask
bit for the SoC that is currently in use, and test against that,
rather than needing to set some combination of flags.
Similarly, clarify the use of struct clksel_rate.flags. The bit
allocated for RATE_IN_3XXX has been reassigned, and RATE_IN_3XXX has
been defined as a disjunction of the 34xx and 36xx rate flags. The
advantages are the same as the above.
Clarify the usage of struct omap_clk.cpu flags such as CK_34XX to only
apply to the SoCs that they name, e.g., OMAP34xx chips. The previous
practice caused significantly different SoCs, such as OMAP36xx, to be
included in CK_34XX. In my opinion, this is much more intuitive.
Similarly, clarify the use of struct clksel_rate.flags, such that
RATE_IN_3430ES2PLUS now only applies to 34xx chips with ES level >= 2
- it does not apply to OMAP36xx.
...
At some point, it probably makes sense to collapse the CK_* and
RATE_IN_* flags together into a single bitfield, and possibly use the
existing CHIP_IS_OMAP* flags for platform detection.
...
This all seems to work fine on OMAP34xx and OMAP36xx Beagle. Not sure
if it works on Sitara or the TI816X, unfortunately I don't have any
here to test with.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2010-12-22 07:08:14 +03:00
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/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
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#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
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2010-07-27 02:34:27 +04:00
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/**
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* struct clksel_rate - register bitfield values corresponding to clk divisors
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* @val: register bitfield value (shifted to bit 0)
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* @div: clock divisor corresponding to @val
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* @flags: (see "struct clksel_rate.flags possibilities" above)
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*
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* @val should match the value of a read from struct clk.clksel_reg
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* AND'ed with struct clk.clksel_mask, shifted right to bit 0.
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*
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* @div is the divisor that should be applied to the parent clock's rate
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* to produce the current clock's rate.
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*/
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2008-03-18 11:35:15 +03:00
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struct clksel_rate {
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u32 val;
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2008-11-05 00:50:46 +03:00
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u8 div;
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2011-12-13 22:46:43 +04:00
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u16 flags;
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2008-03-18 11:35:15 +03:00
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};
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2010-07-27 02:34:27 +04:00
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/**
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* struct clksel - available parent clocks, and a pointer to their divisors
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* @parent: struct clk * to a possible parent clock
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* @rates: available divisors for this parent clock
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*
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* A struct clksel is always associated with one or more struct clks
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* and one or more struct clksel_rates.
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*/
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2008-03-18 11:35:15 +03:00
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struct clksel {
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struct clk *parent;
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const struct clksel_rate *rates;
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};
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|
OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 08:09:12 +03:00
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/**
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* struct dpll_data - DPLL registers and integration data
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* @mult_div1_reg: register containing the DPLL M and N bitfields
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* @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
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* @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
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* @clk_bypass: struct clk pointer to the clock's bypass clock input
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* @clk_ref: struct clk pointer to the clock's reference clock input
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* @control_reg: register containing the DPLL mode bitfield
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* @enable_mask: mask of the DPLL mode bitfield in @control_reg
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* @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
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* @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
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* @max_multiplier: maximum valid non-bypass multiplier value (actual)
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* @last_rounded_n: cache of the last N result of omap2_dpll_round_rate()
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* @min_divider: minimum valid non-bypass divider value (actual)
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* @max_divider: maximum valid non-bypass divider value (actual)
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* @modes: possible values of @enable_mask
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* @autoidle_reg: register containing the DPLL autoidle mode bitfield
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* @idlest_reg: register containing the DPLL idle status bitfield
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* @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
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* @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
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* @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
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* @auto_recal_bit: bitshift of the driftguard enable bit in @control_reg
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* @recal_en_bit: bitshift of the PRM_IRQENABLE_* bit for recalibration IRQs
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* @recal_st_bit: bitshift of the PRM_IRQSTATUS_* bit for recalibration IRQs
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* @flags: DPLL type/features (see below)
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*
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* Possible values for @flags:
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* DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
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2010-12-22 07:31:43 +03:00
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*
|
OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 08:09:12 +03:00
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* @freqsel_mask is only used on the OMAP34xx family and AM35xx.
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*
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* XXX Some DPLLs have multiple bypass inputs, so it's not technically
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* correct to only have one @clk_bypass pointer.
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*
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* XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
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* @last_rounded_n) should be separated from the runtime-fixed fields
|
2011-02-17 01:38:39 +03:00
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|
|
* and placed into a different structure, so that the runtime-fixed data
|
OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 08:09:12 +03:00
|
|
|
* can be placed into read-only space.
|
2010-02-23 08:09:08 +03:00
|
|
|
*/
|
2008-03-18 11:35:15 +03:00
|
|
|
struct dpll_data {
|
|
|
|
void __iomem *mult_div1_reg;
|
|
|
|
u32 mult_mask;
|
|
|
|
u32 div1_mask;
|
[ARM] omap: add support for bypassing DPLLs
This roughly corresponds with OMAP commits: 7d06c48, 3241b19,
88b5d9b, 18a5500, 9c909ac, 5c6497b, 8b1f0bd, 2ac1da8.
For both OMAP2 and OMAP3, we note the reference and bypass clocks in
the DPLL data structure. Whenever we modify the DPLL rate, we first
ensure that both the reference and bypass clocks are enabled. Then,
we decide whether to use the reference and DPLL, or the bypass clock
if the desired rate is identical to the bypass rate, and program the
DPLL appropriately. Finally, we update the clock's parent, and then
disable the unused clocks.
This keeps the parents correctly balanced, and more importantly ensures
that the bypass clock is running whenever we reprogram the DPLL. This
is especially important because the procedure for reprogramming the DPLL
involves switching to the bypass clock.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2009-02-19 16:29:22 +03:00
|
|
|
struct clk *clk_bypass;
|
|
|
|
struct clk *clk_ref;
|
|
|
|
void __iomem *control_reg;
|
|
|
|
u32 enable_mask;
|
2008-11-05 00:50:46 +03:00
|
|
|
unsigned long last_rounded_rate;
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 13:24:46 +04:00
|
|
|
u16 last_rounded_m;
|
OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 08:09:12 +03:00
|
|
|
u16 max_multiplier;
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 13:24:46 +04:00
|
|
|
u8 last_rounded_n;
|
2009-01-28 22:08:44 +03:00
|
|
|
u8 min_divider;
|
2011-07-10 05:14:46 +04:00
|
|
|
u16 max_divider;
|
2008-07-03 13:24:45 +04:00
|
|
|
u8 modes;
|
OMAP2/3/4 clock: fix DPLL multiplier value errors; also copyrights, includes, documentation
The maximum DPLL multiplier (M) values for OMAP2xxx and OMAP3xxx are
one increment higher than they should be. See for example the
OMAP242x TRM Rev X Section 5.10.6 "Clock Generator Registers" and the
OMAP36xx TRM Rev C Table 3-202 "CM_CLKSEL1_PLL". Programming a 0 into
the DPLL's M register bitfield is valid for OMAP2/3 and indicates that
the DPLL should enter MN-bypass mode. Also, increase the minimum
multiplier (M) value for the DPLL rate rounding code from 1 to 2, to
ensure that it does not inadvertently put the DPLL into bypass.
Note that the register documentation in the OMAP2xxx and OMAP3xxx TRMs
does not make clear that the actual DPLL divider value (the "N") is
the content of the appropriate register bitfield for the N value,
_plus one_. (In other words, an N register bitfield of 0 indicates a
DPLL divider value of 1.) This is only clearly documented in the
OMAP4430 TRM, in, for example, OMAP4430 TRM Rev A Table 3-1167
"CM_CLKSEL_DPLL_USB".
While here, update copyrights, add kerneldoc for struct dpll_data,
drop the unused struct dpll_data.max_tolerance field, remove some
unnecessary #includes in DPLL-related code, and replace the #include
of <linux/module.h> with <linux/list.h>, which is what was really
needed. The OMAP4 clock autogenerator script has been updated
accordingly.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
2010-02-23 08:09:12 +03:00
|
|
|
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
|
2008-11-05 00:50:46 +03:00
|
|
|
void __iomem *autoidle_reg;
|
|
|
|
void __iomem *idlest_reg;
|
|
|
|
u32 autoidle_mask;
|
2009-01-28 05:12:47 +03:00
|
|
|
u32 freqsel_mask;
|
2009-01-28 22:08:17 +03:00
|
|
|
u32 idlest_mask;
|
2010-12-22 07:31:43 +03:00
|
|
|
u32 dco_mask;
|
|
|
|
u32 sddiv_mask;
|
2008-03-18 12:24:28 +03:00
|
|
|
u8 auto_recal_bit;
|
|
|
|
u8 recal_en_bit;
|
|
|
|
u8 recal_st_bit;
|
|
|
|
# endif
|
2011-11-11 00:12:55 +04:00
|
|
|
u8 flags;
|
2008-03-18 11:35:15 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
#endif
|
2005-11-10 17:26:53 +03:00
|
|
|
|
2011-02-26 01:49:01 +03:00
|
|
|
/*
|
|
|
|
* struct clk.flags possibilities
|
|
|
|
*
|
|
|
|
* XXX document the rest of the clock flags here
|
|
|
|
*
|
|
|
|
* CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
|
|
|
|
* bits share the same register. This flag allows the
|
|
|
|
* omap4_dpllmx*() code to determine which GATE_CTRL bit field
|
|
|
|
* should be used. This is a temporary solution - a better approach
|
|
|
|
* would be to associate clock type-specific data with the clock,
|
|
|
|
* similar to the struct dpll_data approach.
|
|
|
|
*/
|
2010-07-27 02:34:27 +04:00
|
|
|
#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */
|
|
|
|
#define CLOCK_IDLE_CONTROL (1 << 1)
|
|
|
|
#define CLOCK_NO_IDLE_PARENT (1 << 2)
|
|
|
|
#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */
|
|
|
|
#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */
|
2011-02-26 01:49:01 +03:00
|
|
|
#define CLOCK_CLKOUTX2 (1 << 5)
|
2010-07-27 02:34:27 +04:00
|
|
|
|
|
|
|
/**
|
|
|
|
* struct clk - OMAP struct clk
|
|
|
|
* @node: list_head connecting this clock into the full clock list
|
|
|
|
* @ops: struct clkops * for this clock
|
|
|
|
* @name: the name of the clock in the hardware (used in hwmod data and debug)
|
|
|
|
* @parent: pointer to this clock's parent struct clk
|
|
|
|
* @children: list_head connecting to the child clks' @sibling list_heads
|
|
|
|
* @sibling: list_head connecting this clk to its parent clk's @children
|
|
|
|
* @rate: current clock rate
|
|
|
|
* @enable_reg: register to write to enable the clock (see @enable_bit)
|
|
|
|
* @recalc: fn ptr that returns the clock's current rate
|
|
|
|
* @set_rate: fn ptr that can change the clock's current rate
|
|
|
|
* @round_rate: fn ptr that can round the clock's current rate
|
|
|
|
* @init: fn ptr to do clock-specific initialization
|
|
|
|
* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
|
|
|
|
* @usecount: number of users that have requested this clock to be enabled
|
|
|
|
* @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div
|
|
|
|
* @flags: see "struct clk.flags possibilities" above
|
|
|
|
* @clksel_reg: for clksel clks, register va containing src/divisor select
|
|
|
|
* @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
|
|
|
|
* @clksel: for clksel clks, pointer to struct clksel for this clock
|
|
|
|
* @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
|
|
|
|
* @clkdm_name: clockdomain name that this clock is contained in
|
|
|
|
* @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
|
|
|
|
* @rate_offset: bitshift for rate selection bitfield (OMAP1 only)
|
|
|
|
* @src_offset: bitshift for source selection bitfield (OMAP1 only)
|
|
|
|
*
|
|
|
|
* XXX @rate_offset, @src_offset should probably be removed and OMAP1
|
|
|
|
* clock code converted to use clksel.
|
|
|
|
*
|
|
|
|
* XXX @usecount is poorly named. It should be "enable_count" or
|
|
|
|
* something similar. "users" in the description refers to kernel
|
|
|
|
* code (core code or drivers) that have called clk_enable() and not
|
|
|
|
* yet called clk_disable(); the usecount of parent clocks is also
|
|
|
|
* incremented by the clock code when clk_enable() is called on child
|
|
|
|
* clocks and decremented by the clock code when clk_disable() is
|
|
|
|
* called on child clocks.
|
|
|
|
*
|
|
|
|
* XXX @clkdm, @usecount, @children, @sibling should be marked for
|
|
|
|
* internal use only.
|
|
|
|
*
|
|
|
|
* @children and @sibling are used to optimize parent-to-child clock
|
|
|
|
* tree traversals. (child-to-parent traversals use @parent.)
|
|
|
|
*
|
|
|
|
* XXX The notion of the clock's current rate probably needs to be
|
|
|
|
* separated from the clock's target rate.
|
|
|
|
*/
|
2005-11-10 17:26:53 +03:00
|
|
|
struct clk {
|
|
|
|
struct list_head node;
|
2008-11-04 17:02:46 +03:00
|
|
|
const struct clkops *ops;
|
2005-11-10 17:26:53 +03:00
|
|
|
const char *name;
|
|
|
|
struct clk *parent;
|
2009-01-31 13:05:51 +03:00
|
|
|
struct list_head children;
|
|
|
|
struct list_head sibling; /* node for children */
|
2005-11-10 17:26:53 +03:00
|
|
|
unsigned long rate;
|
|
|
|
void __iomem *enable_reg;
|
2009-02-12 13:12:59 +03:00
|
|
|
unsigned long (*recalc)(struct clk *);
|
2005-11-10 17:26:53 +03:00
|
|
|
int (*set_rate)(struct clk *, unsigned long);
|
|
|
|
long (*round_rate)(struct clk *, unsigned long);
|
|
|
|
void (*init)(struct clk *);
|
2010-07-27 02:34:27 +04:00
|
|
|
u8 enable_bit;
|
|
|
|
s8 usecount;
|
2010-01-27 06:12:57 +03:00
|
|
|
u8 fixed_div;
|
2010-02-23 08:09:18 +03:00
|
|
|
u8 flags;
|
2010-02-12 23:26:48 +03:00
|
|
|
#ifdef CONFIG_ARCH_OMAP2PLUS
|
2008-03-18 11:35:15 +03:00
|
|
|
void __iomem *clksel_reg;
|
|
|
|
u32 clksel_mask;
|
|
|
|
const struct clksel *clksel;
|
ARM: OMAP2: Clock: New OMAP2/3 DPLL rate rounding algorithm
This patch adds a new rate rounding algorithm for DPLL clocks on the
OMAP2/3 architecture.
For a desired DPLL target rate, there may be several
multiplier/divider (M, N) values which will generate a sufficiently
close rate. Lower N values result in greater power economy. However,
lower N values can cause the difference between the rounded rate and
the target rate ("rate error") to be larger than it would be with a
higher N. This can cause downstream devices to run more slowly than
they otherwise would.
This DPLL rate rounding algorithm:
- attempts to find the lowest possible N (DPLL divider) to reach the
target_rate (since, according to Richard Woodruff <r-woodruff@ti.com>,
lower N values save more power than higher N values).
- allows developers to set an upper bound on the error between the
rounded rate and the desired target rate ("rate tolerance"), so an
appropriate balance between rate fidelity and power savings can be
set. This maximum rate error tolerance is set via
omap2_set_dpll_rate_tolerance().
- never returns a rounded rate higher than the target rate.
The rate rounding algorithm caches the last rounded M, N, and rate
computation to avoid rounding the rate twice for each clk_set_rate()
call. (This patch does not yet implement set_rate for DPLLs; that
follows in a future patch.)
The algorithm trades execution speed for rate accuracy. It will find
the (M, N) set that results in the least rate error, within a
specified rate tolerance. It does this by evaluating each divider
setting - on OMAP3, this involves 128 steps. Another approach to DPLL
rate rounding would be to bail out as soon as a valid rate is found
within the rate tolerance, which would trade rate accuracy for
execution speed. Alternate implementations welcome.
This code is not yet used by the OMAP24XX DPLL clock, since it
is currently defined as a composite clock, fusing the DPLL M,N and the
M2 output divider. This patch also renames the existing OMAP24xx DPLL
programming functions to highlight that they program both the DPLL and
the DPLL's output multiplier.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2008-07-03 13:24:46 +04:00
|
|
|
struct dpll_data *dpll_data;
|
2008-08-19 12:08:44 +04:00
|
|
|
const char *clkdm_name;
|
|
|
|
struct clockdomain *clkdm;
|
2008-03-18 11:35:15 +03:00
|
|
|
#else
|
2010-07-27 02:34:27 +04:00
|
|
|
u8 rate_offset;
|
|
|
|
u8 src_offset;
|
2008-03-18 11:35:15 +03:00
|
|
|
#endif
|
2008-07-03 13:24:41 +04:00
|
|
|
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
|
|
|
|
struct dentry *dent; /* For visible tree hierarchy */
|
|
|
|
#endif
|
2005-11-10 17:26:53 +03:00
|
|
|
};
|
|
|
|
|
2008-05-22 19:38:50 +04:00
|
|
|
struct cpufreq_frequency_table;
|
|
|
|
|
2005-11-10 17:26:53 +03:00
|
|
|
struct clk_functions {
|
|
|
|
int (*clk_enable)(struct clk *clk);
|
|
|
|
void (*clk_disable)(struct clk *clk);
|
|
|
|
long (*clk_round_rate)(struct clk *clk, unsigned long rate);
|
|
|
|
int (*clk_set_rate)(struct clk *clk, unsigned long rate);
|
|
|
|
int (*clk_set_parent)(struct clk *clk, struct clk *parent);
|
|
|
|
void (*clk_allow_idle)(struct clk *clk);
|
|
|
|
void (*clk_deny_idle)(struct clk *clk);
|
2006-09-25 14:27:20 +04:00
|
|
|
void (*clk_disable_unused)(struct clk *clk);
|
2008-05-22 19:38:50 +04:00
|
|
|
#ifdef CONFIG_CPU_FREQ
|
|
|
|
void (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
|
2010-01-09 01:23:16 +03:00
|
|
|
void (*clk_exit_cpufreq_table)(struct cpufreq_frequency_table **);
|
2008-05-22 19:38:50 +04:00
|
|
|
#endif
|
2005-11-10 17:26:53 +03:00
|
|
|
};
|
|
|
|
|
2010-01-27 06:13:11 +03:00
|
|
|
extern int mpurate;
|
2005-11-10 17:26:53 +03:00
|
|
|
|
2009-01-28 05:12:50 +03:00
|
|
|
extern int clk_init(struct clk_functions *custom_clocks);
|
2009-05-13 03:50:30 +04:00
|
|
|
extern void clk_preinit(struct clk *clk);
|
2005-11-10 17:26:53 +03:00
|
|
|
extern int clk_register(struct clk *clk);
|
2009-01-31 13:05:51 +03:00
|
|
|
extern void clk_reparent(struct clk *child, struct clk *parent);
|
2005-11-10 17:26:53 +03:00
|
|
|
extern void clk_unregister(struct clk *clk);
|
|
|
|
extern void propagate_rate(struct clk *clk);
|
2008-03-18 11:35:15 +03:00
|
|
|
extern void recalculate_root_clocks(void);
|
2009-02-12 13:12:59 +03:00
|
|
|
extern unsigned long followparent_recalc(struct clk *clk);
|
2008-03-18 11:35:15 +03:00
|
|
|
extern void clk_enable_init_clocks(void);
|
2010-01-27 06:12:57 +03:00
|
|
|
unsigned long omap_fixed_divisor_recalc(struct clk *clk);
|
2009-01-28 05:13:38 +03:00
|
|
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#ifdef CONFIG_CPU_FREQ
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extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
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2010-01-09 01:23:16 +03:00
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extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
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2009-01-28 05:13:38 +03:00
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#endif
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2010-02-23 08:09:29 +03:00
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extern struct clk *omap_clk_get_by_name(const char *name);
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2011-02-26 01:49:00 +03:00
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extern int omap_clk_enable_autoidle_all(void);
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extern int omap_clk_disable_autoidle_all(void);
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2005-11-10 17:26:53 +03:00
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2008-11-04 19:35:03 +03:00
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extern const struct clkops clkops_null;
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2010-02-23 08:09:40 +03:00
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extern struct clk dummy_ck;
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2005-11-10 17:26:53 +03:00
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#endif
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