2019-05-27 09:55:05 +03:00
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// SPDX-License-Identifier: GPL-2.0-or-later
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2007-05-08 04:33:32 +04:00
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/*
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* Driver for OHCI 1394 controllers
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2006-12-20 03:58:35 +03:00
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*
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* Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
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*/
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2010-11-29 05:09:50 +03:00
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#include <linux/bitops.h>
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2010-06-12 22:26:51 +04:00
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#include <linux/bug.h>
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2007-08-20 23:58:30 +04:00
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#include <linux/compiler.h>
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2006-12-20 03:58:35 +03:00
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#include <linux/delay.h>
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2009-06-04 23:09:38 +04:00
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#include <linux/device.h>
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2006-12-28 01:36:37 +03:00
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#include <linux/dma-mapping.h>
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firewire: reorganize header files
The three header files of firewire-core, i.e.
"drivers/firewire/fw-device.h",
"drivers/firewire/fw-topology.h",
"drivers/firewire/fw-transaction.h",
are replaced by
"drivers/firewire/core.h",
"include/linux/firewire.h".
The latter includes everything which a firewire high-level driver (like
firewire-sbp2) needs besides linux/firewire-constants.h, while core.h
contains the rest which is needed by firewire-core itself and by low-
level drivers (card drivers) like firewire-ohci.
High-level drivers can now also reside outside of drivers/firewire
without having to add drivers/firewire to the header file search path in
makefiles. At least the firedtv driver will be such a driver.
I also considered to spread the contents of core.h over several files,
one for each .c file where the respective implementation resides. But
it turned out that most core .c files will end up including most of the
core .h files. Also, the combined core.h isn't unreasonably big, and it
will lose more of its contents to linux/firewire.h anyway soon when more
firewire drivers are added. (IP-over-1394, firedtv, and there are plans
for one or two more.)
Furthermore, fw-ohci.h is renamed to ohci.h. The name of core.h and
ohci.h is chosen with regard to name changes of the .c files in a
follow-up change.
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2009-06-05 18:26:18 +04:00
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#include <linux/firewire.h>
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2009-06-04 23:09:38 +04:00
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#include <linux/firewire-constants.h>
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2007-08-20 23:41:22 +04:00
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#include <linux/init.h>
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#include <linux/interrupt.h>
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2009-06-04 23:09:38 +04:00
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#include <linux/io.h>
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2007-08-20 23:41:22 +04:00
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#include <linux/kernel.h>
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2009-06-04 23:09:38 +04:00
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#include <linux/list.h>
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2007-05-15 23:36:10 +04:00
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#include <linux/mm.h>
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2007-08-20 23:41:22 +04:00
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#include <linux/module.h>
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2008-03-21 00:04:36 +03:00
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#include <linux/moduleparam.h>
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2010-07-08 18:09:06 +04:00
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#include <linux/mutex.h>
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2007-08-20 23:41:22 +04:00
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#include <linux/pci.h>
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2009-08-28 15:25:15 +04:00
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#include <linux/pci_ids.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 11:04:11 +03:00
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#include <linux/slab.h>
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2007-08-20 23:40:30 +04:00
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#include <linux/spinlock.h>
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2009-06-04 23:09:38 +04:00
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#include <linux/string.h>
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2010-08-02 11:33:25 +04:00
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#include <linux/time.h>
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2010-11-26 10:57:31 +03:00
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#include <linux/vmalloc.h>
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2011-07-26 00:16:24 +04:00
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#include <linux/workqueue.h>
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2006-12-28 01:36:37 +03:00
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2009-06-04 23:09:38 +04:00
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#include <asm/byteorder.h>
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2007-08-20 23:40:30 +04:00
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#include <asm/page.h>
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2006-12-20 03:58:35 +03:00
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2008-03-01 04:42:56 +03:00
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#ifdef CONFIG_PPC_PMAC
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#include <asm/pmac_feature.h>
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#endif
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firewire: reorganize header files
The three header files of firewire-core, i.e.
"drivers/firewire/fw-device.h",
"drivers/firewire/fw-topology.h",
"drivers/firewire/fw-transaction.h",
are replaced by
"drivers/firewire/core.h",
"include/linux/firewire.h".
The latter includes everything which a firewire high-level driver (like
firewire-sbp2) needs besides linux/firewire-constants.h, while core.h
contains the rest which is needed by firewire-core itself and by low-
level drivers (card drivers) like firewire-ohci.
High-level drivers can now also reside outside of drivers/firewire
without having to add drivers/firewire to the header file search path in
makefiles. At least the firedtv driver will be such a driver.
I also considered to spread the contents of core.h over several files,
one for each .c file where the respective implementation resides. But
it turned out that most core .c files will end up including most of the
core .h files. Also, the combined core.h isn't unreasonably big, and it
will lose more of its contents to linux/firewire.h anyway soon when more
firewire drivers are added. (IP-over-1394, firedtv, and there are plans
for one or two more.)
Furthermore, fw-ohci.h is renamed to ohci.h. The name of core.h and
ohci.h is chosen with regard to name changes of the .c files in a
follow-up change.
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2009-06-05 18:26:18 +04:00
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#include "core.h"
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#include "ohci.h"
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2006-12-20 03:58:35 +03:00
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2013-03-26 19:54:06 +04:00
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#define ohci_info(ohci, f, args...) dev_info(ohci->card.device, f, ##args)
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#define ohci_notice(ohci, f, args...) dev_notice(ohci->card.device, f, ##args)
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#define ohci_err(ohci, f, args...) dev_err(ohci->card.device, f, ##args)
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2007-05-08 04:33:35 +04:00
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#define DESCRIPTOR_OUTPUT_MORE 0
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#define DESCRIPTOR_OUTPUT_LAST (1 << 12)
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#define DESCRIPTOR_INPUT_MORE (2 << 12)
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#define DESCRIPTOR_INPUT_LAST (3 << 12)
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#define DESCRIPTOR_STATUS (1 << 11)
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#define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
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#define DESCRIPTOR_PING (1 << 7)
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#define DESCRIPTOR_YY (1 << 6)
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#define DESCRIPTOR_NO_IRQ (0 << 4)
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#define DESCRIPTOR_IRQ_ERROR (1 << 4)
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#define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
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#define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
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#define DESCRIPTOR_WAIT (3 << 0)
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2006-12-20 03:58:35 +03:00
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firewire: ohci: fix VIA VT6306 video reception
Add quirk for VT6306 wake bit behavior.
VT6306 seems to reread the wrong descriptor when the wake bit is
written. work around by putting a copy of the branch address in the
first descriptor of the block.
[Stefan R: This fixes the known broken video reception via gstreamer
on VIA VT6306. 100% repeatable testcase:
$ gst-launch-0.10 dv1394src \! dvdemux \! dvdec \! xvimagesink
with a camcorder or other DV source connected. Likewise for MPEG2-TS
reception via gstreamer, e.g. from TV settop boxes.
Perhaps this also fixes dv4l on VT6306, but this is as yet untested.
Kino, dvgrab or FFADO had not been affected by this chip quirk.
Additional comments from Andy:]
I've looked into some problems with the wake bit on a vt6306 family
chip (1106:3044, rev 46).
I used this firewire card in a mythtv setup (ISO receive MPEG2 stream)
with Debian 2.6.32 kernels for ~2 years without problems.
Since upgrading to 3.2, I've been having problems with the input stream
freezing -- input data stops until I restart mythtv (I expect closing
and reopening the device would be sufficient). This happens
infrequently, maybe one out of 20 recordings. I eventually determined
that the problem is more likely to occur if the system is loaded.
I isolated the kernel version as the triggering SW factor and then
specifically the change from dualbuffer back to packet-per-buffer DMA
mode.
The possibility that the controller does not properly respond to the
wake bit was suggested in
https://bugzilla.redhat.com/show_bug.cgi?id=415841, but not proven.
Based on the fact that dualbuffer mode worked while packet-per-buffer
has trouble, I guessed that upon seeing the wake bit written, the vt6306
controller only checks the branch address in the first descriptor of the
block, even if that is not the correct place to look (because the block
has multiple descriptors).
This theory seems to be correct. When the ISO reception is hung, I am
able to resume it by manually writing the branch address to the first
descriptor in the block, and then writing the wake bit.
I've had luck so far with the attached patch, so I'm including it. It's
probably not a complete solution -- I haven't tested transmit modes to
see whether they have a similar issue.
I doubt that the quirk test is any cheaper than just writing the extra
branch address in all cases, but it does reduce the risk of breaking
other hardware.
[Stefan R: omitted QUIRK_NO_MSI from VT6306 quirks table entry,
changed whitespace]
Signed-off-by: Andy Leiserson <andy@leiserson.org>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2013-04-24 20:10:32 +04:00
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#define DESCRIPTOR_CMD (0xf << 12)
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2006-12-20 03:58:35 +03:00
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struct descriptor {
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__le16 req_count;
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__le16 control;
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__le32 data_address;
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__le32 branch_address;
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__le16 res_count;
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__le16 transfer_status;
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} __attribute__((aligned(16)));
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2007-05-08 04:33:35 +04:00
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#define CONTROL_SET(regs) (regs)
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#define CONTROL_CLEAR(regs) ((regs) + 4)
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#define COMMAND_PTR(regs) ((regs) + 12)
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#define CONTEXT_MATCH(regs) ((regs) + 16)
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2007-02-06 22:49:31 +03:00
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2010-11-26 10:57:31 +03:00
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#define AR_BUFFER_SIZE (32*1024)
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#define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
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/* we need at least two pages for proper list management */
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#define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
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#define MAX_ASYNC_PAYLOAD 4096
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#define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
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#define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
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2006-12-20 03:58:35 +03:00
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2007-02-06 22:49:30 +03:00
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struct ar_context {
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struct fw_ohci *ohci;
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2010-11-26 10:57:31 +03:00
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struct page *pages[AR_BUFFERS];
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void *buffer;
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struct descriptor *descriptors;
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dma_addr_t descriptors_bus;
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2007-02-06 22:49:30 +03:00
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void *pointer;
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2010-11-26 10:57:31 +03:00
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unsigned int last_buffer_index;
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2007-02-06 22:49:31 +03:00
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u32 regs;
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2006-12-20 03:58:35 +03:00
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struct tasklet_struct tasklet;
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};
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2007-02-17 01:34:39 +03:00
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struct context;
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typedef int (*descriptor_callback_t)(struct context *ctx,
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struct descriptor *d,
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struct descriptor *last);
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firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
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/*
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* A buffer that contains a block of DMA-able coherent memory used for
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* storing a portion of a DMA descriptor program.
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*/
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struct descriptor_buffer {
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struct list_head list;
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dma_addr_t buffer_bus;
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size_t buffer_size;
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size_t used;
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2020-05-28 17:35:11 +03:00
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struct descriptor buffer[];
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firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
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};
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2007-02-17 01:34:39 +03:00
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struct context {
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2007-03-04 16:45:18 +03:00
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struct fw_ohci *ohci;
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2007-02-17 01:34:39 +03:00
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u32 regs;
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firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
int total_allocation;
|
2011-10-16 01:12:23 +04:00
|
|
|
u32 current_bus;
|
2010-12-24 16:42:46 +03:00
|
|
|
bool running;
|
2010-12-24 16:40:15 +03:00
|
|
|
bool flushing;
|
2007-03-04 16:45:18 +03:00
|
|
|
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
/*
|
|
|
|
* List of page-sized buffers for storing DMA descriptors.
|
|
|
|
* Head of list contains buffers in use and tail of list contains
|
|
|
|
* free buffers.
|
|
|
|
*/
|
|
|
|
struct list_head buffer_list;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Pointer to a buffer inside buffer_list that contains the tail
|
|
|
|
* end of the current DMA program.
|
|
|
|
*/
|
|
|
|
struct descriptor_buffer *buffer_tail;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The descriptor containing the branch address of the first
|
|
|
|
* descriptor that has not yet been filled by the device.
|
|
|
|
*/
|
|
|
|
struct descriptor *last;
|
|
|
|
|
|
|
|
/*
|
firewire: ohci: fix VIA VT6306 video reception
Add quirk for VT6306 wake bit behavior.
VT6306 seems to reread the wrong descriptor when the wake bit is
written. work around by putting a copy of the branch address in the
first descriptor of the block.
[Stefan R: This fixes the known broken video reception via gstreamer
on VIA VT6306. 100% repeatable testcase:
$ gst-launch-0.10 dv1394src \! dvdemux \! dvdec \! xvimagesink
with a camcorder or other DV source connected. Likewise for MPEG2-TS
reception via gstreamer, e.g. from TV settop boxes.
Perhaps this also fixes dv4l on VT6306, but this is as yet untested.
Kino, dvgrab or FFADO had not been affected by this chip quirk.
Additional comments from Andy:]
I've looked into some problems with the wake bit on a vt6306 family
chip (1106:3044, rev 46).
I used this firewire card in a mythtv setup (ISO receive MPEG2 stream)
with Debian 2.6.32 kernels for ~2 years without problems.
Since upgrading to 3.2, I've been having problems with the input stream
freezing -- input data stops until I restart mythtv (I expect closing
and reopening the device would be sufficient). This happens
infrequently, maybe one out of 20 recordings. I eventually determined
that the problem is more likely to occur if the system is loaded.
I isolated the kernel version as the triggering SW factor and then
specifically the change from dualbuffer back to packet-per-buffer DMA
mode.
The possibility that the controller does not properly respond to the
wake bit was suggested in
https://bugzilla.redhat.com/show_bug.cgi?id=415841, but not proven.
Based on the fact that dualbuffer mode worked while packet-per-buffer
has trouble, I guessed that upon seeing the wake bit written, the vt6306
controller only checks the branch address in the first descriptor of the
block, even if that is not the correct place to look (because the block
has multiple descriptors).
This theory seems to be correct. When the ISO reception is hung, I am
able to resume it by manually writing the branch address to the first
descriptor in the block, and then writing the wake bit.
I've had luck so far with the attached patch, so I'm including it. It's
probably not a complete solution -- I haven't tested transmit modes to
see whether they have a similar issue.
I doubt that the quirk test is any cheaper than just writing the extra
branch address in all cases, but it does reduce the risk of breaking
other hardware.
[Stefan R: omitted QUIRK_NO_MSI from VT6306 quirks table entry,
changed whitespace]
Signed-off-by: Andy Leiserson <andy@leiserson.org>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2013-04-24 20:10:32 +04:00
|
|
|
* The last descriptor block in the DMA program. It contains the branch
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
* address that must be updated upon appending a new descriptor.
|
|
|
|
*/
|
|
|
|
struct descriptor *prev;
|
firewire: ohci: fix VIA VT6306 video reception
Add quirk for VT6306 wake bit behavior.
VT6306 seems to reread the wrong descriptor when the wake bit is
written. work around by putting a copy of the branch address in the
first descriptor of the block.
[Stefan R: This fixes the known broken video reception via gstreamer
on VIA VT6306. 100% repeatable testcase:
$ gst-launch-0.10 dv1394src \! dvdemux \! dvdec \! xvimagesink
with a camcorder or other DV source connected. Likewise for MPEG2-TS
reception via gstreamer, e.g. from TV settop boxes.
Perhaps this also fixes dv4l on VT6306, but this is as yet untested.
Kino, dvgrab or FFADO had not been affected by this chip quirk.
Additional comments from Andy:]
I've looked into some problems with the wake bit on a vt6306 family
chip (1106:3044, rev 46).
I used this firewire card in a mythtv setup (ISO receive MPEG2 stream)
with Debian 2.6.32 kernels for ~2 years without problems.
Since upgrading to 3.2, I've been having problems with the input stream
freezing -- input data stops until I restart mythtv (I expect closing
and reopening the device would be sufficient). This happens
infrequently, maybe one out of 20 recordings. I eventually determined
that the problem is more likely to occur if the system is loaded.
I isolated the kernel version as the triggering SW factor and then
specifically the change from dualbuffer back to packet-per-buffer DMA
mode.
The possibility that the controller does not properly respond to the
wake bit was suggested in
https://bugzilla.redhat.com/show_bug.cgi?id=415841, but not proven.
Based on the fact that dualbuffer mode worked while packet-per-buffer
has trouble, I guessed that upon seeing the wake bit written, the vt6306
controller only checks the branch address in the first descriptor of the
block, even if that is not the correct place to look (because the block
has multiple descriptors).
This theory seems to be correct. When the ISO reception is hung, I am
able to resume it by manually writing the branch address to the first
descriptor in the block, and then writing the wake bit.
I've had luck so far with the attached patch, so I'm including it. It's
probably not a complete solution -- I haven't tested transmit modes to
see whether they have a similar issue.
I doubt that the quirk test is any cheaper than just writing the extra
branch address in all cases, but it does reduce the risk of breaking
other hardware.
[Stefan R: omitted QUIRK_NO_MSI from VT6306 quirks table entry,
changed whitespace]
Signed-off-by: Andy Leiserson <andy@leiserson.org>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2013-04-24 20:10:32 +04:00
|
|
|
int prev_z;
|
2007-02-17 01:34:39 +03:00
|
|
|
|
|
|
|
descriptor_callback_t callback;
|
|
|
|
|
2007-03-04 16:45:18 +03:00
|
|
|
struct tasklet_struct tasklet;
|
2007-02-17 01:34:39 +03:00
|
|
|
};
|
|
|
|
|
2007-05-08 04:33:35 +04:00
|
|
|
#define IT_HEADER_SY(v) ((v) << 0)
|
|
|
|
#define IT_HEADER_TCODE(v) ((v) << 4)
|
|
|
|
#define IT_HEADER_CHANNEL(v) ((v) << 8)
|
|
|
|
#define IT_HEADER_TAG(v) ((v) << 14)
|
|
|
|
#define IT_HEADER_SPEED(v) ((v) << 16)
|
|
|
|
#define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
struct iso_context {
|
|
|
|
struct fw_iso_context base;
|
2007-02-17 01:34:39 +03:00
|
|
|
struct context context;
|
2007-02-17 01:34:44 +03:00
|
|
|
void *header;
|
|
|
|
size_t header_length;
|
2012-03-18 22:06:39 +04:00
|
|
|
unsigned long flushing_completions;
|
|
|
|
u32 mc_buffer_bus;
|
|
|
|
u16 mc_completed;
|
2012-03-18 22:04:43 +04:00
|
|
|
u16 last_timestamp;
|
2010-11-29 05:09:50 +03:00
|
|
|
u8 sync;
|
|
|
|
u8 tags;
|
2006-12-20 03:58:35 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
#define CONFIG_ROM_SIZE 1024
|
|
|
|
|
|
|
|
struct fw_ohci {
|
|
|
|
struct fw_card card;
|
|
|
|
|
|
|
|
__iomem char *registers;
|
2007-01-26 08:38:04 +03:00
|
|
|
int node_id;
|
2006-12-20 03:58:35 +03:00
|
|
|
int generation;
|
2008-03-11 04:23:29 +03:00
|
|
|
int request_generation; /* for timestamping incoming requests */
|
2010-02-21 19:58:01 +03:00
|
|
|
unsigned quirks;
|
2010-06-10 10:35:06 +04:00
|
|
|
unsigned int pri_req_max;
|
2010-06-10 10:33:07 +04:00
|
|
|
u32 bus_time;
|
2012-05-24 21:29:19 +04:00
|
|
|
bool bus_time_running;
|
2010-06-10 10:36:37 +04:00
|
|
|
bool is_root;
|
2010-06-12 22:34:50 +04:00
|
|
|
bool csr_state_setclear_abdicate;
|
2010-11-29 05:09:50 +03:00
|
|
|
int n_ir;
|
|
|
|
int n_it;
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
|
|
|
* Spinlock for accessing fw_ohci data. Never call out of
|
|
|
|
* this driver with this lock held.
|
|
|
|
*/
|
2006-12-20 03:58:35 +03:00
|
|
|
spinlock_t lock;
|
|
|
|
|
2010-07-08 18:09:06 +04:00
|
|
|
struct mutex phy_reg_mutex;
|
|
|
|
|
2010-11-30 10:25:17 +03:00
|
|
|
void *misc_buffer;
|
|
|
|
dma_addr_t misc_buffer_bus;
|
|
|
|
|
2006-12-20 03:58:35 +03:00
|
|
|
struct ar_context ar_request_ctx;
|
|
|
|
struct ar_context ar_response_ctx;
|
2007-03-07 20:12:49 +03:00
|
|
|
struct context at_request_ctx;
|
|
|
|
struct context at_response_ctx;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2011-01-10 19:21:35 +03:00
|
|
|
u32 it_context_support;
|
2010-07-29 20:19:22 +04:00
|
|
|
u32 it_context_mask; /* unoccupied IT contexts */
|
2006-12-20 03:58:35 +03:00
|
|
|
struct iso_context *it_context_list;
|
2010-07-29 20:19:22 +04:00
|
|
|
u64 ir_context_channels; /* unoccupied channels */
|
2011-01-10 19:21:35 +03:00
|
|
|
u32 ir_context_support;
|
2010-07-29 20:19:22 +04:00
|
|
|
u32 ir_context_mask; /* unoccupied IR contexts */
|
2006-12-20 03:58:35 +03:00
|
|
|
struct iso_context *ir_context_list;
|
2010-07-29 20:19:22 +04:00
|
|
|
u64 mc_channels; /* channels in use by the multichannel IR context */
|
|
|
|
bool mc_allocated;
|
2010-02-21 19:57:32 +03:00
|
|
|
|
|
|
|
__be32 *config_rom;
|
|
|
|
dma_addr_t config_rom_bus;
|
|
|
|
__be32 *next_config_rom;
|
|
|
|
dma_addr_t next_config_rom_bus;
|
|
|
|
__be32 next_header;
|
|
|
|
|
2013-08-05 17:10:38 +04:00
|
|
|
__le32 *self_id;
|
2010-02-21 19:57:32 +03:00
|
|
|
dma_addr_t self_id_bus;
|
2011-07-26 00:16:24 +04:00
|
|
|
struct work_struct bus_reset_work;
|
2010-02-21 19:57:32 +03:00
|
|
|
|
|
|
|
u32 self_id_buffer[512];
|
2006-12-20 03:58:35 +03:00
|
|
|
};
|
|
|
|
|
2013-08-26 22:50:05 +04:00
|
|
|
static struct workqueue_struct *selfid_workqueue;
|
|
|
|
|
2007-01-22 21:17:37 +03:00
|
|
|
static inline struct fw_ohci *fw_ohci(struct fw_card *card)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
|
|
|
return container_of(card, struct fw_ohci, card);
|
|
|
|
}
|
|
|
|
|
2007-02-17 01:34:40 +03:00
|
|
|
#define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
|
|
|
|
#define IR_CONTEXT_BUFFER_FILL 0x80000000
|
|
|
|
#define IR_CONTEXT_ISOCH_HEADER 0x40000000
|
|
|
|
#define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
|
|
|
|
#define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
|
|
|
|
#define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
#define CONTEXT_RUN 0x8000
|
|
|
|
#define CONTEXT_WAKE 0x1000
|
|
|
|
#define CONTEXT_DEAD 0x0800
|
|
|
|
#define CONTEXT_ACTIVE 0x0400
|
|
|
|
|
2009-01-20 21:10:58 +03:00
|
|
|
#define OHCI1394_MAX_AT_REQ_RETRIES 0xf
|
2006-12-20 03:58:35 +03:00
|
|
|
#define OHCI1394_MAX_AT_RESP_RETRIES 0x2
|
|
|
|
#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
|
|
|
|
|
|
|
|
#define OHCI1394_REGISTER_SIZE 0x800
|
|
|
|
#define OHCI1394_PCI_HCI_Control 0x40
|
|
|
|
#define SELF_ID_BUF_SIZE 0x800
|
2007-02-06 22:49:30 +03:00
|
|
|
#define OHCI_TCODE_PHY_PACKET 0x0e
|
2007-02-17 01:34:49 +03:00
|
|
|
#define OHCI_VERSION_1_1 0x010010
|
2007-01-26 08:38:49 +03:00
|
|
|
|
2006-12-20 03:58:35 +03:00
|
|
|
static char ohci_driver_name[] = KBUILD_MODNAME;
|
|
|
|
|
2013-08-05 17:14:36 +04:00
|
|
|
#define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
|
2010-12-07 22:32:40 +03:00
|
|
|
#define PCI_DEVICE_ID_AGERE_FW643 0x5901
|
2012-01-27 01:05:58 +04:00
|
|
|
#define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001
|
2010-06-05 14:31:25 +04:00
|
|
|
#define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
|
2010-03-17 13:07:55 +03:00
|
|
|
#define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
|
2011-09-13 00:23:53 +04:00
|
|
|
#define PCI_DEVICE_ID_TI_TSB12LV26 0x8020
|
|
|
|
#define PCI_DEVICE_ID_TI_TSB82AA2 0x8025
|
firewire: ohci: fix VIA VT6306 video reception
Add quirk for VT6306 wake bit behavior.
VT6306 seems to reread the wrong descriptor when the wake bit is
written. work around by putting a copy of the branch address in the
first descriptor of the block.
[Stefan R: This fixes the known broken video reception via gstreamer
on VIA VT6306. 100% repeatable testcase:
$ gst-launch-0.10 dv1394src \! dvdemux \! dvdec \! xvimagesink
with a camcorder or other DV source connected. Likewise for MPEG2-TS
reception via gstreamer, e.g. from TV settop boxes.
Perhaps this also fixes dv4l on VT6306, but this is as yet untested.
Kino, dvgrab or FFADO had not been affected by this chip quirk.
Additional comments from Andy:]
I've looked into some problems with the wake bit on a vt6306 family
chip (1106:3044, rev 46).
I used this firewire card in a mythtv setup (ISO receive MPEG2 stream)
with Debian 2.6.32 kernels for ~2 years without problems.
Since upgrading to 3.2, I've been having problems with the input stream
freezing -- input data stops until I restart mythtv (I expect closing
and reopening the device would be sufficient). This happens
infrequently, maybe one out of 20 recordings. I eventually determined
that the problem is more likely to occur if the system is loaded.
I isolated the kernel version as the triggering SW factor and then
specifically the change from dualbuffer back to packet-per-buffer DMA
mode.
The possibility that the controller does not properly respond to the
wake bit was suggested in
https://bugzilla.redhat.com/show_bug.cgi?id=415841, but not proven.
Based on the fact that dualbuffer mode worked while packet-per-buffer
has trouble, I guessed that upon seeing the wake bit written, the vt6306
controller only checks the branch address in the first descriptor of the
block, even if that is not the correct place to look (because the block
has multiple descriptors).
This theory seems to be correct. When the ISO reception is hung, I am
able to resume it by manually writing the branch address to the first
descriptor in the block, and then writing the wake bit.
I've had luck so far with the attached patch, so I'm including it. It's
probably not a complete solution -- I haven't tested transmit modes to
see whether they have a similar issue.
I doubt that the quirk test is any cheaper than just writing the extra
branch address in all cases, but it does reduce the risk of breaking
other hardware.
[Stefan R: omitted QUIRK_NO_MSI from VT6306 quirks table entry,
changed whitespace]
Signed-off-by: Andy Leiserson <andy@leiserson.org>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2013-04-24 20:10:32 +04:00
|
|
|
#define PCI_DEVICE_ID_VIA_VT630X 0x3044
|
|
|
|
#define PCI_REV_ID_VIA_VT6306 0x46
|
2014-04-16 03:08:08 +04:00
|
|
|
#define PCI_DEVICE_ID_VIA_VT6315 0x3403
|
2010-03-17 13:07:55 +03:00
|
|
|
|
2013-08-05 17:14:36 +04:00
|
|
|
#define QUIRK_CYCLE_TIMER 0x1
|
|
|
|
#define QUIRK_RESET_PACKET 0x2
|
|
|
|
#define QUIRK_BE_HEADERS 0x4
|
|
|
|
#define QUIRK_NO_1394A 0x8
|
|
|
|
#define QUIRK_NO_MSI 0x10
|
|
|
|
#define QUIRK_TI_SLLZ059 0x20
|
|
|
|
#define QUIRK_IR_WAKE 0x40
|
2010-02-21 19:58:01 +03:00
|
|
|
|
|
|
|
/* In case of multiple matches in ohci_quirks[], only the first one is used. */
|
|
|
|
static const struct {
|
2010-12-07 22:32:40 +03:00
|
|
|
unsigned short vendor, device, revision, flags;
|
2010-02-21 19:58:01 +03:00
|
|
|
} ohci_quirks[] = {
|
2010-12-07 22:32:40 +03:00
|
|
|
{PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
|
|
|
|
QUIRK_CYCLE_TIMER},
|
|
|
|
|
|
|
|
{PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
|
|
|
|
QUIRK_BE_HEADERS},
|
|
|
|
|
|
|
|
{PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
|
2014-03-06 23:39:04 +04:00
|
|
|
QUIRK_NO_MSI},
|
2010-12-07 22:32:40 +03:00
|
|
|
|
2012-01-27 01:05:58 +04:00
|
|
|
{PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
|
|
|
|
QUIRK_RESET_PACKET},
|
|
|
|
|
2010-12-07 22:32:40 +03:00
|
|
|
{PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
|
|
|
|
QUIRK_NO_MSI},
|
|
|
|
|
|
|
|
{PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
|
|
|
|
QUIRK_CYCLE_TIMER},
|
|
|
|
|
2011-08-31 06:45:46 +04:00
|
|
|
{PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
|
|
|
|
QUIRK_NO_MSI},
|
|
|
|
|
2010-12-07 22:32:40 +03:00
|
|
|
{PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
|
2012-01-29 15:41:15 +04:00
|
|
|
QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
|
2010-12-07 22:32:40 +03:00
|
|
|
|
|
|
|
{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
|
|
|
|
QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
|
|
|
|
|
2011-09-13 00:23:53 +04:00
|
|
|
{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
|
|
|
|
QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
|
|
|
|
|
|
|
|
{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
|
|
|
|
QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
|
|
|
|
|
2010-12-07 22:32:40 +03:00
|
|
|
{PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
|
|
|
|
QUIRK_RESET_PACKET},
|
|
|
|
|
firewire: ohci: fix VIA VT6306 video reception
Add quirk for VT6306 wake bit behavior.
VT6306 seems to reread the wrong descriptor when the wake bit is
written. work around by putting a copy of the branch address in the
first descriptor of the block.
[Stefan R: This fixes the known broken video reception via gstreamer
on VIA VT6306. 100% repeatable testcase:
$ gst-launch-0.10 dv1394src \! dvdemux \! dvdec \! xvimagesink
with a camcorder or other DV source connected. Likewise for MPEG2-TS
reception via gstreamer, e.g. from TV settop boxes.
Perhaps this also fixes dv4l on VT6306, but this is as yet untested.
Kino, dvgrab or FFADO had not been affected by this chip quirk.
Additional comments from Andy:]
I've looked into some problems with the wake bit on a vt6306 family
chip (1106:3044, rev 46).
I used this firewire card in a mythtv setup (ISO receive MPEG2 stream)
with Debian 2.6.32 kernels for ~2 years without problems.
Since upgrading to 3.2, I've been having problems with the input stream
freezing -- input data stops until I restart mythtv (I expect closing
and reopening the device would be sufficient). This happens
infrequently, maybe one out of 20 recordings. I eventually determined
that the problem is more likely to occur if the system is loaded.
I isolated the kernel version as the triggering SW factor and then
specifically the change from dualbuffer back to packet-per-buffer DMA
mode.
The possibility that the controller does not properly respond to the
wake bit was suggested in
https://bugzilla.redhat.com/show_bug.cgi?id=415841, but not proven.
Based on the fact that dualbuffer mode worked while packet-per-buffer
has trouble, I guessed that upon seeing the wake bit written, the vt6306
controller only checks the branch address in the first descriptor of the
block, even if that is not the correct place to look (because the block
has multiple descriptors).
This theory seems to be correct. When the ISO reception is hung, I am
able to resume it by manually writing the branch address to the first
descriptor in the block, and then writing the wake bit.
I've had luck so far with the attached patch, so I'm including it. It's
probably not a complete solution -- I haven't tested transmit modes to
see whether they have a similar issue.
I doubt that the quirk test is any cheaper than just writing the extra
branch address in all cases, but it does reduce the risk of breaking
other hardware.
[Stefan R: omitted QUIRK_NO_MSI from VT6306 quirks table entry,
changed whitespace]
Signed-off-by: Andy Leiserson <andy@leiserson.org>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2013-04-24 20:10:32 +04:00
|
|
|
{PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT630X, PCI_REV_ID_VIA_VT6306,
|
|
|
|
QUIRK_CYCLE_TIMER | QUIRK_IR_WAKE},
|
|
|
|
|
2014-04-16 03:08:08 +04:00
|
|
|
{PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, 0,
|
2014-07-23 22:08:12 +04:00
|
|
|
QUIRK_CYCLE_TIMER /* FIXME: necessary? */ | QUIRK_NO_MSI},
|
2014-04-16 03:08:08 +04:00
|
|
|
|
|
|
|
{PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT6315, PCI_ANY_ID,
|
2014-07-23 22:08:12 +04:00
|
|
|
QUIRK_NO_MSI},
|
2014-04-16 03:08:08 +04:00
|
|
|
|
2010-12-07 22:32:40 +03:00
|
|
|
{PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
|
|
|
|
QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
|
2010-02-21 19:58:01 +03:00
|
|
|
};
|
|
|
|
|
2010-02-21 19:58:29 +03:00
|
|
|
/* This overrides anything that was found in ohci_quirks[]. */
|
|
|
|
static int param_quirks;
|
|
|
|
module_param_named(quirks, param_quirks, int, 0644);
|
|
|
|
MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
|
|
|
|
", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
|
|
|
|
", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
|
2012-12-28 21:00:09 +04:00
|
|
|
", AR/selfID endianness = " __stringify(QUIRK_BE_HEADERS)
|
2010-04-04 17:19:54 +04:00
|
|
|
", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
|
2010-06-05 14:31:25 +04:00
|
|
|
", disable MSI = " __stringify(QUIRK_NO_MSI)
|
2011-09-19 02:17:37 +04:00
|
|
|
", TI SLLZ059 erratum = " __stringify(QUIRK_TI_SLLZ059)
|
firewire: ohci: fix VIA VT6306 video reception
Add quirk for VT6306 wake bit behavior.
VT6306 seems to reread the wrong descriptor when the wake bit is
written. work around by putting a copy of the branch address in the
first descriptor of the block.
[Stefan R: This fixes the known broken video reception via gstreamer
on VIA VT6306. 100% repeatable testcase:
$ gst-launch-0.10 dv1394src \! dvdemux \! dvdec \! xvimagesink
with a camcorder or other DV source connected. Likewise for MPEG2-TS
reception via gstreamer, e.g. from TV settop boxes.
Perhaps this also fixes dv4l on VT6306, but this is as yet untested.
Kino, dvgrab or FFADO had not been affected by this chip quirk.
Additional comments from Andy:]
I've looked into some problems with the wake bit on a vt6306 family
chip (1106:3044, rev 46).
I used this firewire card in a mythtv setup (ISO receive MPEG2 stream)
with Debian 2.6.32 kernels for ~2 years without problems.
Since upgrading to 3.2, I've been having problems with the input stream
freezing -- input data stops until I restart mythtv (I expect closing
and reopening the device would be sufficient). This happens
infrequently, maybe one out of 20 recordings. I eventually determined
that the problem is more likely to occur if the system is loaded.
I isolated the kernel version as the triggering SW factor and then
specifically the change from dualbuffer back to packet-per-buffer DMA
mode.
The possibility that the controller does not properly respond to the
wake bit was suggested in
https://bugzilla.redhat.com/show_bug.cgi?id=415841, but not proven.
Based on the fact that dualbuffer mode worked while packet-per-buffer
has trouble, I guessed that upon seeing the wake bit written, the vt6306
controller only checks the branch address in the first descriptor of the
block, even if that is not the correct place to look (because the block
has multiple descriptors).
This theory seems to be correct. When the ISO reception is hung, I am
able to resume it by manually writing the branch address to the first
descriptor in the block, and then writing the wake bit.
I've had luck so far with the attached patch, so I'm including it. It's
probably not a complete solution -- I haven't tested transmit modes to
see whether they have a similar issue.
I doubt that the quirk test is any cheaper than just writing the extra
branch address in all cases, but it does reduce the risk of breaking
other hardware.
[Stefan R: omitted QUIRK_NO_MSI from VT6306 quirks table entry,
changed whitespace]
Signed-off-by: Andy Leiserson <andy@leiserson.org>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2013-04-24 20:10:32 +04:00
|
|
|
", IR wake unreliable = " __stringify(QUIRK_IR_WAKE)
|
2010-02-21 19:58:29 +03:00
|
|
|
")");
|
|
|
|
|
2008-04-08 00:33:35 +04:00
|
|
|
#define OHCI_PARAM_DEBUG_AT_AR 1
|
2008-03-21 00:04:36 +03:00
|
|
|
#define OHCI_PARAM_DEBUG_SELFIDS 2
|
2008-04-08 00:33:35 +04:00
|
|
|
#define OHCI_PARAM_DEBUG_IRQS 4
|
|
|
|
#define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
|
2008-03-21 00:04:36 +03:00
|
|
|
|
|
|
|
static int param_debug;
|
|
|
|
module_param_named(debug, param_debug, int, 0644);
|
|
|
|
MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
|
|
|
|
", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
|
2008-04-08 00:33:35 +04:00
|
|
|
", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
|
|
|
|
", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
|
|
|
|
", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
|
2008-03-21 00:04:36 +03:00
|
|
|
", or a combination, or all = -1)");
|
|
|
|
|
2013-12-22 14:34:22 +04:00
|
|
|
static bool param_remote_dma;
|
|
|
|
module_param_named(remote_dma, param_remote_dma, bool, 0444);
|
|
|
|
MODULE_PARM_DESC(remote_dma, "Enable unfiltered remote DMA (default = N)");
|
|
|
|
|
2011-12-21 00:32:46 +04:00
|
|
|
static void log_irqs(struct fw_ohci *ohci, u32 evt)
|
2008-03-21 00:04:36 +03:00
|
|
|
{
|
2008-04-08 00:33:35 +04:00
|
|
|
if (likely(!(param_debug &
|
|
|
|
(OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
|
|
|
|
!(evt & OHCI1394_busReset))
|
2008-03-21 00:04:36 +03:00
|
|
|
return;
|
|
|
|
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci, "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
|
2008-06-14 16:23:43 +04:00
|
|
|
evt & OHCI1394_selfIDComplete ? " selfID" : "",
|
|
|
|
evt & OHCI1394_RQPkt ? " AR_req" : "",
|
|
|
|
evt & OHCI1394_RSPkt ? " AR_resp" : "",
|
|
|
|
evt & OHCI1394_reqTxComplete ? " AT_req" : "",
|
|
|
|
evt & OHCI1394_respTxComplete ? " AT_resp" : "",
|
|
|
|
evt & OHCI1394_isochRx ? " IR" : "",
|
|
|
|
evt & OHCI1394_isochTx ? " IT" : "",
|
|
|
|
evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
|
|
|
|
evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
|
2010-06-10 10:33:07 +04:00
|
|
|
evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
|
2009-11-17 20:29:17 +03:00
|
|
|
evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
|
2008-06-14 16:23:43 +04:00
|
|
|
evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
|
2011-01-10 19:21:35 +03:00
|
|
|
evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
|
2008-06-14 16:23:43 +04:00
|
|
|
evt & OHCI1394_busReset ? " busReset" : "",
|
|
|
|
evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
|
|
|
|
OHCI1394_RSPkt | OHCI1394_reqTxComplete |
|
|
|
|
OHCI1394_respTxComplete | OHCI1394_isochRx |
|
|
|
|
OHCI1394_isochTx | OHCI1394_postedWriteErr |
|
2010-06-10 10:33:07 +04:00
|
|
|
OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
|
|
|
|
OHCI1394_cycleInconsistent |
|
2008-06-14 16:23:43 +04:00
|
|
|
OHCI1394_regAccessFail | OHCI1394_busReset)
|
2008-03-21 00:04:36 +03:00
|
|
|
? " ?" : "");
|
|
|
|
}
|
|
|
|
|
|
|
|
static const char *speed[] = {
|
|
|
|
[0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
|
|
|
|
};
|
|
|
|
static const char *power[] = {
|
|
|
|
[0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
|
|
|
|
[4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
|
|
|
|
};
|
|
|
|
static const char port[] = { '.', '-', 'p', 'c', };
|
|
|
|
|
|
|
|
static char _p(u32 *s, int shift)
|
|
|
|
{
|
|
|
|
return port[*s >> shift & 3];
|
|
|
|
}
|
|
|
|
|
2011-12-21 00:32:46 +04:00
|
|
|
static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
|
2008-03-21 00:04:36 +03:00
|
|
|
{
|
2011-12-21 00:32:46 +04:00
|
|
|
u32 *s;
|
|
|
|
|
2008-03-21 00:04:36 +03:00
|
|
|
if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
|
|
|
|
return;
|
|
|
|
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci, "%d selfIDs, generation %d, local node ID %04x\n",
|
|
|
|
self_id_count, generation, ohci->node_id);
|
2008-03-21 00:04:36 +03:00
|
|
|
|
2011-12-21 00:32:46 +04:00
|
|
|
for (s = ohci->self_id_buffer; self_id_count--; ++s)
|
2008-03-21 00:04:36 +03:00
|
|
|
if ((*s & 1 << 23) == 0)
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci,
|
|
|
|
"selfID 0: %08x, phy %d [%c%c%c] %s gc=%d %s %s%s%s\n",
|
2008-06-14 16:23:43 +04:00
|
|
|
*s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
|
|
|
|
speed[*s >> 14 & 3], *s >> 16 & 63,
|
|
|
|
power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
|
|
|
|
*s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
|
2008-03-21 00:04:36 +03:00
|
|
|
else
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci,
|
2011-12-21 00:32:46 +04:00
|
|
|
"selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
|
2008-06-14 16:23:43 +04:00
|
|
|
*s, *s >> 24 & 63,
|
|
|
|
_p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
|
|
|
|
_p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
|
2008-03-21 00:04:36 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const char *evts[] = {
|
|
|
|
[0x00] = "evt_no_status", [0x01] = "-reserved-",
|
|
|
|
[0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
|
|
|
|
[0x04] = "evt_underrun", [0x05] = "evt_overrun",
|
|
|
|
[0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
|
|
|
|
[0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
|
|
|
|
[0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
|
|
|
|
[0x0c] = "-reserved-", [0x0d] = "-reserved-",
|
|
|
|
[0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
|
|
|
|
[0x10] = "-reserved-", [0x11] = "ack_complete",
|
|
|
|
[0x12] = "ack_pending ", [0x13] = "-reserved-",
|
|
|
|
[0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
|
|
|
|
[0x16] = "ack_busy_B", [0x17] = "-reserved-",
|
|
|
|
[0x18] = "-reserved-", [0x19] = "-reserved-",
|
|
|
|
[0x1a] = "-reserved-", [0x1b] = "ack_tardy",
|
|
|
|
[0x1c] = "-reserved-", [0x1d] = "ack_data_error",
|
|
|
|
[0x1e] = "ack_type_error", [0x1f] = "-reserved-",
|
|
|
|
[0x20] = "pending/cancelled",
|
|
|
|
};
|
|
|
|
static const char *tcodes[] = {
|
|
|
|
[0x0] = "QW req", [0x1] = "BW req",
|
|
|
|
[0x2] = "W resp", [0x3] = "-reserved-",
|
|
|
|
[0x4] = "QR req", [0x5] = "BR req",
|
|
|
|
[0x6] = "QR resp", [0x7] = "BR resp",
|
|
|
|
[0x8] = "cycle start", [0x9] = "Lk req",
|
|
|
|
[0xa] = "async stream packet", [0xb] = "Lk resp",
|
|
|
|
[0xc] = "-reserved-", [0xd] = "-reserved-",
|
|
|
|
[0xe] = "link internal", [0xf] = "-reserved-",
|
|
|
|
};
|
|
|
|
|
2011-12-21 00:32:46 +04:00
|
|
|
static void log_ar_at_event(struct fw_ohci *ohci,
|
|
|
|
char dir, int speed, u32 *header, int evt)
|
2008-03-21 00:04:36 +03:00
|
|
|
{
|
|
|
|
int tcode = header[0] >> 4 & 0xf;
|
|
|
|
char specific[12];
|
|
|
|
|
|
|
|
if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
|
|
|
|
return;
|
|
|
|
|
|
|
|
if (unlikely(evt >= ARRAY_SIZE(evts)))
|
|
|
|
evt = 0x1f;
|
|
|
|
|
2008-04-11 02:51:15 +04:00
|
|
|
if (evt == OHCI1394_evt_bus_reset) {
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci, "A%c evt_bus_reset, generation %d\n",
|
|
|
|
dir, (header[2] >> 16) & 0xff);
|
2008-04-11 02:51:15 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2008-03-21 00:04:36 +03:00
|
|
|
switch (tcode) {
|
|
|
|
case 0x0: case 0x6: case 0x8:
|
|
|
|
snprintf(specific, sizeof(specific), " = %08x",
|
|
|
|
be32_to_cpu((__force __be32)header[3]));
|
|
|
|
break;
|
|
|
|
case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
|
|
|
|
snprintf(specific, sizeof(specific), " %x,%x",
|
|
|
|
header[3] >> 16, header[3] & 0xffff);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
specific[0] = '\0';
|
|
|
|
}
|
|
|
|
|
|
|
|
switch (tcode) {
|
2010-11-30 10:24:47 +03:00
|
|
|
case 0xa:
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci, "A%c %s, %s\n",
|
|
|
|
dir, evts[evt], tcodes[tcode]);
|
2008-03-21 00:04:36 +03:00
|
|
|
break;
|
2010-11-30 10:24:47 +03:00
|
|
|
case 0xe:
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci, "A%c %s, PHY %08x %08x\n",
|
|
|
|
dir, evts[evt], header[1], header[2]);
|
2010-11-30 10:24:47 +03:00
|
|
|
break;
|
2008-03-21 00:04:36 +03:00
|
|
|
case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci,
|
|
|
|
"A%c spd %x tl %02x, %04x -> %04x, %s, %s, %04x%08x%s\n",
|
|
|
|
dir, speed, header[0] >> 10 & 0x3f,
|
|
|
|
header[1] >> 16, header[0] >> 16, evts[evt],
|
|
|
|
tcodes[tcode], header[1] & 0xffff, header[2], specific);
|
2008-03-21 00:04:36 +03:00
|
|
|
break;
|
|
|
|
default:
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci,
|
|
|
|
"A%c spd %x tl %02x, %04x -> %04x, %s, %s%s\n",
|
|
|
|
dir, speed, header[0] >> 10 & 0x3f,
|
|
|
|
header[1] >> 16, header[0] >> 16, evts[evt],
|
|
|
|
tcodes[tcode], specific);
|
2008-03-21 00:04:36 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-01-22 21:17:37 +03:00
|
|
|
static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
|
|
|
writel(data, ohci->registers + offset);
|
|
|
|
}
|
|
|
|
|
2007-01-22 21:17:37 +03:00
|
|
|
static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
|
|
|
return readl(ohci->registers + offset);
|
|
|
|
}
|
|
|
|
|
2007-01-22 21:17:37 +03:00
|
|
|
static inline void flush_writes(const struct fw_ohci *ohci)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
|
|
|
/* Do a dummy read to flush writes. */
|
|
|
|
reg_read(ohci, OHCI1394_Version);
|
|
|
|
}
|
|
|
|
|
2011-06-21 17:24:26 +04:00
|
|
|
/*
|
|
|
|
* Beware! read_phy_reg(), write_phy_reg(), update_phy_reg(), and
|
|
|
|
* read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
|
|
|
|
* In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
|
|
|
|
* directly. Exceptions are intrinsically serialized contexts like pci_probe.
|
|
|
|
*/
|
2010-04-10 18:04:56 +04:00
|
|
|
static int read_phy_reg(struct fw_ohci *ohci, int addr)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
2010-04-04 17:19:52 +04:00
|
|
|
u32 val;
|
2010-04-10 18:04:56 +04:00
|
|
|
int i;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
|
2010-06-10 10:22:07 +04:00
|
|
|
for (i = 0; i < 3 + 100; i++) {
|
2010-04-10 18:04:56 +04:00
|
|
|
val = reg_read(ohci, OHCI1394_PhyControl);
|
2011-06-22 23:05:08 +04:00
|
|
|
if (!~val)
|
|
|
|
return -ENODEV; /* Card was ejected. */
|
|
|
|
|
2010-04-10 18:04:56 +04:00
|
|
|
if (val & OHCI1394_PhyControl_ReadDone)
|
|
|
|
return OHCI1394_PhyControl_ReadData(val);
|
|
|
|
|
2010-06-10 10:22:07 +04:00
|
|
|
/*
|
|
|
|
* Try a few times without waiting. Sleeping is necessary
|
|
|
|
* only when the link/PHY interface is busy.
|
|
|
|
*/
|
|
|
|
if (i >= 3)
|
|
|
|
msleep(1);
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
2013-03-27 14:57:40 +04:00
|
|
|
ohci_err(ohci, "failed to read phy reg %d\n", addr);
|
|
|
|
dump_stack();
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2010-04-10 18:04:56 +04:00
|
|
|
return -EBUSY;
|
|
|
|
}
|
2010-04-04 17:19:52 +04:00
|
|
|
|
2010-04-10 18:04:56 +04:00
|
|
|
static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
|
|
|
|
{
|
|
|
|
int i;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
reg_write(ohci, OHCI1394_PhyControl,
|
2010-04-10 18:04:56 +04:00
|
|
|
OHCI1394_PhyControl_Write(addr, val));
|
2010-06-10 10:22:07 +04:00
|
|
|
for (i = 0; i < 3 + 100; i++) {
|
2010-04-10 18:04:56 +04:00
|
|
|
val = reg_read(ohci, OHCI1394_PhyControl);
|
2011-06-22 23:05:08 +04:00
|
|
|
if (!~val)
|
|
|
|
return -ENODEV; /* Card was ejected. */
|
|
|
|
|
2010-04-10 18:04:56 +04:00
|
|
|
if (!(val & OHCI1394_PhyControl_WritePending))
|
|
|
|
return 0;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2010-06-10 10:22:07 +04:00
|
|
|
if (i >= 3)
|
|
|
|
msleep(1);
|
2010-04-10 18:04:56 +04:00
|
|
|
}
|
2013-03-27 14:57:40 +04:00
|
|
|
ohci_err(ohci, "failed to write phy reg %d, val %u\n", addr, val);
|
|
|
|
dump_stack();
|
2010-04-10 18:04:56 +04:00
|
|
|
|
|
|
|
return -EBUSY;
|
2010-04-04 17:19:52 +04:00
|
|
|
}
|
|
|
|
|
2010-07-08 18:09:06 +04:00
|
|
|
static int update_phy_reg(struct fw_ohci *ohci, int addr,
|
|
|
|
int clear_bits, int set_bits)
|
2010-04-04 17:19:52 +04:00
|
|
|
{
|
2010-07-08 18:09:06 +04:00
|
|
|
int ret = read_phy_reg(ohci, addr);
|
2010-04-10 18:04:56 +04:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2010-04-04 17:19:52 +04:00
|
|
|
|
2010-04-01 18:40:18 +04:00
|
|
|
/*
|
|
|
|
* The interrupt status bits are cleared by writing a one bit.
|
|
|
|
* Avoid clearing them unless explicitly requested in set_bits.
|
|
|
|
*/
|
|
|
|
if (addr == 5)
|
|
|
|
clear_bits |= PHY_INT_STATUS_BITS;
|
|
|
|
|
2010-04-10 18:04:56 +04:00
|
|
|
return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2010-04-10 18:04:56 +04:00
|
|
|
static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
|
2010-04-04 17:19:54 +04:00
|
|
|
{
|
2010-04-10 18:04:56 +04:00
|
|
|
int ret;
|
2010-04-04 17:19:54 +04:00
|
|
|
|
2010-07-08 18:09:06 +04:00
|
|
|
ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
|
2010-04-10 18:04:56 +04:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2010-04-04 17:19:54 +04:00
|
|
|
|
2010-04-10 18:04:56 +04:00
|
|
|
return read_phy_reg(ohci, addr);
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2010-07-08 18:09:06 +04:00
|
|
|
static int ohci_read_phy_reg(struct fw_card *card, int addr)
|
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = fw_ohci(card);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&ohci->phy_reg_mutex);
|
|
|
|
ret = read_phy_reg(ohci, addr);
|
|
|
|
mutex_unlock(&ohci->phy_reg_mutex);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ohci_update_phy_reg(struct fw_card *card, int addr,
|
|
|
|
int clear_bits, int set_bits)
|
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = fw_ohci(card);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
mutex_lock(&ohci->phy_reg_mutex);
|
|
|
|
ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
|
|
|
|
mutex_unlock(&ohci->phy_reg_mutex);
|
|
|
|
|
|
|
|
return ret;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
|
|
|
|
{
|
|
|
|
return page_private(ctx->pages[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
2010-11-26 10:57:31 +03:00
|
|
|
struct descriptor *d;
|
2007-02-06 22:49:30 +03:00
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
d = &ctx->descriptors[index];
|
|
|
|
d->branch_address &= cpu_to_le32(~0xf);
|
|
|
|
d->res_count = cpu_to_le16(PAGE_SIZE);
|
|
|
|
d->transfer_status = 0;
|
2007-02-06 22:49:30 +03:00
|
|
|
|
2010-07-27 15:20:33 +04:00
|
|
|
wmb(); /* finish init of new descriptors before branch_address update */
|
2010-11-26 10:57:31 +03:00
|
|
|
d = &ctx->descriptors[ctx->last_buffer_index];
|
|
|
|
d->branch_address |= cpu_to_le32(1);
|
|
|
|
|
|
|
|
ctx->last_buffer_index = index;
|
2007-02-06 22:49:30 +03:00
|
|
|
|
2007-05-08 04:33:35 +04:00
|
|
|
reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
|
2010-10-25 13:42:42 +04:00
|
|
|
}
|
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
static void ar_context_release(struct ar_context *ctx)
|
2010-10-25 13:42:42 +04:00
|
|
|
{
|
2020-09-01 14:48:33 +03:00
|
|
|
struct device *dev = ctx->ohci->card.device;
|
2010-11-26 10:57:31 +03:00
|
|
|
unsigned int i;
|
2010-10-25 13:42:42 +04:00
|
|
|
|
2014-11-16 23:08:49 +03:00
|
|
|
vunmap(ctx->buffer);
|
2007-02-06 22:49:30 +03:00
|
|
|
|
2020-09-01 14:48:33 +03:00
|
|
|
for (i = 0; i < AR_BUFFERS; i++) {
|
|
|
|
if (ctx->pages[i])
|
|
|
|
dma_free_pages(dev, PAGE_SIZE, ctx->pages[i],
|
|
|
|
ar_buffer_bus(ctx, i), DMA_FROM_DEVICE);
|
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
|
2008-10-22 23:59:42 +04:00
|
|
|
{
|
2011-12-21 00:32:46 +04:00
|
|
|
struct fw_ohci *ohci = ctx->ohci;
|
2008-10-22 23:59:42 +04:00
|
|
|
|
2011-12-21 00:32:46 +04:00
|
|
|
if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
|
|
|
|
reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
|
|
|
|
flush_writes(ohci);
|
2008-10-22 23:59:42 +04:00
|
|
|
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "AR error: %s; DMA stopped\n", error_msg);
|
2008-10-22 23:59:42 +04:00
|
|
|
}
|
2010-11-26 10:57:31 +03:00
|
|
|
/* FIXME: restart? */
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned int ar_next_buffer_index(unsigned int index)
|
|
|
|
{
|
|
|
|
return (index + 1) % AR_BUFFERS;
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
|
|
|
|
{
|
|
|
|
return ar_next_buffer_index(ctx->last_buffer_index);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We search for the buffer that contains the last AR packet DMA data written
|
|
|
|
* by the controller.
|
|
|
|
*/
|
|
|
|
static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
|
|
|
|
unsigned int *buffer_offset)
|
|
|
|
{
|
|
|
|
unsigned int i, next_i, last = ctx->last_buffer_index;
|
|
|
|
__le16 res_count, next_res_count;
|
|
|
|
|
|
|
|
i = ar_first_buffer_index(ctx);
|
locking/atomics: COCCINELLE/treewide: Convert trivial ACCESS_ONCE() patterns to READ_ONCE()/WRITE_ONCE()
Please do not apply this to mainline directly, instead please re-run the
coccinelle script shown below and apply its output.
For several reasons, it is desirable to use {READ,WRITE}_ONCE() in
preference to ACCESS_ONCE(), and new code is expected to use one of the
former. So far, there's been no reason to change most existing uses of
ACCESS_ONCE(), as these aren't harmful, and changing them results in
churn.
However, for some features, the read/write distinction is critical to
correct operation. To distinguish these cases, separate read/write
accessors must be used. This patch migrates (most) remaining
ACCESS_ONCE() instances to {READ,WRITE}_ONCE(), using the following
coccinelle script:
----
// Convert trivial ACCESS_ONCE() uses to equivalent READ_ONCE() and
// WRITE_ONCE()
// $ make coccicheck COCCI=/home/mark/once.cocci SPFLAGS="--include-headers" MODE=patch
virtual patch
@ depends on patch @
expression E1, E2;
@@
- ACCESS_ONCE(E1) = E2
+ WRITE_ONCE(E1, E2)
@ depends on patch @
expression E;
@@
- ACCESS_ONCE(E)
+ READ_ONCE(E)
----
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: davem@davemloft.net
Cc: linux-arch@vger.kernel.org
Cc: mpe@ellerman.id.au
Cc: shuah@kernel.org
Cc: snitzer@redhat.com
Cc: thor.thayer@linux.intel.com
Cc: tj@kernel.org
Cc: viro@zeniv.linux.org.uk
Cc: will.deacon@arm.com
Link: http://lkml.kernel.org/r/1508792849-3115-19-git-send-email-paulmck@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-10-24 00:07:29 +03:00
|
|
|
res_count = READ_ONCE(ctx->descriptors[i].res_count);
|
2010-11-26 10:57:31 +03:00
|
|
|
|
|
|
|
/* A buffer that is not yet completely filled must be the last one. */
|
|
|
|
while (i != last && res_count == 0) {
|
|
|
|
|
|
|
|
/* Peek at the next descriptor. */
|
|
|
|
next_i = ar_next_buffer_index(i);
|
|
|
|
rmb(); /* read descriptors in order */
|
locking/atomics: COCCINELLE/treewide: Convert trivial ACCESS_ONCE() patterns to READ_ONCE()/WRITE_ONCE()
Please do not apply this to mainline directly, instead please re-run the
coccinelle script shown below and apply its output.
For several reasons, it is desirable to use {READ,WRITE}_ONCE() in
preference to ACCESS_ONCE(), and new code is expected to use one of the
former. So far, there's been no reason to change most existing uses of
ACCESS_ONCE(), as these aren't harmful, and changing them results in
churn.
However, for some features, the read/write distinction is critical to
correct operation. To distinguish these cases, separate read/write
accessors must be used. This patch migrates (most) remaining
ACCESS_ONCE() instances to {READ,WRITE}_ONCE(), using the following
coccinelle script:
----
// Convert trivial ACCESS_ONCE() uses to equivalent READ_ONCE() and
// WRITE_ONCE()
// $ make coccicheck COCCI=/home/mark/once.cocci SPFLAGS="--include-headers" MODE=patch
virtual patch
@ depends on patch @
expression E1, E2;
@@
- ACCESS_ONCE(E1) = E2
+ WRITE_ONCE(E1, E2)
@ depends on patch @
expression E;
@@
- ACCESS_ONCE(E)
+ READ_ONCE(E)
----
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: davem@davemloft.net
Cc: linux-arch@vger.kernel.org
Cc: mpe@ellerman.id.au
Cc: shuah@kernel.org
Cc: snitzer@redhat.com
Cc: thor.thayer@linux.intel.com
Cc: tj@kernel.org
Cc: viro@zeniv.linux.org.uk
Cc: will.deacon@arm.com
Link: http://lkml.kernel.org/r/1508792849-3115-19-git-send-email-paulmck@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-10-24 00:07:29 +03:00
|
|
|
next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count);
|
2010-11-26 10:57:31 +03:00
|
|
|
/*
|
|
|
|
* If the next descriptor is still empty, we must stop at this
|
|
|
|
* descriptor.
|
|
|
|
*/
|
|
|
|
if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
|
|
|
|
/*
|
|
|
|
* The exception is when the DMA data for one packet is
|
|
|
|
* split over three buffers; in this case, the middle
|
|
|
|
* buffer's descriptor might be never updated by the
|
|
|
|
* controller and look still empty, and we have to peek
|
|
|
|
* at the third one.
|
|
|
|
*/
|
|
|
|
if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
|
|
|
|
next_i = ar_next_buffer_index(next_i);
|
|
|
|
rmb();
|
locking/atomics: COCCINELLE/treewide: Convert trivial ACCESS_ONCE() patterns to READ_ONCE()/WRITE_ONCE()
Please do not apply this to mainline directly, instead please re-run the
coccinelle script shown below and apply its output.
For several reasons, it is desirable to use {READ,WRITE}_ONCE() in
preference to ACCESS_ONCE(), and new code is expected to use one of the
former. So far, there's been no reason to change most existing uses of
ACCESS_ONCE(), as these aren't harmful, and changing them results in
churn.
However, for some features, the read/write distinction is critical to
correct operation. To distinguish these cases, separate read/write
accessors must be used. This patch migrates (most) remaining
ACCESS_ONCE() instances to {READ,WRITE}_ONCE(), using the following
coccinelle script:
----
// Convert trivial ACCESS_ONCE() uses to equivalent READ_ONCE() and
// WRITE_ONCE()
// $ make coccicheck COCCI=/home/mark/once.cocci SPFLAGS="--include-headers" MODE=patch
virtual patch
@ depends on patch @
expression E1, E2;
@@
- ACCESS_ONCE(E1) = E2
+ WRITE_ONCE(E1, E2)
@ depends on patch @
expression E;
@@
- ACCESS_ONCE(E)
+ READ_ONCE(E)
----
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: davem@davemloft.net
Cc: linux-arch@vger.kernel.org
Cc: mpe@ellerman.id.au
Cc: shuah@kernel.org
Cc: snitzer@redhat.com
Cc: thor.thayer@linux.intel.com
Cc: tj@kernel.org
Cc: viro@zeniv.linux.org.uk
Cc: will.deacon@arm.com
Link: http://lkml.kernel.org/r/1508792849-3115-19-git-send-email-paulmck@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-10-24 00:07:29 +03:00
|
|
|
next_res_count = READ_ONCE(ctx->descriptors[next_i].res_count);
|
2010-11-26 10:57:31 +03:00
|
|
|
if (next_res_count != cpu_to_le16(PAGE_SIZE))
|
|
|
|
goto next_buffer_is_active;
|
|
|
|
}
|
|
|
|
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
next_buffer_is_active:
|
|
|
|
i = next_i;
|
|
|
|
res_count = next_res_count;
|
|
|
|
}
|
|
|
|
|
|
|
|
rmb(); /* read res_count before the DMA data */
|
|
|
|
|
|
|
|
*buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
|
|
|
|
if (*buffer_offset > PAGE_SIZE) {
|
|
|
|
*buffer_offset = 0;
|
|
|
|
ar_context_abort(ctx, "corrupted descriptor");
|
|
|
|
}
|
|
|
|
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
|
|
|
|
unsigned int end_buffer_index,
|
|
|
|
unsigned int end_buffer_offset)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
i = ar_first_buffer_index(ctx);
|
|
|
|
while (i != end_buffer_index) {
|
|
|
|
dma_sync_single_for_cpu(ctx->ohci->card.device,
|
|
|
|
ar_buffer_bus(ctx, i),
|
|
|
|
PAGE_SIZE, DMA_FROM_DEVICE);
|
|
|
|
i = ar_next_buffer_index(i);
|
|
|
|
}
|
|
|
|
if (end_buffer_offset > 0)
|
|
|
|
dma_sync_single_for_cpu(ctx->ohci->card.device,
|
|
|
|
ar_buffer_bus(ctx, i),
|
|
|
|
end_buffer_offset, DMA_FROM_DEVICE);
|
2008-10-22 23:59:42 +04:00
|
|
|
}
|
|
|
|
|
2008-03-01 04:47:15 +03:00
|
|
|
#if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
|
|
|
|
#define cond_le32_to_cpu(v) \
|
2010-02-21 19:58:01 +03:00
|
|
|
(ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
|
2008-03-01 04:47:15 +03:00
|
|
|
#else
|
|
|
|
#define cond_le32_to_cpu(v) le32_to_cpu(v)
|
|
|
|
#endif
|
|
|
|
|
2007-02-06 22:49:30 +03:00
|
|
|
static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = ctx->ohci;
|
2007-01-26 08:37:57 +03:00
|
|
|
struct fw_packet p;
|
|
|
|
u32 status, length, tcode;
|
2008-03-11 23:22:26 +03:00
|
|
|
int evt;
|
2007-01-26 08:37:57 +03:00
|
|
|
|
2008-03-01 04:47:15 +03:00
|
|
|
p.header[0] = cond_le32_to_cpu(buffer[0]);
|
|
|
|
p.header[1] = cond_le32_to_cpu(buffer[1]);
|
|
|
|
p.header[2] = cond_le32_to_cpu(buffer[2]);
|
2007-01-26 08:37:57 +03:00
|
|
|
|
|
|
|
tcode = (p.header[0] >> 4) & 0x0f;
|
|
|
|
switch (tcode) {
|
|
|
|
case TCODE_WRITE_QUADLET_REQUEST:
|
|
|
|
case TCODE_READ_QUADLET_RESPONSE:
|
2007-02-06 22:49:30 +03:00
|
|
|
p.header[3] = (__force __u32) buffer[3];
|
2007-01-26 08:37:57 +03:00
|
|
|
p.header_length = 16;
|
2007-02-06 22:49:30 +03:00
|
|
|
p.payload_length = 0;
|
2007-01-26 08:37:57 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
case TCODE_READ_BLOCK_REQUEST :
|
2008-03-01 04:47:15 +03:00
|
|
|
p.header[3] = cond_le32_to_cpu(buffer[3]);
|
2007-02-06 22:49:30 +03:00
|
|
|
p.header_length = 16;
|
|
|
|
p.payload_length = 0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case TCODE_WRITE_BLOCK_REQUEST:
|
2007-01-26 08:37:57 +03:00
|
|
|
case TCODE_READ_BLOCK_RESPONSE:
|
|
|
|
case TCODE_LOCK_REQUEST:
|
|
|
|
case TCODE_LOCK_RESPONSE:
|
2008-03-01 04:47:15 +03:00
|
|
|
p.header[3] = cond_le32_to_cpu(buffer[3]);
|
2007-01-26 08:37:57 +03:00
|
|
|
p.header_length = 16;
|
2007-02-06 22:49:30 +03:00
|
|
|
p.payload_length = p.header[3] >> 16;
|
2010-11-26 10:57:31 +03:00
|
|
|
if (p.payload_length > MAX_ASYNC_PAYLOAD) {
|
|
|
|
ar_context_abort(ctx, "invalid packet length");
|
|
|
|
return NULL;
|
|
|
|
}
|
2007-01-26 08:37:57 +03:00
|
|
|
break;
|
|
|
|
|
|
|
|
case TCODE_WRITE_RESPONSE:
|
|
|
|
case TCODE_READ_QUADLET_REQUEST:
|
2007-02-06 22:49:30 +03:00
|
|
|
case OHCI_TCODE_PHY_PACKET:
|
2007-01-26 08:37:57 +03:00
|
|
|
p.header_length = 12;
|
2007-02-06 22:49:30 +03:00
|
|
|
p.payload_length = 0;
|
2007-01-26 08:37:57 +03:00
|
|
|
break;
|
2008-05-31 21:36:06 +04:00
|
|
|
|
|
|
|
default:
|
2010-11-26 10:57:31 +03:00
|
|
|
ar_context_abort(ctx, "invalid tcode");
|
|
|
|
return NULL;
|
2007-01-26 08:37:57 +03:00
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-02-06 22:49:30 +03:00
|
|
|
p.payload = (void *) buffer + p.header_length;
|
|
|
|
|
|
|
|
/* FIXME: What to do about evt_* errors? */
|
|
|
|
length = (p.header_length + p.payload_length + 3) / 4;
|
2008-03-01 04:47:15 +03:00
|
|
|
status = cond_le32_to_cpu(buffer[length]);
|
2008-03-11 23:22:26 +03:00
|
|
|
evt = (status >> 16) & 0x1f;
|
2007-02-06 22:49:30 +03:00
|
|
|
|
2008-03-11 23:22:26 +03:00
|
|
|
p.ack = evt - 16;
|
2007-02-06 22:49:30 +03:00
|
|
|
p.speed = (status >> 21) & 0x7;
|
|
|
|
p.timestamp = status & 0xffff;
|
|
|
|
p.generation = ohci->request_generation;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2011-12-21 00:32:46 +04:00
|
|
|
log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
|
2008-03-21 00:04:36 +03:00
|
|
|
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
2010-08-28 16:21:26 +04:00
|
|
|
* Several controllers, notably from NEC and VIA, forget to
|
|
|
|
* write ack_complete status at PHY packet reception.
|
|
|
|
*/
|
|
|
|
if (evt == OHCI1394_evt_no_status &&
|
|
|
|
(p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
|
|
|
|
p.ack = ACK_COMPLETE;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The OHCI bus reset handler synthesizes a PHY packet with
|
2006-12-20 03:58:35 +03:00
|
|
|
* the new generation number when a bus reset happens (see
|
|
|
|
* section 8.4.2.3). This helps us determine when a request
|
|
|
|
* was received and make sure we send the response in the same
|
|
|
|
* generation. We only need this for requests; for responses
|
|
|
|
* we use the unique tlabel for finding the matching
|
2007-05-08 04:33:32 +04:00
|
|
|
* request.
|
2008-04-13 00:31:25 +04:00
|
|
|
*
|
|
|
|
* Alas some chips sometimes emit bus reset packets with a
|
|
|
|
* wrong generation. We set the correct generation for these
|
2011-07-26 00:16:24 +04:00
|
|
|
* at a slightly incorrect time (in bus_reset_work).
|
2007-05-08 04:33:32 +04:00
|
|
|
*/
|
2008-04-13 00:31:25 +04:00
|
|
|
if (evt == OHCI1394_evt_bus_reset) {
|
2010-02-21 19:58:01 +03:00
|
|
|
if (!(ohci->quirks & QUIRK_RESET_PACKET))
|
2008-04-13 00:31:25 +04:00
|
|
|
ohci->request_generation = (p.header[2] >> 16) & 0xff;
|
|
|
|
} else if (ctx == &ohci->ar_request_ctx) {
|
2007-01-26 08:37:57 +03:00
|
|
|
fw_core_handle_request(&ohci->card, &p);
|
2008-04-13 00:31:25 +04:00
|
|
|
} else {
|
2007-01-26 08:37:57 +03:00
|
|
|
fw_core_handle_response(&ohci->card, &p);
|
2008-04-13 00:31:25 +04:00
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-02-06 22:49:30 +03:00
|
|
|
return buffer + length + 1;
|
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
|
|
|
|
{
|
|
|
|
void *next;
|
|
|
|
|
|
|
|
while (p < end) {
|
|
|
|
next = handle_ar_packet(ctx, p);
|
|
|
|
if (!next)
|
|
|
|
return p;
|
|
|
|
p = next;
|
|
|
|
}
|
|
|
|
|
|
|
|
return p;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
i = ar_first_buffer_index(ctx);
|
|
|
|
while (i != end_buffer) {
|
|
|
|
dma_sync_single_for_device(ctx->ohci->card.device,
|
|
|
|
ar_buffer_bus(ctx, i),
|
|
|
|
PAGE_SIZE, DMA_FROM_DEVICE);
|
|
|
|
ar_context_link_page(ctx, i);
|
|
|
|
i = ar_next_buffer_index(i);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-02-06 22:49:30 +03:00
|
|
|
static void ar_context_tasklet(unsigned long data)
|
|
|
|
{
|
|
|
|
struct ar_context *ctx = (struct ar_context *)data;
|
2010-11-26 10:57:31 +03:00
|
|
|
unsigned int end_buffer_index, end_buffer_offset;
|
|
|
|
void *p, *end;
|
2007-02-06 22:49:30 +03:00
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
p = ctx->pointer;
|
|
|
|
if (!p)
|
|
|
|
return;
|
2007-02-06 22:49:30 +03:00
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
end_buffer_index = ar_search_last_active_buffer(ctx,
|
|
|
|
&end_buffer_offset);
|
|
|
|
ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
|
|
|
|
end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
|
2007-02-06 22:49:30 +03:00
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
if (end_buffer_index < ar_first_buffer_index(ctx)) {
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
2010-11-26 10:57:31 +03:00
|
|
|
* The filled part of the overall buffer wraps around; handle
|
|
|
|
* all packets up to the buffer end here. If the last packet
|
|
|
|
* wraps around, its tail will be visible after the buffer end
|
|
|
|
* because the buffer start pages are mapped there again.
|
2007-05-08 04:33:32 +04:00
|
|
|
*/
|
2010-11-26 10:57:31 +03:00
|
|
|
void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
|
|
|
|
p = handle_ar_packets(ctx, p, buffer_end);
|
|
|
|
if (p < buffer_end)
|
|
|
|
goto error;
|
|
|
|
/* adjust p to point back into the actual buffer */
|
|
|
|
p -= AR_BUFFERS * PAGE_SIZE;
|
|
|
|
}
|
2007-02-06 22:49:30 +03:00
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
p = handle_ar_packets(ctx, p, end);
|
|
|
|
if (p != end) {
|
|
|
|
if (p > end)
|
|
|
|
ar_context_abort(ctx, "inconsistent descriptor");
|
|
|
|
goto error;
|
|
|
|
}
|
2007-02-06 22:49:30 +03:00
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
ctx->pointer = p;
|
|
|
|
ar_recycle_buffers(ctx, end_buffer_index);
|
2007-02-06 22:49:30 +03:00
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
return;
|
2010-10-25 13:42:20 +04:00
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
error:
|
|
|
|
ctx->pointer = NULL;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2010-11-30 10:25:17 +03:00
|
|
|
static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
|
|
|
|
unsigned int descriptors_offset, u32 regs)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
2020-09-01 14:48:33 +03:00
|
|
|
struct device *dev = ohci->card.device;
|
2010-11-26 10:57:31 +03:00
|
|
|
unsigned int i;
|
|
|
|
dma_addr_t dma_addr;
|
|
|
|
struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
|
|
|
|
struct descriptor *d;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-02-06 22:49:31 +03:00
|
|
|
ctx->regs = regs;
|
|
|
|
ctx->ohci = ohci;
|
2006-12-20 03:58:35 +03:00
|
|
|
tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
|
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
for (i = 0; i < AR_BUFFERS; i++) {
|
2020-09-01 14:48:33 +03:00
|
|
|
ctx->pages[i] = dma_alloc_pages(dev, PAGE_SIZE, &dma_addr,
|
|
|
|
DMA_FROM_DEVICE, GFP_KERNEL);
|
2010-11-26 10:57:31 +03:00
|
|
|
if (!ctx->pages[i])
|
|
|
|
goto out_of_memory;
|
|
|
|
set_page_private(ctx->pages[i], dma_addr);
|
2020-09-01 14:48:33 +03:00
|
|
|
dma_sync_single_for_device(dev, dma_addr, PAGE_SIZE,
|
|
|
|
DMA_FROM_DEVICE);
|
2010-11-26 10:57:31 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < AR_BUFFERS; i++)
|
|
|
|
pages[i] = ctx->pages[i];
|
|
|
|
for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
|
|
|
|
pages[AR_BUFFERS + i] = ctx->pages[i];
|
2014-11-16 23:08:49 +03:00
|
|
|
ctx->buffer = vmap(pages, ARRAY_SIZE(pages), VM_MAP, PAGE_KERNEL);
|
2010-11-26 10:57:31 +03:00
|
|
|
if (!ctx->buffer)
|
|
|
|
goto out_of_memory;
|
|
|
|
|
2010-11-30 10:25:17 +03:00
|
|
|
ctx->descriptors = ohci->misc_buffer + descriptors_offset;
|
|
|
|
ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
|
2010-11-26 10:57:31 +03:00
|
|
|
|
|
|
|
for (i = 0; i < AR_BUFFERS; i++) {
|
|
|
|
d = &ctx->descriptors[i];
|
|
|
|
d->req_count = cpu_to_le16(PAGE_SIZE);
|
|
|
|
d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
|
|
|
|
DESCRIPTOR_STATUS |
|
|
|
|
DESCRIPTOR_BRANCH_ALWAYS);
|
|
|
|
d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
|
|
|
|
d->branch_address = cpu_to_le32(ctx->descriptors_bus +
|
|
|
|
ar_next_buffer_index(i) * sizeof(struct descriptor));
|
|
|
|
}
|
2007-02-06 22:49:30 +03:00
|
|
|
|
2007-05-31 03:06:35 +04:00
|
|
|
return 0;
|
2010-11-26 10:57:31 +03:00
|
|
|
|
|
|
|
out_of_memory:
|
|
|
|
ar_context_release(ctx);
|
|
|
|
|
|
|
|
return -ENOMEM;
|
2007-05-31 03:06:35 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ar_context_run(struct ar_context *ctx)
|
|
|
|
{
|
2010-11-26 10:57:31 +03:00
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
for (i = 0; i < AR_BUFFERS; i++)
|
|
|
|
ar_context_link_page(ctx, i);
|
2007-05-31 03:06:35 +04:00
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
ctx->pointer = ctx->buffer;
|
2007-05-31 03:06:35 +04:00
|
|
|
|
2010-11-26 10:57:31 +03:00
|
|
|
reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
|
2007-05-08 04:33:35 +04:00
|
|
|
reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
2007-03-04 16:45:18 +03:00
|
|
|
|
2008-12-14 23:47:04 +03:00
|
|
|
static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
{
|
2011-04-12 09:54:59 +04:00
|
|
|
__le16 branch;
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
|
2011-04-12 09:54:59 +04:00
|
|
|
branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
|
|
|
|
/* figure out which descriptor the branch address goes in */
|
2011-04-12 09:54:59 +04:00
|
|
|
if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
return d;
|
|
|
|
else
|
|
|
|
return d + z - 1;
|
|
|
|
}
|
|
|
|
|
2007-02-17 01:34:39 +03:00
|
|
|
static void context_tasklet(unsigned long data)
|
|
|
|
{
|
|
|
|
struct context *ctx = (struct context *) data;
|
|
|
|
struct descriptor *d, *last;
|
|
|
|
u32 address;
|
|
|
|
int z;
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
struct descriptor_buffer *desc;
|
2007-02-17 01:34:39 +03:00
|
|
|
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
desc = list_entry(ctx->buffer_list.next,
|
|
|
|
struct descriptor_buffer, list);
|
|
|
|
last = ctx->last;
|
2007-02-17 01:34:39 +03:00
|
|
|
while (last->branch_address != 0) {
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
struct descriptor_buffer *old_desc = desc;
|
2007-02-17 01:34:39 +03:00
|
|
|
address = le32_to_cpu(last->branch_address);
|
|
|
|
z = address & 0xf;
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
address &= ~0xf;
|
2011-10-16 01:12:23 +04:00
|
|
|
ctx->current_bus = address;
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
|
|
|
|
/* If the branch address points to a buffer outside of the
|
|
|
|
* current buffer, advance to the next buffer. */
|
|
|
|
if (address < desc->buffer_bus ||
|
|
|
|
address >= desc->buffer_bus + desc->used)
|
|
|
|
desc = list_entry(desc->list.next,
|
|
|
|
struct descriptor_buffer, list);
|
|
|
|
d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
last = find_branch_descriptor(d, z);
|
2007-02-17 01:34:39 +03:00
|
|
|
|
|
|
|
if (!ctx->callback(ctx, d, last))
|
|
|
|
break;
|
|
|
|
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
if (old_desc != desc) {
|
|
|
|
/* If we've advanced to the next buffer, move the
|
|
|
|
* previous buffer to the free list. */
|
|
|
|
unsigned long flags;
|
|
|
|
old_desc->used = 0;
|
|
|
|
spin_lock_irqsave(&ctx->ohci->lock, flags);
|
|
|
|
list_move_tail(&old_desc->list, &ctx->buffer_list);
|
|
|
|
spin_unlock_irqrestore(&ctx->ohci->lock, flags);
|
|
|
|
}
|
|
|
|
ctx->last = last;
|
2007-02-17 01:34:39 +03:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
/*
|
|
|
|
* Allocate a new buffer and add it to the list of free buffers for this
|
|
|
|
* context. Must be called with ohci->lock held.
|
|
|
|
*/
|
2008-12-14 23:47:04 +03:00
|
|
|
static int context_add_buffer(struct context *ctx)
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
{
|
|
|
|
struct descriptor_buffer *desc;
|
treewide: Remove uninitialized_var() usage
Using uninitialized_var() is dangerous as it papers over real bugs[1]
(or can in the future), and suppresses unrelated compiler warnings
(e.g. "unused variable"). If the compiler thinks it is uninitialized,
either simply initialize the variable or make compiler changes.
In preparation for removing[2] the[3] macro[4], remove all remaining
needless uses with the following script:
git grep '\buninitialized_var\b' | cut -d: -f1 | sort -u | \
xargs perl -pi -e \
's/\buninitialized_var\(([^\)]+)\)/\1/g;
s:\s*/\* (GCC be quiet|to make compiler happy) \*/$::g;'
drivers/video/fbdev/riva/riva_hw.c was manually tweaked to avoid
pathological white-space.
No outstanding warnings were found building allmodconfig with GCC 9.3.0
for x86_64, i386, arm64, arm, powerpc, powerpc64le, s390x, mips, sparc64,
alpha, and m68k.
[1] https://lore.kernel.org/lkml/20200603174714.192027-1-glider@google.com/
[2] https://lore.kernel.org/lkml/CA+55aFw+Vbj0i=1TGqCR5vQkCzWJ0QxK6CernOU6eedsudAixw@mail.gmail.com/
[3] https://lore.kernel.org/lkml/CA+55aFwgbgqhbp1fkxvRKEpzyR5J8n1vKT1VZdz9knmPuXhOeg@mail.gmail.com/
[4] https://lore.kernel.org/lkml/CA+55aFz2500WfbKXAx8s67wrm9=yVJu65TpLgN_ybYNv0VEOKA@mail.gmail.com/
Reviewed-by: Leon Romanovsky <leonro@mellanox.com> # drivers/infiniband and mlx4/mlx5
Acked-by: Jason Gunthorpe <jgg@mellanox.com> # IB
Acked-by: Kalle Valo <kvalo@codeaurora.org> # wireless drivers
Reviewed-by: Chao Yu <yuchao0@huawei.com> # erofs
Signed-off-by: Kees Cook <keescook@chromium.org>
2020-06-03 23:09:38 +03:00
|
|
|
dma_addr_t bus_addr;
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
int offset;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* 16MB of descriptors should be far more than enough for any DMA
|
|
|
|
* program. This will catch run-away userspace or DoS attacks.
|
|
|
|
*/
|
|
|
|
if (ctx->total_allocation >= 16*1024*1024)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
|
|
|
|
&bus_addr, GFP_ATOMIC);
|
|
|
|
if (!desc)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
offset = (void *)&desc->buffer - (void *)desc;
|
2017-11-03 14:28:57 +03:00
|
|
|
/*
|
|
|
|
* Some controllers, like JMicron ones, always issue 0x20-byte DMA reads
|
|
|
|
* for descriptors, even 0x10-byte ones. This can cause page faults when
|
|
|
|
* an IOMMU is in use and the oversized read crosses a page boundary.
|
|
|
|
* Work around this by always leaving at least 0x10 bytes of padding.
|
|
|
|
*/
|
|
|
|
desc->buffer_size = PAGE_SIZE - offset - 0x10;
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
desc->buffer_bus = bus_addr + offset;
|
|
|
|
desc->used = 0;
|
|
|
|
|
|
|
|
list_add_tail(&desc->list, &ctx->buffer_list);
|
|
|
|
ctx->total_allocation += PAGE_SIZE;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-12-14 23:47:04 +03:00
|
|
|
static int context_init(struct context *ctx, struct fw_ohci *ohci,
|
|
|
|
u32 regs, descriptor_callback_t callback)
|
2007-02-17 01:34:39 +03:00
|
|
|
{
|
|
|
|
ctx->ohci = ohci;
|
|
|
|
ctx->regs = regs;
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
ctx->total_allocation = 0;
|
|
|
|
|
|
|
|
INIT_LIST_HEAD(&ctx->buffer_list);
|
|
|
|
if (context_add_buffer(ctx) < 0)
|
2007-02-17 01:34:39 +03:00
|
|
|
return -ENOMEM;
|
|
|
|
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
ctx->buffer_tail = list_entry(ctx->buffer_list.next,
|
|
|
|
struct descriptor_buffer, list);
|
|
|
|
|
2007-02-17 01:34:39 +03:00
|
|
|
tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
|
|
|
|
ctx->callback = callback;
|
|
|
|
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
|
|
|
* We put a dummy descriptor in the buffer that has a NULL
|
2007-02-17 01:34:39 +03:00
|
|
|
* branch address and looks like it's been sent. That way we
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
* have a descriptor to append DMA programs to.
|
2007-05-08 04:33:32 +04:00
|
|
|
*/
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
|
|
|
|
ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
|
|
|
|
ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
|
|
|
|
ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
|
|
|
|
ctx->last = ctx->buffer_tail->buffer;
|
|
|
|
ctx->prev = ctx->buffer_tail->buffer;
|
firewire: ohci: fix VIA VT6306 video reception
Add quirk for VT6306 wake bit behavior.
VT6306 seems to reread the wrong descriptor when the wake bit is
written. work around by putting a copy of the branch address in the
first descriptor of the block.
[Stefan R: This fixes the known broken video reception via gstreamer
on VIA VT6306. 100% repeatable testcase:
$ gst-launch-0.10 dv1394src \! dvdemux \! dvdec \! xvimagesink
with a camcorder or other DV source connected. Likewise for MPEG2-TS
reception via gstreamer, e.g. from TV settop boxes.
Perhaps this also fixes dv4l on VT6306, but this is as yet untested.
Kino, dvgrab or FFADO had not been affected by this chip quirk.
Additional comments from Andy:]
I've looked into some problems with the wake bit on a vt6306 family
chip (1106:3044, rev 46).
I used this firewire card in a mythtv setup (ISO receive MPEG2 stream)
with Debian 2.6.32 kernels for ~2 years without problems.
Since upgrading to 3.2, I've been having problems with the input stream
freezing -- input data stops until I restart mythtv (I expect closing
and reopening the device would be sufficient). This happens
infrequently, maybe one out of 20 recordings. I eventually determined
that the problem is more likely to occur if the system is loaded.
I isolated the kernel version as the triggering SW factor and then
specifically the change from dualbuffer back to packet-per-buffer DMA
mode.
The possibility that the controller does not properly respond to the
wake bit was suggested in
https://bugzilla.redhat.com/show_bug.cgi?id=415841, but not proven.
Based on the fact that dualbuffer mode worked while packet-per-buffer
has trouble, I guessed that upon seeing the wake bit written, the vt6306
controller only checks the branch address in the first descriptor of the
block, even if that is not the correct place to look (because the block
has multiple descriptors).
This theory seems to be correct. When the ISO reception is hung, I am
able to resume it by manually writing the branch address to the first
descriptor in the block, and then writing the wake bit.
I've had luck so far with the attached patch, so I'm including it. It's
probably not a complete solution -- I haven't tested transmit modes to
see whether they have a similar issue.
I doubt that the quirk test is any cheaper than just writing the extra
branch address in all cases, but it does reduce the risk of breaking
other hardware.
[Stefan R: omitted QUIRK_NO_MSI from VT6306 quirks table entry,
changed whitespace]
Signed-off-by: Andy Leiserson <andy@leiserson.org>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2013-04-24 20:10:32 +04:00
|
|
|
ctx->prev_z = 1;
|
2007-02-17 01:34:39 +03:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-12-14 23:47:04 +03:00
|
|
|
static void context_release(struct context *ctx)
|
2007-02-17 01:34:39 +03:00
|
|
|
{
|
|
|
|
struct fw_card *card = &ctx->ohci->card;
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
struct descriptor_buffer *desc, *tmp;
|
2007-02-17 01:34:39 +03:00
|
|
|
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
|
|
|
|
dma_free_coherent(card->device, PAGE_SIZE, desc,
|
|
|
|
desc->buffer_bus -
|
|
|
|
((void *)&desc->buffer - (void *)desc));
|
2007-02-17 01:34:39 +03:00
|
|
|
}
|
|
|
|
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
/* Must be called with ohci->lock held */
|
2008-12-14 23:47:04 +03:00
|
|
|
static struct descriptor *context_get_descriptors(struct context *ctx,
|
|
|
|
int z, dma_addr_t *d_bus)
|
2007-02-17 01:34:39 +03:00
|
|
|
{
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
struct descriptor *d = NULL;
|
|
|
|
struct descriptor_buffer *desc = ctx->buffer_tail;
|
|
|
|
|
|
|
|
if (z * sizeof(*d) > desc->buffer_size)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
if (z * sizeof(*d) > desc->buffer_size - desc->used) {
|
|
|
|
/* No room for the descriptor in this buffer, so advance to the
|
|
|
|
* next one. */
|
2007-02-17 01:34:39 +03:00
|
|
|
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
if (desc->list.next == &ctx->buffer_list) {
|
|
|
|
/* If there is no free buffer next in the list,
|
|
|
|
* allocate one. */
|
|
|
|
if (context_add_buffer(ctx) < 0)
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
desc = list_entry(desc->list.next,
|
|
|
|
struct descriptor_buffer, list);
|
|
|
|
ctx->buffer_tail = desc;
|
|
|
|
}
|
2007-02-17 01:34:39 +03:00
|
|
|
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
d = desc->buffer + desc->used / sizeof(*d);
|
2007-05-10 03:23:14 +04:00
|
|
|
memset(d, 0, z * sizeof(*d));
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
*d_bus = desc->buffer_bus + desc->used;
|
2007-02-17 01:34:39 +03:00
|
|
|
|
|
|
|
return d;
|
|
|
|
}
|
|
|
|
|
2007-02-17 01:34:40 +03:00
|
|
|
static void context_run(struct context *ctx, u32 extra)
|
2007-02-17 01:34:39 +03:00
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = ctx->ohci;
|
|
|
|
|
2007-05-08 04:33:35 +04:00
|
|
|
reg_write(ohci, COMMAND_PTR(ctx->regs),
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
le32_to_cpu(ctx->last->branch_address));
|
2007-05-08 04:33:35 +04:00
|
|
|
reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
|
|
|
|
reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
|
2010-12-24 16:42:46 +03:00
|
|
|
ctx->running = true;
|
2007-02-17 01:34:39 +03:00
|
|
|
flush_writes(ohci);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void context_append(struct context *ctx,
|
|
|
|
struct descriptor *d, int z, int extra)
|
|
|
|
{
|
|
|
|
dma_addr_t d_bus;
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
struct descriptor_buffer *desc = ctx->buffer_tail;
|
firewire: ohci: fix VIA VT6306 video reception
Add quirk for VT6306 wake bit behavior.
VT6306 seems to reread the wrong descriptor when the wake bit is
written. work around by putting a copy of the branch address in the
first descriptor of the block.
[Stefan R: This fixes the known broken video reception via gstreamer
on VIA VT6306. 100% repeatable testcase:
$ gst-launch-0.10 dv1394src \! dvdemux \! dvdec \! xvimagesink
with a camcorder or other DV source connected. Likewise for MPEG2-TS
reception via gstreamer, e.g. from TV settop boxes.
Perhaps this also fixes dv4l on VT6306, but this is as yet untested.
Kino, dvgrab or FFADO had not been affected by this chip quirk.
Additional comments from Andy:]
I've looked into some problems with the wake bit on a vt6306 family
chip (1106:3044, rev 46).
I used this firewire card in a mythtv setup (ISO receive MPEG2 stream)
with Debian 2.6.32 kernels for ~2 years without problems.
Since upgrading to 3.2, I've been having problems with the input stream
freezing -- input data stops until I restart mythtv (I expect closing
and reopening the device would be sufficient). This happens
infrequently, maybe one out of 20 recordings. I eventually determined
that the problem is more likely to occur if the system is loaded.
I isolated the kernel version as the triggering SW factor and then
specifically the change from dualbuffer back to packet-per-buffer DMA
mode.
The possibility that the controller does not properly respond to the
wake bit was suggested in
https://bugzilla.redhat.com/show_bug.cgi?id=415841, but not proven.
Based on the fact that dualbuffer mode worked while packet-per-buffer
has trouble, I guessed that upon seeing the wake bit written, the vt6306
controller only checks the branch address in the first descriptor of the
block, even if that is not the correct place to look (because the block
has multiple descriptors).
This theory seems to be correct. When the ISO reception is hung, I am
able to resume it by manually writing the branch address to the first
descriptor in the block, and then writing the wake bit.
I've had luck so far with the attached patch, so I'm including it. It's
probably not a complete solution -- I haven't tested transmit modes to
see whether they have a similar issue.
I doubt that the quirk test is any cheaper than just writing the extra
branch address in all cases, but it does reduce the risk of breaking
other hardware.
[Stefan R: omitted QUIRK_NO_MSI from VT6306 quirks table entry,
changed whitespace]
Signed-off-by: Andy Leiserson <andy@leiserson.org>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2013-04-24 20:10:32 +04:00
|
|
|
struct descriptor *d_branch;
|
2007-02-17 01:34:39 +03:00
|
|
|
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
|
2007-02-17 01:34:39 +03:00
|
|
|
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
desc->used += (z + extra) * sizeof(*d);
|
2010-07-27 15:20:33 +04:00
|
|
|
|
|
|
|
wmb(); /* finish init of new descriptors before branch_address update */
|
firewire: ohci: fix VIA VT6306 video reception
Add quirk for VT6306 wake bit behavior.
VT6306 seems to reread the wrong descriptor when the wake bit is
written. work around by putting a copy of the branch address in the
first descriptor of the block.
[Stefan R: This fixes the known broken video reception via gstreamer
on VIA VT6306. 100% repeatable testcase:
$ gst-launch-0.10 dv1394src \! dvdemux \! dvdec \! xvimagesink
with a camcorder or other DV source connected. Likewise for MPEG2-TS
reception via gstreamer, e.g. from TV settop boxes.
Perhaps this also fixes dv4l on VT6306, but this is as yet untested.
Kino, dvgrab or FFADO had not been affected by this chip quirk.
Additional comments from Andy:]
I've looked into some problems with the wake bit on a vt6306 family
chip (1106:3044, rev 46).
I used this firewire card in a mythtv setup (ISO receive MPEG2 stream)
with Debian 2.6.32 kernels for ~2 years without problems.
Since upgrading to 3.2, I've been having problems with the input stream
freezing -- input data stops until I restart mythtv (I expect closing
and reopening the device would be sufficient). This happens
infrequently, maybe one out of 20 recordings. I eventually determined
that the problem is more likely to occur if the system is loaded.
I isolated the kernel version as the triggering SW factor and then
specifically the change from dualbuffer back to packet-per-buffer DMA
mode.
The possibility that the controller does not properly respond to the
wake bit was suggested in
https://bugzilla.redhat.com/show_bug.cgi?id=415841, but not proven.
Based on the fact that dualbuffer mode worked while packet-per-buffer
has trouble, I guessed that upon seeing the wake bit written, the vt6306
controller only checks the branch address in the first descriptor of the
block, even if that is not the correct place to look (because the block
has multiple descriptors).
This theory seems to be correct. When the ISO reception is hung, I am
able to resume it by manually writing the branch address to the first
descriptor in the block, and then writing the wake bit.
I've had luck so far with the attached patch, so I'm including it. It's
probably not a complete solution -- I haven't tested transmit modes to
see whether they have a similar issue.
I doubt that the quirk test is any cheaper than just writing the extra
branch address in all cases, but it does reduce the risk of breaking
other hardware.
[Stefan R: omitted QUIRK_NO_MSI from VT6306 quirks table entry,
changed whitespace]
Signed-off-by: Andy Leiserson <andy@leiserson.org>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2013-04-24 20:10:32 +04:00
|
|
|
|
|
|
|
d_branch = find_branch_descriptor(ctx->prev, ctx->prev_z);
|
|
|
|
d_branch->branch_address = cpu_to_le32(d_bus | z);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* VT6306 incorrectly checks only the single descriptor at the
|
|
|
|
* CommandPtr when the wake bit is written, so if it's a
|
|
|
|
* multi-descriptor block starting with an INPUT_MORE, put a copy of
|
|
|
|
* the branch address in the first descriptor.
|
|
|
|
*
|
|
|
|
* Not doing this for transmit contexts since not sure how it interacts
|
|
|
|
* with skip addresses.
|
|
|
|
*/
|
|
|
|
if (unlikely(ctx->ohci->quirks & QUIRK_IR_WAKE) &&
|
|
|
|
d_branch != ctx->prev &&
|
|
|
|
(ctx->prev->control & cpu_to_le16(DESCRIPTOR_CMD)) ==
|
|
|
|
cpu_to_le16(DESCRIPTOR_INPUT_MORE)) {
|
|
|
|
ctx->prev->branch_address = cpu_to_le32(d_bus | z);
|
|
|
|
}
|
|
|
|
|
|
|
|
ctx->prev = d;
|
|
|
|
ctx->prev_z = z;
|
2007-02-17 01:34:39 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void context_stop(struct context *ctx)
|
|
|
|
{
|
2011-12-21 00:32:46 +04:00
|
|
|
struct fw_ohci *ohci = ctx->ohci;
|
2007-02-17 01:34:39 +03:00
|
|
|
u32 reg;
|
2007-02-17 01:34:42 +03:00
|
|
|
int i;
|
2007-02-17 01:34:39 +03:00
|
|
|
|
2011-12-21 00:32:46 +04:00
|
|
|
reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
|
2010-12-24 16:42:46 +03:00
|
|
|
ctx->running = false;
|
2007-02-17 01:34:39 +03:00
|
|
|
|
firewire: ohci: reduce potential context_stop latency
Stopping an isochronous reception DMA context takes two loop iterations
in context_stop on several controllers (JMicron, NEC, VIA). But there
is no extra delay necessary between these two reg_read trials; the MMIO
reads themselves are slow enough. Hence bring back the behavior from
before commit dd6254e5c0efe01ad255188898cb3dadf98cb56d "firewire: ohci:
remove superfluous posted write flushes" on these controllers by means
of an "if (i)" condition.
Isochronous context stop is performed in preemptible contexts (and only
rarely), hence this change is of little impact. (Besides, Agere and TI
controllers always, or almost always, have the context stopped already
at the first ContextControl read.)
More important is asynchronous transmit context stop, which is performed
while local interrupts are disabled (on the two AT DMAs in
bus_reset_tasklet, i.e. after a self-ID-complete event). In my
experience with several controllers, tested with a usermode AT-request
transmitter as well as with FTP transmission over firewire-net, the AT
contexts were luckily already stopped at the first ContextControl read,
i.e. never required another MMIO read let alone mdelay. A possible
explanation for this is that the controllers which I tested perhaps stop
AT DMA before they perform the self-ID reception DMA.
But we cannot be sure about that and should keep the interrupts-disabled
busy loop as short as possible. Hence, query the ContextControl
register in 1000 udelay(10) intervals instead of 10 udelay(1000)
intervals. I understand from an estimation by Clemens Ladisch that
stopping a busy DMA context should take microseconds or at worst tens of
microseconds, not milliseconds.
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2011-06-12 16:30:57 +04:00
|
|
|
for (i = 0; i < 1000; i++) {
|
2011-12-21 00:32:46 +04:00
|
|
|
reg = reg_read(ohci, CONTROL_SET(ctx->regs));
|
2007-02-17 01:34:42 +03:00
|
|
|
if ((reg & CONTEXT_ACTIVE) == 0)
|
2009-01-05 22:43:23 +03:00
|
|
|
return;
|
2007-02-17 01:34:42 +03:00
|
|
|
|
firewire: ohci: reduce potential context_stop latency
Stopping an isochronous reception DMA context takes two loop iterations
in context_stop on several controllers (JMicron, NEC, VIA). But there
is no extra delay necessary between these two reg_read trials; the MMIO
reads themselves are slow enough. Hence bring back the behavior from
before commit dd6254e5c0efe01ad255188898cb3dadf98cb56d "firewire: ohci:
remove superfluous posted write flushes" on these controllers by means
of an "if (i)" condition.
Isochronous context stop is performed in preemptible contexts (and only
rarely), hence this change is of little impact. (Besides, Agere and TI
controllers always, or almost always, have the context stopped already
at the first ContextControl read.)
More important is asynchronous transmit context stop, which is performed
while local interrupts are disabled (on the two AT DMAs in
bus_reset_tasklet, i.e. after a self-ID-complete event). In my
experience with several controllers, tested with a usermode AT-request
transmitter as well as with FTP transmission over firewire-net, the AT
contexts were luckily already stopped at the first ContextControl read,
i.e. never required another MMIO read let alone mdelay. A possible
explanation for this is that the controllers which I tested perhaps stop
AT DMA before they perform the self-ID reception DMA.
But we cannot be sure about that and should keep the interrupts-disabled
busy loop as short as possible. Hence, query the ContextControl
register in 1000 udelay(10) intervals instead of 10 udelay(1000)
intervals. I understand from an estimation by Clemens Ladisch that
stopping a busy DMA context should take microseconds or at worst tens of
microseconds, not milliseconds.
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2011-06-12 16:30:57 +04:00
|
|
|
if (i)
|
|
|
|
udelay(10);
|
2007-02-17 01:34:42 +03:00
|
|
|
}
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "DMA context still active (0x%08x)\n", reg);
|
2007-02-17 01:34:39 +03:00
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-03-07 20:12:49 +03:00
|
|
|
struct driver_data {
|
2011-04-11 11:57:54 +04:00
|
|
|
u8 inline_data[8];
|
2007-03-07 20:12:49 +03:00
|
|
|
struct fw_packet *packet;
|
|
|
|
};
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
|
|
|
* This function apppends a packet to the DMA queue for transmission.
|
2007-03-07 20:12:49 +03:00
|
|
|
* Must always be called with the ochi->lock held to ensure proper
|
2007-05-08 04:33:32 +04:00
|
|
|
* generation handling and locking around packet queue manipulation.
|
|
|
|
*/
|
2008-12-14 23:47:04 +03:00
|
|
|
static int at_context_queue_packet(struct context *ctx,
|
|
|
|
struct fw_packet *packet)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = ctx->ohci;
|
treewide: Remove uninitialized_var() usage
Using uninitialized_var() is dangerous as it papers over real bugs[1]
(or can in the future), and suppresses unrelated compiler warnings
(e.g. "unused variable"). If the compiler thinks it is uninitialized,
either simply initialize the variable or make compiler changes.
In preparation for removing[2] the[3] macro[4], remove all remaining
needless uses with the following script:
git grep '\buninitialized_var\b' | cut -d: -f1 | sort -u | \
xargs perl -pi -e \
's/\buninitialized_var\(([^\)]+)\)/\1/g;
s:\s*/\* (GCC be quiet|to make compiler happy) \*/$::g;'
drivers/video/fbdev/riva/riva_hw.c was manually tweaked to avoid
pathological white-space.
No outstanding warnings were found building allmodconfig with GCC 9.3.0
for x86_64, i386, arm64, arm, powerpc, powerpc64le, s390x, mips, sparc64,
alpha, and m68k.
[1] https://lore.kernel.org/lkml/20200603174714.192027-1-glider@google.com/
[2] https://lore.kernel.org/lkml/CA+55aFw+Vbj0i=1TGqCR5vQkCzWJ0QxK6CernOU6eedsudAixw@mail.gmail.com/
[3] https://lore.kernel.org/lkml/CA+55aFwgbgqhbp1fkxvRKEpzyR5J8n1vKT1VZdz9knmPuXhOeg@mail.gmail.com/
[4] https://lore.kernel.org/lkml/CA+55aFz2500WfbKXAx8s67wrm9=yVJu65TpLgN_ybYNv0VEOKA@mail.gmail.com/
Reviewed-by: Leon Romanovsky <leonro@mellanox.com> # drivers/infiniband and mlx4/mlx5
Acked-by: Jason Gunthorpe <jgg@mellanox.com> # IB
Acked-by: Kalle Valo <kvalo@codeaurora.org> # wireless drivers
Reviewed-by: Chao Yu <yuchao0@huawei.com> # erofs
Signed-off-by: Kees Cook <keescook@chromium.org>
2020-06-03 23:09:38 +03:00
|
|
|
dma_addr_t d_bus, payload_bus;
|
2007-03-07 20:12:49 +03:00
|
|
|
struct driver_data *driver_data;
|
|
|
|
struct descriptor *d, *last;
|
|
|
|
__le32 *header;
|
2006-12-20 03:58:35 +03:00
|
|
|
int z, tcode;
|
|
|
|
|
2007-03-07 20:12:49 +03:00
|
|
|
d = context_get_descriptors(ctx, 4, &d_bus);
|
|
|
|
if (d == NULL) {
|
|
|
|
packet->ack = RCODE_SEND_ERROR;
|
|
|
|
return -1;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2007-05-08 04:33:35 +04:00
|
|
|
d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
|
2007-03-07 20:12:49 +03:00
|
|
|
d[0].res_count = cpu_to_le16(packet->timestamp);
|
|
|
|
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
2012-09-20 05:48:02 +04:00
|
|
|
* The DMA format for asynchronous link packets is different
|
2006-12-20 03:58:35 +03:00
|
|
|
* from the IEEE1394 layout, so shift the fields around
|
2010-11-30 10:24:47 +03:00
|
|
|
* accordingly.
|
2007-05-08 04:33:32 +04:00
|
|
|
*/
|
2007-03-07 20:12:49 +03:00
|
|
|
|
2010-11-30 10:24:47 +03:00
|
|
|
tcode = (packet->header[0] >> 4) & 0x0f;
|
2007-03-07 20:12:49 +03:00
|
|
|
header = (__le32 *) &d[1];
|
2010-11-30 10:24:47 +03:00
|
|
|
switch (tcode) {
|
|
|
|
case TCODE_WRITE_QUADLET_REQUEST:
|
|
|
|
case TCODE_WRITE_BLOCK_REQUEST:
|
|
|
|
case TCODE_WRITE_RESPONSE:
|
|
|
|
case TCODE_READ_QUADLET_REQUEST:
|
|
|
|
case TCODE_READ_BLOCK_REQUEST:
|
|
|
|
case TCODE_READ_QUADLET_RESPONSE:
|
|
|
|
case TCODE_READ_BLOCK_RESPONSE:
|
|
|
|
case TCODE_LOCK_REQUEST:
|
|
|
|
case TCODE_LOCK_RESPONSE:
|
2007-03-07 20:12:49 +03:00
|
|
|
header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
|
|
|
|
(packet->speed << 16));
|
|
|
|
header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
|
|
|
|
(packet->header[0] & 0xffff0000));
|
|
|
|
header[2] = cpu_to_le32(packet->header[2]);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
if (TCODE_IS_BLOCK_PACKET(tcode))
|
2007-03-07 20:12:49 +03:00
|
|
|
header[3] = cpu_to_le32(packet->header[3]);
|
2006-12-20 03:58:35 +03:00
|
|
|
else
|
2007-03-07 20:12:49 +03:00
|
|
|
header[3] = (__force __le32) packet->header[3];
|
|
|
|
|
|
|
|
d[0].req_count = cpu_to_le16(packet->header_length);
|
2009-03-05 21:08:40 +03:00
|
|
|
break;
|
|
|
|
|
2010-11-30 10:24:47 +03:00
|
|
|
case TCODE_LINK_INTERNAL:
|
2007-03-07 20:12:49 +03:00
|
|
|
header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
|
|
|
|
(packet->speed << 16));
|
2010-11-30 10:24:47 +03:00
|
|
|
header[1] = cpu_to_le32(packet->header[1]);
|
|
|
|
header[2] = cpu_to_le32(packet->header[2]);
|
2007-03-07 20:12:49 +03:00
|
|
|
d[0].req_count = cpu_to_le16(12);
|
2010-07-18 15:00:50 +04:00
|
|
|
|
2010-11-30 10:24:47 +03:00
|
|
|
if (is_ping_packet(&packet->header[1]))
|
2010-07-18 15:00:50 +04:00
|
|
|
d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
|
2009-03-05 21:08:40 +03:00
|
|
|
break;
|
|
|
|
|
2010-11-30 10:24:47 +03:00
|
|
|
case TCODE_STREAM_DATA:
|
2009-03-05 21:08:40 +03:00
|
|
|
header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
|
|
|
|
(packet->speed << 16));
|
|
|
|
header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
|
|
|
|
d[0].req_count = cpu_to_le16(8);
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
/* BUG(); */
|
|
|
|
packet->ack = RCODE_SEND_ERROR;
|
|
|
|
return -1;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2011-04-11 11:57:54 +04:00
|
|
|
BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
|
2007-03-07 20:12:49 +03:00
|
|
|
driver_data = (struct driver_data *) &d[3];
|
|
|
|
driver_data->packet = packet;
|
2007-03-27 03:18:19 +04:00
|
|
|
packet->driver_data = driver_data;
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
|
2007-03-07 20:12:49 +03:00
|
|
|
if (packet->payload_length > 0) {
|
2011-04-11 11:57:54 +04:00
|
|
|
if (packet->payload_length > sizeof(driver_data->inline_data)) {
|
|
|
|
payload_bus = dma_map_single(ohci->card.device,
|
|
|
|
packet->payload,
|
|
|
|
packet->payload_length,
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
if (dma_mapping_error(ohci->card.device, payload_bus)) {
|
|
|
|
packet->ack = RCODE_SEND_ERROR;
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
packet->payload_bus = payload_bus;
|
|
|
|
packet->payload_mapped = true;
|
|
|
|
} else {
|
|
|
|
memcpy(driver_data->inline_data, packet->payload,
|
|
|
|
packet->payload_length);
|
|
|
|
payload_bus = d_bus + 3 * sizeof(*d);
|
2007-03-07 20:12:49 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
d[2].req_count = cpu_to_le16(packet->payload_length);
|
|
|
|
d[2].data_address = cpu_to_le32(payload_bus);
|
|
|
|
last = &d[2];
|
|
|
|
z = 3;
|
2006-12-20 03:58:35 +03:00
|
|
|
} else {
|
2007-03-07 20:12:49 +03:00
|
|
|
last = &d[0];
|
|
|
|
z = 2;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2007-05-08 04:33:35 +04:00
|
|
|
last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
|
|
|
|
DESCRIPTOR_IRQ_ALWAYS |
|
|
|
|
DESCRIPTOR_BRANCH_ALWAYS);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2011-02-26 17:08:35 +03:00
|
|
|
/* FIXME: Document how the locking works. */
|
|
|
|
if (ohci->generation != packet->generation) {
|
2009-10-14 22:40:10 +04:00
|
|
|
if (packet->payload_mapped)
|
2007-08-29 21:40:28 +04:00
|
|
|
dma_unmap_single(ohci->card.device, payload_bus,
|
|
|
|
packet->payload_length, DMA_TO_DEVICE);
|
2007-03-07 20:12:49 +03:00
|
|
|
packet->ack = RCODE_GENERATION;
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
|
|
|
context_append(ctx, d, z, 4 - z);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2011-05-16 10:10:10 +04:00
|
|
|
if (ctx->running)
|
2011-05-02 11:33:56 +04:00
|
|
|
reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
|
2011-05-16 10:10:10 +04:00
|
|
|
else
|
2007-03-07 20:12:49 +03:00
|
|
|
context_run(ctx, 0);
|
|
|
|
|
|
|
|
return 0;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2010-12-24 16:40:15 +03:00
|
|
|
static void at_context_flush(struct context *ctx)
|
|
|
|
{
|
|
|
|
tasklet_disable(&ctx->tasklet);
|
|
|
|
|
|
|
|
ctx->flushing = true;
|
|
|
|
context_tasklet((unsigned long)ctx);
|
|
|
|
ctx->flushing = false;
|
|
|
|
|
|
|
|
tasklet_enable(&ctx->tasklet);
|
|
|
|
}
|
|
|
|
|
2007-03-07 20:12:49 +03:00
|
|
|
static int handle_at_packet(struct context *context,
|
|
|
|
struct descriptor *d,
|
|
|
|
struct descriptor *last)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
2007-03-07 20:12:49 +03:00
|
|
|
struct driver_data *driver_data;
|
2006-12-20 03:58:35 +03:00
|
|
|
struct fw_packet *packet;
|
2007-03-07 20:12:49 +03:00
|
|
|
struct fw_ohci *ohci = context->ohci;
|
2006-12-20 03:58:35 +03:00
|
|
|
int evt;
|
|
|
|
|
2010-12-24 16:40:15 +03:00
|
|
|
if (last->transfer_status == 0 && !context->flushing)
|
2007-03-07 20:12:49 +03:00
|
|
|
/* This descriptor isn't done yet, stop iteration. */
|
|
|
|
return 0;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-03-07 20:12:49 +03:00
|
|
|
driver_data = (struct driver_data *) &d[3];
|
|
|
|
packet = driver_data->packet;
|
|
|
|
if (packet == NULL)
|
|
|
|
/* This packet was cancelled, just continue. */
|
|
|
|
return 1;
|
2007-02-06 22:49:32 +03:00
|
|
|
|
2009-10-14 22:40:10 +04:00
|
|
|
if (packet->payload_mapped)
|
2008-12-10 02:20:38 +03:00
|
|
|
dma_unmap_single(ohci->card.device, packet->payload_bus,
|
2006-12-20 03:58:35 +03:00
|
|
|
packet->payload_length, DMA_TO_DEVICE);
|
|
|
|
|
2007-03-07 20:12:49 +03:00
|
|
|
evt = le16_to_cpu(last->transfer_status) & 0x1f;
|
|
|
|
packet->timestamp = le16_to_cpu(last->res_count);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2011-12-21 00:32:46 +04:00
|
|
|
log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
|
2008-03-21 00:04:36 +03:00
|
|
|
|
2007-03-07 20:12:49 +03:00
|
|
|
switch (evt) {
|
|
|
|
case OHCI1394_evt_timeout:
|
|
|
|
/* Async response transmit timed out. */
|
|
|
|
packet->ack = RCODE_CANCELLED;
|
|
|
|
break;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-03-07 20:12:49 +03:00
|
|
|
case OHCI1394_evt_flushed:
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
|
|
|
* The packet was flushed should give same error as
|
|
|
|
* when we try to use a stale generation count.
|
|
|
|
*/
|
2007-03-07 20:12:49 +03:00
|
|
|
packet->ack = RCODE_GENERATION;
|
|
|
|
break;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-03-07 20:12:49 +03:00
|
|
|
case OHCI1394_evt_missing_ack:
|
2010-12-24 16:40:15 +03:00
|
|
|
if (context->flushing)
|
|
|
|
packet->ack = RCODE_GENERATION;
|
|
|
|
else {
|
|
|
|
/*
|
|
|
|
* Using a valid (current) generation count, but the
|
|
|
|
* node is not on the bus or not sending acks.
|
|
|
|
*/
|
|
|
|
packet->ack = RCODE_NO_ACK;
|
|
|
|
}
|
2007-03-07 20:12:49 +03:00
|
|
|
break;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-03-07 20:12:49 +03:00
|
|
|
case ACK_COMPLETE + 0x10:
|
|
|
|
case ACK_PENDING + 0x10:
|
|
|
|
case ACK_BUSY_X + 0x10:
|
|
|
|
case ACK_BUSY_A + 0x10:
|
|
|
|
case ACK_BUSY_B + 0x10:
|
|
|
|
case ACK_DATA_ERROR + 0x10:
|
|
|
|
case ACK_TYPE_ERROR + 0x10:
|
|
|
|
packet->ack = evt - 0x10;
|
|
|
|
break;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2010-12-24 16:40:15 +03:00
|
|
|
case OHCI1394_evt_no_status:
|
|
|
|
if (context->flushing) {
|
|
|
|
packet->ack = RCODE_GENERATION;
|
|
|
|
break;
|
|
|
|
}
|
2020-08-24 01:36:59 +03:00
|
|
|
fallthrough;
|
2010-12-24 16:40:15 +03:00
|
|
|
|
2007-03-07 20:12:49 +03:00
|
|
|
default:
|
|
|
|
packet->ack = RCODE_SEND_ERROR;
|
|
|
|
break;
|
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-03-07 20:12:49 +03:00
|
|
|
packet->callback(packet, &ohci->card, packet->ack);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-03-07 20:12:49 +03:00
|
|
|
return 1;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2007-05-08 04:33:35 +04:00
|
|
|
#define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
|
|
|
|
#define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
|
|
|
|
#define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
|
|
|
|
#define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
|
|
|
|
#define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
|
2007-01-26 08:38:26 +03:00
|
|
|
|
2008-12-14 23:47:04 +03:00
|
|
|
static void handle_local_rom(struct fw_ohci *ohci,
|
|
|
|
struct fw_packet *packet, u32 csr)
|
2007-01-26 08:38:26 +03:00
|
|
|
{
|
|
|
|
struct fw_packet response;
|
|
|
|
int tcode, length, i;
|
|
|
|
|
2007-05-08 04:33:35 +04:00
|
|
|
tcode = HEADER_GET_TCODE(packet->header[0]);
|
2007-01-26 08:38:26 +03:00
|
|
|
if (TCODE_IS_BLOCK_PACKET(tcode))
|
2007-05-08 04:33:35 +04:00
|
|
|
length = HEADER_GET_DATA_LENGTH(packet->header[3]);
|
2007-01-26 08:38:26 +03:00
|
|
|
else
|
|
|
|
length = 4;
|
|
|
|
|
|
|
|
i = csr - CSR_CONFIG_ROM;
|
|
|
|
if (i + length > CONFIG_ROM_SIZE) {
|
|
|
|
fw_fill_response(&response, packet->header,
|
|
|
|
RCODE_ADDRESS_ERROR, NULL, 0);
|
|
|
|
} else if (!TCODE_IS_READ_REQUEST(tcode)) {
|
|
|
|
fw_fill_response(&response, packet->header,
|
|
|
|
RCODE_TYPE_ERROR, NULL, 0);
|
|
|
|
} else {
|
|
|
|
fw_fill_response(&response, packet->header, RCODE_COMPLETE,
|
|
|
|
(void *) ohci->config_rom + i, length);
|
|
|
|
}
|
|
|
|
|
|
|
|
fw_core_handle_response(&ohci->card, &response);
|
|
|
|
}
|
|
|
|
|
2008-12-14 23:47:04 +03:00
|
|
|
static void handle_local_lock(struct fw_ohci *ohci,
|
|
|
|
struct fw_packet *packet, u32 csr)
|
2007-01-26 08:38:26 +03:00
|
|
|
{
|
|
|
|
struct fw_packet response;
|
2010-04-12 12:35:44 +04:00
|
|
|
int tcode, length, ext_tcode, sel, try;
|
2007-01-26 08:38:26 +03:00
|
|
|
__be32 *payload, lock_old;
|
|
|
|
u32 lock_arg, lock_data;
|
|
|
|
|
2007-05-08 04:33:35 +04:00
|
|
|
tcode = HEADER_GET_TCODE(packet->header[0]);
|
|
|
|
length = HEADER_GET_DATA_LENGTH(packet->header[3]);
|
2007-01-26 08:38:26 +03:00
|
|
|
payload = packet->payload;
|
2007-05-08 04:33:35 +04:00
|
|
|
ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
|
2007-01-26 08:38:26 +03:00
|
|
|
|
|
|
|
if (tcode == TCODE_LOCK_REQUEST &&
|
|
|
|
ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
|
|
|
|
lock_arg = be32_to_cpu(payload[0]);
|
|
|
|
lock_data = be32_to_cpu(payload[1]);
|
|
|
|
} else if (tcode == TCODE_READ_QUADLET_REQUEST) {
|
|
|
|
lock_arg = 0;
|
|
|
|
lock_data = 0;
|
|
|
|
} else {
|
|
|
|
fw_fill_response(&response, packet->header,
|
|
|
|
RCODE_TYPE_ERROR, NULL, 0);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
sel = (csr - CSR_BUS_MANAGER_ID) / 4;
|
|
|
|
reg_write(ohci, OHCI1394_CSRData, lock_data);
|
|
|
|
reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
|
|
|
|
reg_write(ohci, OHCI1394_CSRControl, sel);
|
|
|
|
|
2010-04-12 12:35:44 +04:00
|
|
|
for (try = 0; try < 20; try++)
|
|
|
|
if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
|
|
|
|
lock_old = cpu_to_be32(reg_read(ohci,
|
|
|
|
OHCI1394_CSRData));
|
|
|
|
fw_fill_response(&response, packet->header,
|
|
|
|
RCODE_COMPLETE,
|
|
|
|
&lock_old, sizeof(lock_old));
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "swap not done (CSR lock timeout)\n");
|
2010-04-12 12:35:44 +04:00
|
|
|
fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
|
2007-01-26 08:38:26 +03:00
|
|
|
|
|
|
|
out:
|
|
|
|
fw_core_handle_response(&ohci->card, &response);
|
|
|
|
}
|
|
|
|
|
2008-12-14 23:47:04 +03:00
|
|
|
static void handle_local_request(struct context *ctx, struct fw_packet *packet)
|
2007-01-26 08:38:26 +03:00
|
|
|
{
|
2010-04-12 12:35:30 +04:00
|
|
|
u64 offset, csr;
|
2007-01-26 08:38:26 +03:00
|
|
|
|
2007-03-07 20:12:55 +03:00
|
|
|
if (ctx == &ctx->ohci->at_request_ctx) {
|
|
|
|
packet->ack = ACK_PENDING;
|
|
|
|
packet->callback(packet, &ctx->ohci->card, packet->ack);
|
|
|
|
}
|
2007-01-26 08:38:26 +03:00
|
|
|
|
|
|
|
offset =
|
|
|
|
((unsigned long long)
|
2007-05-08 04:33:35 +04:00
|
|
|
HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
|
2007-01-26 08:38:26 +03:00
|
|
|
packet->header[2];
|
|
|
|
csr = offset - CSR_REGISTER_BASE;
|
|
|
|
|
|
|
|
/* Handle config rom reads. */
|
|
|
|
if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
|
|
|
|
handle_local_rom(ctx->ohci, packet, csr);
|
|
|
|
else switch (csr) {
|
|
|
|
case CSR_BUS_MANAGER_ID:
|
|
|
|
case CSR_BANDWIDTH_AVAILABLE:
|
|
|
|
case CSR_CHANNELS_AVAILABLE_HI:
|
|
|
|
case CSR_CHANNELS_AVAILABLE_LO:
|
|
|
|
handle_local_lock(ctx->ohci, packet, csr);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
if (ctx == &ctx->ohci->at_request_ctx)
|
|
|
|
fw_core_handle_request(&ctx->ohci->card, packet);
|
|
|
|
else
|
|
|
|
fw_core_handle_response(&ctx->ohci->card, packet);
|
|
|
|
break;
|
|
|
|
}
|
2007-03-07 20:12:55 +03:00
|
|
|
|
|
|
|
if (ctx == &ctx->ohci->at_response_ctx) {
|
|
|
|
packet->ack = ACK_COMPLETE;
|
|
|
|
packet->callback(packet, &ctx->ohci->card, packet->ack);
|
|
|
|
}
|
2007-01-26 08:38:26 +03:00
|
|
|
}
|
2007-01-26 08:38:04 +03:00
|
|
|
|
2008-12-14 23:47:04 +03:00
|
|
|
static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
|
|
|
unsigned long flags;
|
2008-12-14 23:45:45 +03:00
|
|
|
int ret;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
spin_lock_irqsave(&ctx->ohci->lock, flags);
|
|
|
|
|
2007-05-08 04:33:35 +04:00
|
|
|
if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
|
2007-01-26 08:38:04 +03:00
|
|
|
ctx->ohci->generation == packet->generation) {
|
2007-01-26 08:38:26 +03:00
|
|
|
spin_unlock_irqrestore(&ctx->ohci->lock, flags);
|
|
|
|
handle_local_request(ctx, packet);
|
|
|
|
return;
|
2007-01-26 08:38:04 +03:00
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2008-12-14 23:45:45 +03:00
|
|
|
ret = at_context_queue_packet(ctx, packet);
|
2006-12-20 03:58:35 +03:00
|
|
|
spin_unlock_irqrestore(&ctx->ohci->lock, flags);
|
|
|
|
|
2008-12-14 23:45:45 +03:00
|
|
|
if (ret < 0)
|
2007-03-07 20:12:49 +03:00
|
|
|
packet->callback(packet, &ctx->ohci->card, packet->ack);
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2011-01-10 19:21:35 +03:00
|
|
|
static void detect_dead_context(struct fw_ohci *ohci,
|
|
|
|
const char *name, unsigned int regs)
|
|
|
|
{
|
|
|
|
u32 ctl;
|
|
|
|
|
|
|
|
ctl = reg_read(ohci, CONTROL_SET(regs));
|
2012-03-05 00:34:21 +04:00
|
|
|
if (ctl & CONTEXT_DEAD)
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "DMA context %s has stopped, error code: %s\n",
|
2011-12-21 00:32:46 +04:00
|
|
|
name, evts[ctl & 0x1f]);
|
2011-01-10 19:21:35 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void handle_dead_contexts(struct fw_ohci *ohci)
|
|
|
|
{
|
|
|
|
unsigned int i;
|
|
|
|
char name[8];
|
|
|
|
|
|
|
|
detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
|
|
|
|
detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
|
|
|
|
detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
|
|
|
|
detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
|
|
|
|
for (i = 0; i < 32; ++i) {
|
|
|
|
if (!(ohci->it_context_support & (1 << i)))
|
|
|
|
continue;
|
|
|
|
sprintf(name, "IT%u", i);
|
|
|
|
detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
|
|
|
|
}
|
|
|
|
for (i = 0; i < 32; ++i) {
|
|
|
|
if (!(ohci->ir_context_support & (1 << i)))
|
|
|
|
continue;
|
|
|
|
sprintf(name, "IR%u", i);
|
|
|
|
detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
|
|
|
|
}
|
|
|
|
/* TODO: maybe try to flush and restart the dead contexts */
|
|
|
|
}
|
|
|
|
|
2010-06-10 10:33:07 +04:00
|
|
|
static u32 cycle_timer_ticks(u32 cycle_timer)
|
|
|
|
{
|
|
|
|
u32 ticks;
|
|
|
|
|
|
|
|
ticks = cycle_timer & 0xfff;
|
|
|
|
ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
|
|
|
|
ticks += (3072 * 8000) * (cycle_timer >> 25);
|
|
|
|
|
|
|
|
return ticks;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Some controllers exhibit one or more of the following bugs when updating the
|
|
|
|
* iso cycle timer register:
|
|
|
|
* - When the lowest six bits are wrapping around to zero, a read that happens
|
|
|
|
* at the same time will return garbage in the lowest ten bits.
|
|
|
|
* - When the cycleOffset field wraps around to zero, the cycleCount field is
|
|
|
|
* not incremented for about 60 ns.
|
|
|
|
* - Occasionally, the entire register reads zero.
|
|
|
|
*
|
|
|
|
* To catch these, we read the register three times and ensure that the
|
|
|
|
* difference between each two consecutive reads is approximately the same, i.e.
|
|
|
|
* less than twice the other. Furthermore, any negative difference indicates an
|
|
|
|
* error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
|
|
|
|
* execute, so we have enough precision to compute the ratio of the differences.)
|
|
|
|
*/
|
|
|
|
static u32 get_cycle_time(struct fw_ohci *ohci)
|
|
|
|
{
|
|
|
|
u32 c0, c1, c2;
|
|
|
|
u32 t0, t1, t2;
|
|
|
|
s32 diff01, diff12;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
|
|
|
|
|
|
|
|
if (ohci->quirks & QUIRK_CYCLE_TIMER) {
|
|
|
|
i = 0;
|
|
|
|
c1 = c2;
|
|
|
|
c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
|
|
|
|
do {
|
|
|
|
c0 = c1;
|
|
|
|
c1 = c2;
|
|
|
|
c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
|
|
|
|
t0 = cycle_timer_ticks(c0);
|
|
|
|
t1 = cycle_timer_ticks(c1);
|
|
|
|
t2 = cycle_timer_ticks(c2);
|
|
|
|
diff01 = t1 - t0;
|
|
|
|
diff12 = t2 - t1;
|
|
|
|
} while ((diff01 <= 0 || diff12 <= 0 ||
|
|
|
|
diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
|
|
|
|
&& i++ < 20);
|
|
|
|
}
|
|
|
|
|
|
|
|
return c2;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function has to be called at least every 64 seconds. The bus_time
|
|
|
|
* field stores not only the upper 25 bits of the BUS_TIME register but also
|
|
|
|
* the most significant bit of the cycle timer in bit 6 so that we can detect
|
|
|
|
* changes in this bit.
|
|
|
|
*/
|
|
|
|
static u32 update_bus_time(struct fw_ohci *ohci)
|
|
|
|
{
|
|
|
|
u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
|
|
|
|
|
2012-05-24 21:29:19 +04:00
|
|
|
if (unlikely(!ohci->bus_time_running)) {
|
|
|
|
reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_cycle64Seconds);
|
2018-06-18 17:19:24 +03:00
|
|
|
ohci->bus_time = (lower_32_bits(ktime_get_seconds()) & ~0x7f) |
|
2012-05-24 21:29:19 +04:00
|
|
|
(cycle_time_seconds & 0x40);
|
|
|
|
ohci->bus_time_running = true;
|
|
|
|
}
|
|
|
|
|
2010-06-10 10:33:07 +04:00
|
|
|
if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
|
|
|
|
ohci->bus_time += 0x40;
|
|
|
|
|
|
|
|
return ohci->bus_time | cycle_time_seconds;
|
|
|
|
}
|
|
|
|
|
2011-09-13 00:23:53 +04:00
|
|
|
static int get_status_for_port(struct fw_ohci *ohci, int port_index)
|
|
|
|
{
|
|
|
|
int reg;
|
|
|
|
|
|
|
|
mutex_lock(&ohci->phy_reg_mutex);
|
|
|
|
reg = write_phy_reg(ohci, 7, port_index);
|
2011-09-19 02:17:37 +04:00
|
|
|
if (reg >= 0)
|
|
|
|
reg = read_phy_reg(ohci, 8);
|
2011-09-13 00:23:53 +04:00
|
|
|
mutex_unlock(&ohci->phy_reg_mutex);
|
|
|
|
if (reg < 0)
|
|
|
|
return reg;
|
|
|
|
|
|
|
|
switch (reg & 0x0f) {
|
|
|
|
case 0x06:
|
|
|
|
return 2; /* is child node (connected to parent node) */
|
|
|
|
case 0x0e:
|
|
|
|
return 3; /* is parent node (connected to child node) */
|
|
|
|
}
|
|
|
|
return 1; /* not connected */
|
|
|
|
}
|
|
|
|
|
|
|
|
static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
|
|
|
|
int self_id_count)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
u32 entry;
|
2011-09-19 02:17:37 +04:00
|
|
|
|
2011-09-13 00:23:53 +04:00
|
|
|
for (i = 0; i < self_id_count; i++) {
|
|
|
|
entry = ohci->self_id_buffer[i];
|
|
|
|
if ((self_id & 0xff000000) == (entry & 0xff000000))
|
|
|
|
return -1;
|
|
|
|
if ((self_id & 0xff000000) < (entry & 0xff000000))
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
return i;
|
|
|
|
}
|
|
|
|
|
2012-09-03 23:17:50 +04:00
|
|
|
static int initiated_reset(struct fw_ohci *ohci)
|
|
|
|
{
|
|
|
|
int reg;
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
mutex_lock(&ohci->phy_reg_mutex);
|
|
|
|
reg = write_phy_reg(ohci, 7, 0xe0); /* Select page 7 */
|
|
|
|
if (reg >= 0) {
|
|
|
|
reg = read_phy_reg(ohci, 8);
|
|
|
|
reg |= 0x40;
|
|
|
|
reg = write_phy_reg(ohci, 8, reg); /* set PMODE bit */
|
|
|
|
if (reg >= 0) {
|
|
|
|
reg = read_phy_reg(ohci, 12); /* read register 12 */
|
|
|
|
if (reg >= 0) {
|
|
|
|
if ((reg & 0x08) == 0x08) {
|
|
|
|
/* bit 3 indicates "initiated reset" */
|
|
|
|
ret = 0x2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
mutex_unlock(&ohci->phy_reg_mutex);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2011-09-13 00:23:53 +04:00
|
|
|
/*
|
2011-09-19 02:17:37 +04:00
|
|
|
* TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
|
|
|
|
* attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
|
|
|
|
* Construct the selfID from phy register contents.
|
2011-09-13 00:23:53 +04:00
|
|
|
*/
|
|
|
|
static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
|
|
|
|
{
|
2011-09-19 02:17:37 +04:00
|
|
|
int reg, i, pos, status;
|
|
|
|
/* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
|
|
|
|
u32 self_id = 0x8040c800;
|
2011-09-13 00:23:53 +04:00
|
|
|
|
|
|
|
reg = reg_read(ohci, OHCI1394_NodeID);
|
|
|
|
if (!(reg & OHCI1394_NodeID_idValid)) {
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci,
|
|
|
|
"node ID not valid, new bus reset in progress\n");
|
2011-09-13 00:23:53 +04:00
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
self_id |= ((reg & 0x3f) << 24); /* phy ID */
|
|
|
|
|
2011-09-19 02:17:37 +04:00
|
|
|
reg = ohci_read_phy_reg(&ohci->card, 4);
|
2011-09-13 00:23:53 +04:00
|
|
|
if (reg < 0)
|
|
|
|
return reg;
|
|
|
|
self_id |= ((reg & 0x07) << 8); /* power class */
|
|
|
|
|
2011-09-19 02:17:37 +04:00
|
|
|
reg = ohci_read_phy_reg(&ohci->card, 1);
|
2011-09-13 00:23:53 +04:00
|
|
|
if (reg < 0)
|
|
|
|
return reg;
|
|
|
|
self_id |= ((reg & 0x3f) << 16); /* gap count */
|
|
|
|
|
|
|
|
for (i = 0; i < 3; i++) {
|
|
|
|
status = get_status_for_port(ohci, i);
|
|
|
|
if (status < 0)
|
|
|
|
return status;
|
|
|
|
self_id |= ((status & 0x3) << (6 - (i * 2)));
|
|
|
|
}
|
|
|
|
|
2012-09-03 23:17:50 +04:00
|
|
|
self_id |= initiated_reset(ohci);
|
|
|
|
|
2011-09-13 00:23:53 +04:00
|
|
|
pos = get_self_id_pos(ohci, self_id, self_id_count);
|
|
|
|
if (pos >= 0) {
|
|
|
|
memmove(&(ohci->self_id_buffer[pos+1]),
|
|
|
|
&(ohci->self_id_buffer[pos]),
|
|
|
|
(self_id_count - pos) * sizeof(*ohci->self_id_buffer));
|
|
|
|
ohci->self_id_buffer[pos] = self_id;
|
|
|
|
self_id_count++;
|
|
|
|
}
|
|
|
|
return self_id_count;
|
|
|
|
}
|
|
|
|
|
2011-07-26 00:16:24 +04:00
|
|
|
static void bus_reset_work(struct work_struct *work)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
2011-07-26 00:16:24 +04:00
|
|
|
struct fw_ohci *ohci =
|
|
|
|
container_of(work, struct fw_ohci, bus_reset_work);
|
2012-04-09 23:39:53 +04:00
|
|
|
int self_id_count, generation, new_generation, i, j;
|
|
|
|
u32 reg;
|
2007-07-25 21:18:08 +04:00
|
|
|
void *free_rom = NULL;
|
|
|
|
dma_addr_t free_rom_bus = 0;
|
2010-06-10 10:36:37 +04:00
|
|
|
bool is_new_root;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
reg = reg_read(ohci, OHCI1394_NodeID);
|
|
|
|
if (!(reg & OHCI1394_NodeID_idValid)) {
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci,
|
|
|
|
"node ID not valid, new bus reset in progress\n");
|
2006-12-20 03:58:35 +03:00
|
|
|
return;
|
|
|
|
}
|
2007-08-30 02:11:40 +04:00
|
|
|
if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci, "malconfigured bus\n");
|
2007-08-30 02:11:40 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
|
|
|
|
OHCI1394_NodeID_nodeNumber);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2010-06-10 10:36:37 +04:00
|
|
|
is_new_root = (reg & OHCI1394_NodeID_root) != 0;
|
|
|
|
if (!(ohci->is_root && is_new_root))
|
|
|
|
reg_write(ohci, OHCI1394_LinkControlSet,
|
|
|
|
OHCI1394_LinkControl_cycleMaster);
|
|
|
|
ohci->is_root = is_new_root;
|
|
|
|
|
2008-03-19 23:40:32 +03:00
|
|
|
reg = reg_read(ohci, OHCI1394_SelfIDCount);
|
|
|
|
if (reg & OHCI1394_SelfIDCount_selfIDError) {
|
2013-03-27 14:56:01 +04:00
|
|
|
ohci_notice(ohci, "self ID receive error\n");
|
2008-03-19 23:40:32 +03:00
|
|
|
return;
|
|
|
|
}
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
|
|
|
* The count in the SelfIDCount register is the number of
|
2006-12-20 03:58:35 +03:00
|
|
|
* bytes in the self ID receive buffer. Since we also receive
|
|
|
|
* the inverted quadlets and a header quadlet, we shift one
|
2007-05-08 04:33:32 +04:00
|
|
|
* bit extra to get the actual number of self IDs.
|
|
|
|
*/
|
2009-09-06 20:49:17 +04:00
|
|
|
self_id_count = (reg >> 3) & 0xff;
|
2011-09-13 00:23:53 +04:00
|
|
|
|
|
|
|
if (self_id_count > 252) {
|
2013-03-27 14:56:01 +04:00
|
|
|
ohci_notice(ohci, "bad selfIDSize (%08x)\n", reg);
|
2008-03-20 00:05:02 +03:00
|
|
|
return;
|
|
|
|
}
|
2011-09-13 00:23:53 +04:00
|
|
|
|
2013-08-05 17:10:38 +04:00
|
|
|
generation = (cond_le32_to_cpu(ohci->self_id[0]) >> 16) & 0xff;
|
2007-08-25 16:08:19 +04:00
|
|
|
rmb();
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
|
2013-08-05 17:10:38 +04:00
|
|
|
u32 id = cond_le32_to_cpu(ohci->self_id[i]);
|
|
|
|
u32 id2 = cond_le32_to_cpu(ohci->self_id[i + 1]);
|
2013-03-27 14:56:01 +04:00
|
|
|
|
|
|
|
if (id != ~id2) {
|
firewire: ohci: work around selfID junk due to wrong gap count
If a device's firmware initiates a bus reset by setting the IBR bit in
PHY register 1 without resetting the gap count field to 63 (and without
having sent a PHY configuration packet beforehand), the gap count of
this node will remain at the old value after the bus reset and thus be
inconsistent with the gap count on all other nodes.
The bus manager is supposed to detect the inconsistent gap count values
in the self ID packets and correct them by issuing another bus reset.
However, if the buggy device happens to be the cycle master, and if it
sends a cycle start packet immediately after the bus reset (which is
likely after a long bus reset), then the time between the end of the
selfID phase and the start of the cycle start packet will be based on
the too-small gap count value, so this gap will be too short to be
detected as a subaction gap by the other nodes. This means that the
cycle start packet will be assumed to be self ID data, and will be
stored after the actual self ID quadlets in the self ID buffer.
This garbage in the self ID buffer made firewire-core ignore all of the
self ID data, and thus prevented the Linux bus manager from correcting
the problem. Furthermore, because the bus reset handling was aborted
completely, asynchronous transfers would be no longer handled correctly,
and fw_run_transaction() would hang until the next bus reset.
To fix this, make the detection of inconsistent self IDs more
discriminating: If the invalid data in the self ID buffer looks like
a cycle start packet, we can assume that the previous data in the buffer
is correctly received self ID information, and process it normally.
(We inspect only the first quadlet of the cycle start packet, because
this value is different enough from any valid self ID quadlet, and many
controllers do not store the cycle start packet in five quadlets because
they expect self ID data to have an even number of quadlets.)
This bug has been observed when a bus-powered DesktopKonnekt6 is
switched off with its power button.
Signed-off-by: Clemens Ladisch <clemens@ladisch.de>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2011-10-15 20:14:39 +04:00
|
|
|
/*
|
|
|
|
* If the invalid data looks like a cycle start packet,
|
|
|
|
* it's likely to be the result of the cycle master
|
|
|
|
* having a wrong gap count. In this case, the self IDs
|
|
|
|
* so far are valid and should be processed so that the
|
|
|
|
* bus manager can then correct the gap count.
|
|
|
|
*/
|
2013-03-27 14:56:01 +04:00
|
|
|
if (id == 0xffff008f) {
|
|
|
|
ohci_notice(ohci, "ignoring spurious self IDs\n");
|
firewire: ohci: work around selfID junk due to wrong gap count
If a device's firmware initiates a bus reset by setting the IBR bit in
PHY register 1 without resetting the gap count field to 63 (and without
having sent a PHY configuration packet beforehand), the gap count of
this node will remain at the old value after the bus reset and thus be
inconsistent with the gap count on all other nodes.
The bus manager is supposed to detect the inconsistent gap count values
in the self ID packets and correct them by issuing another bus reset.
However, if the buggy device happens to be the cycle master, and if it
sends a cycle start packet immediately after the bus reset (which is
likely after a long bus reset), then the time between the end of the
selfID phase and the start of the cycle start packet will be based on
the too-small gap count value, so this gap will be too short to be
detected as a subaction gap by the other nodes. This means that the
cycle start packet will be assumed to be self ID data, and will be
stored after the actual self ID quadlets in the self ID buffer.
This garbage in the self ID buffer made firewire-core ignore all of the
self ID data, and thus prevented the Linux bus manager from correcting
the problem. Furthermore, because the bus reset handling was aborted
completely, asynchronous transfers would be no longer handled correctly,
and fw_run_transaction() would hang until the next bus reset.
To fix this, make the detection of inconsistent self IDs more
discriminating: If the invalid data in the self ID buffer looks like
a cycle start packet, we can assume that the previous data in the buffer
is correctly received self ID information, and process it normally.
(We inspect only the first quadlet of the cycle start packet, because
this value is different enough from any valid self ID quadlet, and many
controllers do not store the cycle start packet in five quadlets because
they expect self ID data to have an even number of quadlets.)
This bug has been observed when a bus-powered DesktopKonnekt6 is
switched off with its power button.
Signed-off-by: Clemens Ladisch <clemens@ladisch.de>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2011-10-15 20:14:39 +04:00
|
|
|
self_id_count = j;
|
|
|
|
break;
|
|
|
|
}
|
2013-03-27 14:56:01 +04:00
|
|
|
|
|
|
|
ohci_notice(ohci, "bad self ID %d/%d (%08x != ~%08x)\n",
|
|
|
|
j, self_id_count, id, id2);
|
|
|
|
return;
|
2008-03-19 23:40:32 +03:00
|
|
|
}
|
2013-03-27 14:56:01 +04:00
|
|
|
ohci->self_id_buffer[j] = id;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
2011-09-13 00:23:53 +04:00
|
|
|
|
|
|
|
if (ohci->quirks & QUIRK_TI_SLLZ059) {
|
|
|
|
self_id_count = find_and_insert_self_id(ohci, self_id_count);
|
|
|
|
if (self_id_count < 0) {
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci,
|
|
|
|
"could not construct local self ID\n");
|
2011-09-13 00:23:53 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (self_id_count == 0) {
|
2013-03-27 14:56:01 +04:00
|
|
|
ohci_notice(ohci, "no self IDs\n");
|
2011-09-13 00:23:53 +04:00
|
|
|
return;
|
|
|
|
}
|
2007-08-25 16:08:19 +04:00
|
|
|
rmb();
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
|
|
|
* Check the consistency of the self IDs we just read. The
|
2006-12-20 03:58:35 +03:00
|
|
|
* problem we face is that a new bus reset can start while we
|
|
|
|
* read out the self IDs from the DMA buffer. If this happens,
|
|
|
|
* the DMA buffer will be overwritten with new self IDs and we
|
|
|
|
* will read out inconsistent data. The OHCI specification
|
|
|
|
* (section 11.2) recommends a technique similar to
|
|
|
|
* linux/seqlock.h, where we remember the generation of the
|
|
|
|
* self IDs in the buffer before reading them out and compare
|
|
|
|
* it to the current generation after reading them out. If
|
|
|
|
* the two generations match we know we have a consistent set
|
2007-05-08 04:33:32 +04:00
|
|
|
* of self IDs.
|
|
|
|
*/
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
|
|
|
|
if (new_generation != generation) {
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci, "new bus reset, discarding self ids\n");
|
2006-12-20 03:58:35 +03:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* FIXME: Document how the locking works. */
|
2012-04-09 23:40:33 +04:00
|
|
|
spin_lock_irq(&ohci->lock);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2010-12-24 16:40:15 +03:00
|
|
|
ohci->generation = -1; /* prevent AT packet queueing */
|
2007-03-07 20:12:49 +03:00
|
|
|
context_stop(&ohci->at_request_ctx);
|
|
|
|
context_stop(&ohci->at_response_ctx);
|
2010-12-24 16:40:15 +03:00
|
|
|
|
2012-04-09 23:40:33 +04:00
|
|
|
spin_unlock_irq(&ohci->lock);
|
2010-12-24 16:40:15 +03:00
|
|
|
|
2011-01-01 17:15:40 +03:00
|
|
|
/*
|
|
|
|
* Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
|
|
|
|
* packets in the AT queues and software needs to drain them.
|
|
|
|
* Some OHCI 1.1 controllers (JMicron) apparently require this too.
|
|
|
|
*/
|
2010-12-24 16:40:15 +03:00
|
|
|
at_context_flush(&ohci->at_request_ctx);
|
|
|
|
at_context_flush(&ohci->at_response_ctx);
|
|
|
|
|
2012-04-09 23:40:33 +04:00
|
|
|
spin_lock_irq(&ohci->lock);
|
2010-12-24 16:40:15 +03:00
|
|
|
|
|
|
|
ohci->generation = generation;
|
2006-12-20 03:58:35 +03:00
|
|
|
reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
|
|
|
|
|
2010-02-21 19:58:01 +03:00
|
|
|
if (ohci->quirks & QUIRK_RESET_PACKET)
|
2008-04-13 00:31:25 +04:00
|
|
|
ohci->request_generation = generation;
|
|
|
|
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
|
|
|
* This next bit is unrelated to the AT context stuff but we
|
2006-12-20 03:58:35 +03:00
|
|
|
* have to do it under the spinlock also. If a new config rom
|
|
|
|
* was set up before this reset, the old one is now no longer
|
|
|
|
* in use and we can free it. Update the config rom pointers
|
|
|
|
* to point to the current config rom and clear the
|
2010-03-16 13:47:56 +03:00
|
|
|
* next_config_rom pointer so a new update can take place.
|
2007-05-08 04:33:32 +04:00
|
|
|
*/
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
if (ohci->next_config_rom != NULL) {
|
2007-06-06 03:27:05 +04:00
|
|
|
if (ohci->next_config_rom != ohci->config_rom) {
|
|
|
|
free_rom = ohci->config_rom;
|
|
|
|
free_rom_bus = ohci->config_rom_bus;
|
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
ohci->config_rom = ohci->next_config_rom;
|
|
|
|
ohci->config_rom_bus = ohci->next_config_rom_bus;
|
|
|
|
ohci->next_config_rom = NULL;
|
|
|
|
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
|
|
|
* Restore config_rom image and manually update
|
2006-12-20 03:58:35 +03:00
|
|
|
* config_rom registers. Writing the header quadlet
|
|
|
|
* will indicate that the config rom is ready, so we
|
2007-05-08 04:33:32 +04:00
|
|
|
* do that last.
|
|
|
|
*/
|
2006-12-20 03:58:35 +03:00
|
|
|
reg_write(ohci, OHCI1394_BusOptions,
|
|
|
|
be32_to_cpu(ohci->config_rom[2]));
|
2009-10-08 02:41:59 +04:00
|
|
|
ohci->config_rom[0] = ohci->next_header;
|
|
|
|
reg_write(ohci, OHCI1394_ConfigROMhdr,
|
|
|
|
be32_to_cpu(ohci->next_header));
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2013-12-22 14:34:22 +04:00
|
|
|
if (param_remote_dma) {
|
|
|
|
reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
|
|
|
|
reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
|
|
|
|
}
|
2008-02-28 22:54:43 +03:00
|
|
|
|
2012-04-09 23:40:33 +04:00
|
|
|
spin_unlock_irq(&ohci->lock);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-07-25 21:18:08 +04:00
|
|
|
if (free_rom)
|
|
|
|
dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
|
|
|
|
free_rom, free_rom_bus);
|
|
|
|
|
2011-12-21 00:32:46 +04:00
|
|
|
log_selfids(ohci, generation, self_id_count);
|
2008-03-21 00:04:36 +03:00
|
|
|
|
2007-01-26 08:38:04 +03:00
|
|
|
fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
|
2010-06-12 22:34:50 +04:00
|
|
|
self_id_count, ohci->self_id_buffer,
|
|
|
|
ohci->csr_state_setclear_abdicate);
|
|
|
|
ohci->csr_state_setclear_abdicate = false;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t irq_handler(int irq, void *data)
|
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = data;
|
2010-02-14 20:49:18 +03:00
|
|
|
u32 event, iso_event;
|
2006-12-20 03:58:35 +03:00
|
|
|
int i;
|
|
|
|
|
|
|
|
event = reg_read(ohci, OHCI1394_IntEventClear);
|
|
|
|
|
2007-06-09 21:31:14 +04:00
|
|
|
if (!event || !~event)
|
2006-12-20 03:58:35 +03:00
|
|
|
return IRQ_NONE;
|
|
|
|
|
2010-11-30 10:24:32 +03:00
|
|
|
/*
|
|
|
|
* busReset and postedWriteErr must not be cleared yet
|
|
|
|
* (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
|
|
|
|
*/
|
|
|
|
reg_write(ohci, OHCI1394_IntEventClear,
|
|
|
|
event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
|
2011-12-21 00:32:46 +04:00
|
|
|
log_irqs(ohci, event);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
if (event & OHCI1394_selfIDComplete)
|
2013-08-26 22:50:05 +04:00
|
|
|
queue_work(selfid_workqueue, &ohci->bus_reset_work);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
if (event & OHCI1394_RQPkt)
|
|
|
|
tasklet_schedule(&ohci->ar_request_ctx.tasklet);
|
|
|
|
|
|
|
|
if (event & OHCI1394_RSPkt)
|
|
|
|
tasklet_schedule(&ohci->ar_response_ctx.tasklet);
|
|
|
|
|
|
|
|
if (event & OHCI1394_reqTxComplete)
|
|
|
|
tasklet_schedule(&ohci->at_request_ctx.tasklet);
|
|
|
|
|
|
|
|
if (event & OHCI1394_respTxComplete)
|
|
|
|
tasklet_schedule(&ohci->at_response_ctx.tasklet);
|
|
|
|
|
2010-11-30 10:25:05 +03:00
|
|
|
if (event & OHCI1394_isochRx) {
|
|
|
|
iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
|
|
|
|
reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
|
|
|
|
|
|
|
|
while (iso_event) {
|
|
|
|
i = ffs(iso_event) - 1;
|
|
|
|
tasklet_schedule(
|
|
|
|
&ohci->ir_context_list[i].context.tasklet);
|
|
|
|
iso_event &= ~(1 << i);
|
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2010-11-30 10:25:05 +03:00
|
|
|
if (event & OHCI1394_isochTx) {
|
|
|
|
iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
|
|
|
|
reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2010-11-30 10:25:05 +03:00
|
|
|
while (iso_event) {
|
|
|
|
i = ffs(iso_event) - 1;
|
|
|
|
tasklet_schedule(
|
|
|
|
&ohci->it_context_list[i].context.tasklet);
|
|
|
|
iso_event &= ~(1 << i);
|
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2008-04-04 01:18:23 +04:00
|
|
|
if (unlikely(event & OHCI1394_regAccessFail))
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "register access failure\n");
|
2008-04-04 01:18:23 +04:00
|
|
|
|
2010-11-30 10:24:32 +03:00
|
|
|
if (unlikely(event & OHCI1394_postedWriteErr)) {
|
|
|
|
reg_read(ohci, OHCI1394_PostedWriteAddressHi);
|
|
|
|
reg_read(ohci, OHCI1394_PostedWriteAddressLo);
|
|
|
|
reg_write(ohci, OHCI1394_IntEventClear,
|
|
|
|
OHCI1394_postedWriteErr);
|
2011-09-26 23:44:30 +04:00
|
|
|
if (printk_ratelimit())
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "PCI posted write error\n");
|
2010-11-30 10:24:32 +03:00
|
|
|
}
|
2007-08-20 23:58:30 +04:00
|
|
|
|
2007-12-23 00:14:52 +03:00
|
|
|
if (unlikely(event & OHCI1394_cycleTooLong)) {
|
|
|
|
if (printk_ratelimit())
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci, "isochronous cycle too long\n");
|
2007-12-23 00:14:52 +03:00
|
|
|
reg_write(ohci, OHCI1394_LinkControlSet,
|
|
|
|
OHCI1394_LinkControl_cycleMaster);
|
|
|
|
}
|
|
|
|
|
2009-11-17 20:29:17 +03:00
|
|
|
if (unlikely(event & OHCI1394_cycleInconsistent)) {
|
|
|
|
/*
|
|
|
|
* We need to clear this event bit in order to make
|
|
|
|
* cycleMatch isochronous I/O work. In theory we should
|
|
|
|
* stop active cycleMatch iso contexts now and restart
|
|
|
|
* them at least two cycles later. (FIXME?)
|
|
|
|
*/
|
|
|
|
if (printk_ratelimit())
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci, "isochronous cycle inconsistent\n");
|
2009-11-17 20:29:17 +03:00
|
|
|
}
|
|
|
|
|
2011-01-10 19:21:35 +03:00
|
|
|
if (unlikely(event & OHCI1394_unrecoverableError))
|
|
|
|
handle_dead_contexts(ohci);
|
|
|
|
|
2010-06-10 10:33:07 +04:00
|
|
|
if (event & OHCI1394_cycle64Seconds) {
|
|
|
|
spin_lock(&ohci->lock);
|
|
|
|
update_bus_time(ohci);
|
|
|
|
spin_unlock(&ohci->lock);
|
2010-11-30 10:24:19 +03:00
|
|
|
} else
|
|
|
|
flush_writes(ohci);
|
2010-06-10 10:33:07 +04:00
|
|
|
|
2006-12-20 03:58:35 +03:00
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2007-05-31 03:06:35 +04:00
|
|
|
static int software_reset(struct fw_ohci *ohci)
|
|
|
|
{
|
2011-07-03 19:39:26 +04:00
|
|
|
u32 val;
|
2007-05-31 03:06:35 +04:00
|
|
|
int i;
|
|
|
|
|
|
|
|
reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
|
2011-07-03 19:39:26 +04:00
|
|
|
for (i = 0; i < 500; i++) {
|
|
|
|
val = reg_read(ohci, OHCI1394_HCControlSet);
|
|
|
|
if (!~val)
|
|
|
|
return -ENODEV; /* Card was ejected. */
|
2007-05-31 03:06:35 +04:00
|
|
|
|
2011-07-03 19:39:26 +04:00
|
|
|
if (!(val & OHCI1394_HCControl_softReset))
|
2007-05-31 03:06:35 +04:00
|
|
|
return 0;
|
2011-07-03 19:39:26 +04:00
|
|
|
|
2007-05-31 03:06:35 +04:00
|
|
|
msleep(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
2009-10-08 02:41:59 +04:00
|
|
|
static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
|
|
|
|
{
|
|
|
|
size_t size = length * 4;
|
|
|
|
|
|
|
|
memcpy(dest, src, size);
|
|
|
|
if (size < CONFIG_ROM_SIZE)
|
|
|
|
memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
|
|
|
|
}
|
|
|
|
|
2010-04-04 17:19:54 +04:00
|
|
|
static int configure_1394a_enhancements(struct fw_ohci *ohci)
|
|
|
|
{
|
|
|
|
bool enable_1394a;
|
2010-04-10 18:04:56 +04:00
|
|
|
int ret, clear, set, offset;
|
2010-04-04 17:19:54 +04:00
|
|
|
|
|
|
|
/* Check if the driver should configure link and PHY. */
|
|
|
|
if (!(reg_read(ohci, OHCI1394_HCControlSet) &
|
|
|
|
OHCI1394_HCControl_programPhyEnable))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* Paranoia: check whether the PHY supports 1394a, too. */
|
|
|
|
enable_1394a = false;
|
2010-04-10 18:04:56 +04:00
|
|
|
ret = read_phy_reg(ohci, 2);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
|
|
|
|
ret = read_paged_phy_reg(ohci, 1, 8);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
if (ret >= 1)
|
2010-04-04 17:19:54 +04:00
|
|
|
enable_1394a = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ohci->quirks & QUIRK_NO_1394A)
|
|
|
|
enable_1394a = false;
|
|
|
|
|
|
|
|
/* Configure PHY and link consistently. */
|
|
|
|
if (enable_1394a) {
|
|
|
|
clear = 0;
|
|
|
|
set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
|
|
|
|
} else {
|
|
|
|
clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
|
|
|
|
set = 0;
|
|
|
|
}
|
2010-07-08 18:09:06 +04:00
|
|
|
ret = update_phy_reg(ohci, 5, clear, set);
|
2010-04-10 18:04:56 +04:00
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2010-04-04 17:19:54 +04:00
|
|
|
|
|
|
|
if (enable_1394a)
|
|
|
|
offset = OHCI1394_HCControlSet;
|
|
|
|
else
|
|
|
|
offset = OHCI1394_HCControlClear;
|
|
|
|
reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
|
|
|
|
|
|
|
|
/* Clean up: configuration has been taken care of. */
|
|
|
|
reg_write(ohci, OHCI1394_HCControlClear,
|
|
|
|
OHCI1394_HCControl_programPhyEnable);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-09-13 00:23:53 +04:00
|
|
|
static int probe_tsb41ba3d(struct fw_ohci *ohci)
|
|
|
|
{
|
2011-09-19 11:29:30 +04:00
|
|
|
/* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
|
|
|
|
static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
|
|
|
|
int reg, i;
|
2011-09-13 00:23:53 +04:00
|
|
|
|
|
|
|
reg = read_phy_reg(ohci, 2);
|
|
|
|
if (reg < 0)
|
|
|
|
return reg;
|
2011-09-19 11:29:30 +04:00
|
|
|
if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
|
|
|
|
return 0;
|
2011-09-13 00:23:53 +04:00
|
|
|
|
2011-09-19 11:29:30 +04:00
|
|
|
for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
|
|
|
|
reg = read_paged_phy_reg(ohci, 1, i + 10);
|
|
|
|
if (reg < 0)
|
|
|
|
return reg;
|
|
|
|
if (reg != id[i])
|
|
|
|
return 0;
|
2011-09-13 00:23:53 +04:00
|
|
|
}
|
2011-09-19 11:29:30 +04:00
|
|
|
return 1;
|
2011-09-13 00:23:53 +04:00
|
|
|
}
|
|
|
|
|
2009-10-08 02:41:59 +04:00
|
|
|
static int ohci_enable(struct fw_card *card,
|
|
|
|
const __be32 *config_rom, size_t length)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = fw_ohci(card);
|
2012-05-24 21:29:19 +04:00
|
|
|
u32 lps, version, irqs;
|
2011-09-19 02:17:37 +04:00
|
|
|
int i, ret;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2015-11-01 17:52:13 +03:00
|
|
|
ret = software_reset(ohci);
|
|
|
|
if (ret < 0) {
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "failed to reset ohci card\n");
|
2015-11-01 17:52:13 +03:00
|
|
|
return ret;
|
2007-05-31 03:06:35 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Now enable LPS, which we need in order to start accessing
|
|
|
|
* most of the registers. In fact, on some cards (ALI M5251),
|
|
|
|
* accessing registers in the SClk domain without LPS enabled
|
|
|
|
* will lock up the machine. Wait 50msec to make sure we have
|
2008-03-28 17:02:50 +03:00
|
|
|
* full link enabled. However, with some cards (well, at least
|
|
|
|
* a JMicron PCIe card), we have to try again sometimes.
|
firewire: ohci: Fix 'failed to read phy reg' on FW643 rev8
With the LSI FW643 rev 8 [1], the first commanded bus reset at
the conclusion of ohci_enable() has been observed to fail with
the following messages:
[ 4.884015] firewire_ohci 0000:01:00.0: failed to read phy reg
....
[ 5.684012] firewire_ohci 0000:01:00.0: failed to read phy reg
With drivers/firewire/ohci.c instrumented, the error condition [2]
indicates the PHY arbitration state machine has timed out prior to
enabling PHY LCtrl.
Furthermore, instrumenting ohci_enable() shows that LPS has been
enabled within 1 ms.
Test LPS latching every 1 ms rather than every 50ms.
[1] lspci -v
01:00.0 FireWire (IEEE 1394): LSI Corporation FW643 [TrueFire] PCIe 1394b Controller (rev 08) (prog-if 10 [OHCI])
Subsystem: LSI Corporation FW643 [TrueFire] PCIe 1394b Controller
Flags: bus master, fast devsel, latency 0, IRQ 92
Memory at fbeff000 (64-bit, non-prefetchable) [size=4K]
Capabilities: [44] Power Management version 3
Capabilities: [4c] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [60] Express Endpoint, MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [140] Virtual Channel
Capabilities: [170] Device Serial Number 08-14-43-82-00-00-41-fc
Kernel driver in use: firewire_ohci
Kernel modules: firewire-ohci
[2] instrumented WARNING in read_phy_reg()
[ 4.576010] ------------[ cut here ]------------
[ 4.576035] WARNING: at ./drivers/firewire/ohci.c:570 read_phy_reg+0x93/0xe0 [firewire_ohci]()
[ 4.576050] Hardware name: Precision WorkStation T5400
[ 4.576058] failed to read phy reg:1 (phy(5) @ config enhance:19)
[ 4.576068] Modules linked in: hid_logitech_dj hid_generic(+) usbhid <...snip...>
[ 4.576140] Pid: 61, comm: kworker/2:1 Not tainted 3.8.0-2+fwtest-xeon #2+fwtest
[ 4.576149] Call Trace:
[ 4.576160] [<ffffffff8105468f>] warn_slowpath_common+0x7f/0xc0
[ 4.576168] [<ffffffff81054786>] warn_slowpath_fmt+0x46/0x50
[ 4.576178] [<ffffffffa00caca3>] read_phy_reg+0x93/0xe0 [firewire_ohci]
[ 4.576188] [<ffffffffa00cae19>] ohci_read_phy_reg+0x39/0x60 [firewire_ohci]
[ 4.576203] [<ffffffffa00731ff>] fw_send_phy_config+0xbf/0xe0 [firewire_core]
[ 4.576214] [<ffffffffa006b2d6>] br_work+0x46/0xb0 [firewire_core]
[ 4.576225] [<ffffffff81071e0c>] process_one_work+0x13c/0x500
[ 4.576238] [<ffffffffa006b290>] ? fw_card_initialize+0x180/0x180 [firewire_core]
[ 4.576248] [<ffffffff810737ed>] worker_thread+0x16d/0x470
[ 4.576257] [<ffffffff81073680>] ? busy_worker_rebind_fn+0x100/0x100
[ 4.576266] [<ffffffff8107d160>] kthread+0xc0/0xd0
[ 4.576275] [<ffffffff816a0000>] ? pcpu_dump_alloc_info+0x1cb/0x2c4
[ 4.576284] [<ffffffff8107d0a0>] ? kthread_create_on_node+0x130/0x130
[ 4.576297] [<ffffffff816b2f6c>] ret_from_fork+0x7c/0xb0
[ 4.576305] [<ffffffff8107d0a0>] ? kthread_create_on_node+0x130/0x130
[ 4.576313] ---[ end trace cbc940994b300302 ]---
[Stefan R: Peter also reports a change of behavior with LSI FW323.
Before the patch, there would often occur a lock transaction failure
during firewire-core startup:
[ 6.056022] firewire_core 0000:07:06.0: BM lock failed (timeout), making local node (ffc0) root
This failure no longer happens after the patch, without an obvious
reason for the failure or the fix.]
[Stefan R: Added quirk flag, quirk table entry, and comment.]
Reported-by: Tim Jordan <tim@insipid.org.uk>
Signed-off-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2013-04-29 01:24:08 +04:00
|
|
|
*
|
|
|
|
* TI TSB82AA2 + TSB81BA3(A) cards signal LPS enabled early but
|
|
|
|
* cannot actually use the phy at that time. These need tens of
|
|
|
|
* millisecods pause between LPS write and first phy access too.
|
2007-05-31 03:06:35 +04:00
|
|
|
*/
|
firewire: ohci: Fix 'failed to read phy reg' on FW643 rev8
With the LSI FW643 rev 8 [1], the first commanded bus reset at
the conclusion of ohci_enable() has been observed to fail with
the following messages:
[ 4.884015] firewire_ohci 0000:01:00.0: failed to read phy reg
....
[ 5.684012] firewire_ohci 0000:01:00.0: failed to read phy reg
With drivers/firewire/ohci.c instrumented, the error condition [2]
indicates the PHY arbitration state machine has timed out prior to
enabling PHY LCtrl.
Furthermore, instrumenting ohci_enable() shows that LPS has been
enabled within 1 ms.
Test LPS latching every 1 ms rather than every 50ms.
[1] lspci -v
01:00.0 FireWire (IEEE 1394): LSI Corporation FW643 [TrueFire] PCIe 1394b Controller (rev 08) (prog-if 10 [OHCI])
Subsystem: LSI Corporation FW643 [TrueFire] PCIe 1394b Controller
Flags: bus master, fast devsel, latency 0, IRQ 92
Memory at fbeff000 (64-bit, non-prefetchable) [size=4K]
Capabilities: [44] Power Management version 3
Capabilities: [4c] MSI: Enable+ Count=1/1 Maskable- 64bit+
Capabilities: [60] Express Endpoint, MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [140] Virtual Channel
Capabilities: [170] Device Serial Number 08-14-43-82-00-00-41-fc
Kernel driver in use: firewire_ohci
Kernel modules: firewire-ohci
[2] instrumented WARNING in read_phy_reg()
[ 4.576010] ------------[ cut here ]------------
[ 4.576035] WARNING: at ./drivers/firewire/ohci.c:570 read_phy_reg+0x93/0xe0 [firewire_ohci]()
[ 4.576050] Hardware name: Precision WorkStation T5400
[ 4.576058] failed to read phy reg:1 (phy(5) @ config enhance:19)
[ 4.576068] Modules linked in: hid_logitech_dj hid_generic(+) usbhid <...snip...>
[ 4.576140] Pid: 61, comm: kworker/2:1 Not tainted 3.8.0-2+fwtest-xeon #2+fwtest
[ 4.576149] Call Trace:
[ 4.576160] [<ffffffff8105468f>] warn_slowpath_common+0x7f/0xc0
[ 4.576168] [<ffffffff81054786>] warn_slowpath_fmt+0x46/0x50
[ 4.576178] [<ffffffffa00caca3>] read_phy_reg+0x93/0xe0 [firewire_ohci]
[ 4.576188] [<ffffffffa00cae19>] ohci_read_phy_reg+0x39/0x60 [firewire_ohci]
[ 4.576203] [<ffffffffa00731ff>] fw_send_phy_config+0xbf/0xe0 [firewire_core]
[ 4.576214] [<ffffffffa006b2d6>] br_work+0x46/0xb0 [firewire_core]
[ 4.576225] [<ffffffff81071e0c>] process_one_work+0x13c/0x500
[ 4.576238] [<ffffffffa006b290>] ? fw_card_initialize+0x180/0x180 [firewire_core]
[ 4.576248] [<ffffffff810737ed>] worker_thread+0x16d/0x470
[ 4.576257] [<ffffffff81073680>] ? busy_worker_rebind_fn+0x100/0x100
[ 4.576266] [<ffffffff8107d160>] kthread+0xc0/0xd0
[ 4.576275] [<ffffffff816a0000>] ? pcpu_dump_alloc_info+0x1cb/0x2c4
[ 4.576284] [<ffffffff8107d0a0>] ? kthread_create_on_node+0x130/0x130
[ 4.576297] [<ffffffff816b2f6c>] ret_from_fork+0x7c/0xb0
[ 4.576305] [<ffffffff8107d0a0>] ? kthread_create_on_node+0x130/0x130
[ 4.576313] ---[ end trace cbc940994b300302 ]---
[Stefan R: Peter also reports a change of behavior with LSI FW323.
Before the patch, there would often occur a lock transaction failure
during firewire-core startup:
[ 6.056022] firewire_core 0000:07:06.0: BM lock failed (timeout), making local node (ffc0) root
This failure no longer happens after the patch, without an obvious
reason for the failure or the fix.]
[Stefan R: Added quirk flag, quirk table entry, and comment.]
Reported-by: Tim Jordan <tim@insipid.org.uk>
Signed-off-by: Peter Hurley <peter@hurleysoftware.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2013-04-29 01:24:08 +04:00
|
|
|
|
2007-05-31 03:06:35 +04:00
|
|
|
reg_write(ohci, OHCI1394_HCControlSet,
|
|
|
|
OHCI1394_HCControl_LPS |
|
|
|
|
OHCI1394_HCControl_postedWriteEnable);
|
|
|
|
flush_writes(ohci);
|
2008-03-28 17:02:50 +03:00
|
|
|
|
2014-03-06 23:39:04 +04:00
|
|
|
for (lps = 0, i = 0; !lps && i < 3; i++) {
|
2008-03-28 17:02:50 +03:00
|
|
|
msleep(50);
|
|
|
|
lps = reg_read(ohci, OHCI1394_HCControlSet) &
|
|
|
|
OHCI1394_HCControl_LPS;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!lps) {
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "failed to set Link Power Status\n");
|
2008-03-28 17:02:50 +03:00
|
|
|
return -EIO;
|
|
|
|
}
|
2007-05-31 03:06:35 +04:00
|
|
|
|
2011-09-13 00:23:53 +04:00
|
|
|
if (ohci->quirks & QUIRK_TI_SLLZ059) {
|
2011-09-19 02:17:37 +04:00
|
|
|
ret = probe_tsb41ba3d(ohci);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
|
|
|
if (ret)
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci, "local TSB41BA3D phy\n");
|
2011-09-19 02:17:37 +04:00
|
|
|
else
|
2011-09-13 00:23:53 +04:00
|
|
|
ohci->quirks &= ~QUIRK_TI_SLLZ059;
|
|
|
|
}
|
|
|
|
|
2007-05-31 03:06:35 +04:00
|
|
|
reg_write(ohci, OHCI1394_HCControlClear,
|
|
|
|
OHCI1394_HCControl_noByteSwapData);
|
|
|
|
|
2008-06-05 22:50:53 +04:00
|
|
|
reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
|
2007-05-31 03:06:35 +04:00
|
|
|
reg_write(ohci, OHCI1394_LinkControlSet,
|
|
|
|
OHCI1394_LinkControl_cycleTimerEnable |
|
|
|
|
OHCI1394_LinkControl_cycleMaster);
|
|
|
|
|
|
|
|
reg_write(ohci, OHCI1394_ATRetries,
|
|
|
|
OHCI1394_MAX_AT_REQ_RETRIES |
|
|
|
|
(OHCI1394_MAX_AT_RESP_RETRIES << 4) |
|
2010-06-10 10:34:13 +04:00
|
|
|
(OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
|
|
|
|
(200 << 16));
|
2007-05-31 03:06:35 +04:00
|
|
|
|
2012-05-24 21:29:19 +04:00
|
|
|
ohci->bus_time_running = false;
|
2010-06-10 10:33:07 +04:00
|
|
|
|
2012-06-14 00:29:20 +04:00
|
|
|
for (i = 0; i < 32; i++)
|
|
|
|
if (ohci->ir_context_support & (1 << i))
|
|
|
|
reg_write(ohci, OHCI1394_IsoRcvContextControlClear(i),
|
|
|
|
IR_CONTEXT_MULTI_CHANNEL_MODE);
|
|
|
|
|
2010-06-10 10:40:49 +04:00
|
|
|
version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
|
|
|
|
if (version >= OHCI_VERSION_1_1) {
|
|
|
|
reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
|
|
|
|
0xfffffffe);
|
2010-06-12 22:30:21 +04:00
|
|
|
card->broadcast_channel_auto_allocated = true;
|
2010-06-10 10:40:49 +04:00
|
|
|
}
|
|
|
|
|
2010-06-10 10:35:06 +04:00
|
|
|
/* Get implemented bits of the priority arbitration request counter. */
|
|
|
|
reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
|
|
|
|
ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
|
|
|
|
reg_write(ohci, OHCI1394_FairnessControl, 0);
|
2010-06-12 22:30:21 +04:00
|
|
|
card->priority_budget_implemented = ohci->pri_req_max != 0;
|
2007-05-31 03:06:35 +04:00
|
|
|
|
2014-01-18 20:32:20 +04:00
|
|
|
reg_write(ohci, OHCI1394_PhyUpperBound, FW_MAX_PHYSICAL_RANGE >> 16);
|
2007-05-31 03:06:35 +04:00
|
|
|
reg_write(ohci, OHCI1394_IntEventClear, ~0);
|
|
|
|
reg_write(ohci, OHCI1394_IntMaskClear, ~0);
|
|
|
|
|
2010-04-10 18:04:56 +04:00
|
|
|
ret = configure_1394a_enhancements(ohci);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2010-04-04 17:19:54 +04:00
|
|
|
|
2007-05-31 03:06:35 +04:00
|
|
|
/* Activate link_on bit and contender bit in our self ID packets.*/
|
2010-04-10 18:04:56 +04:00
|
|
|
ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2007-05-31 03:06:35 +04:00
|
|
|
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
|
|
|
* When the link is not yet enabled, the atomic config rom
|
2006-12-20 03:58:35 +03:00
|
|
|
* update mechanism described below in ohci_set_config_rom()
|
|
|
|
* is not active. We have to update ConfigRomHeader and
|
|
|
|
* BusOptions manually, and the write to ConfigROMmap takes
|
|
|
|
* effect immediately. We tie this to the enabling of the
|
|
|
|
* link, so we have a valid config rom before enabling - the
|
|
|
|
* OHCI requires that ConfigROMhdr and BusOptions have valid
|
|
|
|
* values before enabling.
|
|
|
|
*
|
|
|
|
* However, when the ConfigROMmap is written, some controllers
|
|
|
|
* always read back quadlets 0 and 2 from the config rom to
|
|
|
|
* the ConfigRomHeader and BusOptions registers on bus reset.
|
|
|
|
* They shouldn't do that in this initial case where the link
|
|
|
|
* isn't enabled. This means we have to use the same
|
|
|
|
* workaround here, setting the bus header to 0 and then write
|
|
|
|
* the right values in the bus reset tasklet.
|
|
|
|
*/
|
|
|
|
|
2007-06-06 03:27:05 +04:00
|
|
|
if (config_rom) {
|
|
|
|
ohci->next_config_rom =
|
|
|
|
dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
|
|
|
|
&ohci->next_config_rom_bus,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (ohci->next_config_rom == NULL)
|
|
|
|
return -ENOMEM;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2009-10-08 02:41:59 +04:00
|
|
|
copy_config_rom(ohci->next_config_rom, config_rom, length);
|
2007-06-06 03:27:05 +04:00
|
|
|
} else {
|
|
|
|
/*
|
|
|
|
* In the suspend case, config_rom is NULL, which
|
|
|
|
* means that we just reuse the old config rom.
|
|
|
|
*/
|
|
|
|
ohci->next_config_rom = ohci->config_rom;
|
|
|
|
ohci->next_config_rom_bus = ohci->config_rom_bus;
|
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2009-10-08 02:41:59 +04:00
|
|
|
ohci->next_header = ohci->next_config_rom[0];
|
2006-12-20 03:58:35 +03:00
|
|
|
ohci->next_config_rom[0] = 0;
|
|
|
|
reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
|
2007-06-06 03:27:05 +04:00
|
|
|
reg_write(ohci, OHCI1394_BusOptions,
|
|
|
|
be32_to_cpu(ohci->next_config_rom[2]));
|
2006-12-20 03:58:35 +03:00
|
|
|
reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
|
|
|
|
|
|
|
|
reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
|
|
|
|
|
2010-06-05 13:46:49 +04:00
|
|
|
irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
|
|
|
|
OHCI1394_RQPkt | OHCI1394_RSPkt |
|
|
|
|
OHCI1394_isochTx | OHCI1394_isochRx |
|
|
|
|
OHCI1394_postedWriteErr |
|
|
|
|
OHCI1394_selfIDComplete |
|
|
|
|
OHCI1394_regAccessFail |
|
2011-01-10 19:21:35 +03:00
|
|
|
OHCI1394_cycleInconsistent |
|
|
|
|
OHCI1394_unrecoverableError |
|
|
|
|
OHCI1394_cycleTooLong |
|
2010-06-05 13:46:49 +04:00
|
|
|
OHCI1394_masterIntEnable;
|
|
|
|
if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
|
|
|
|
irqs |= OHCI1394_busReset;
|
|
|
|
reg_write(ohci, OHCI1394_IntMaskSet, irqs);
|
|
|
|
|
2006-12-20 03:58:35 +03:00
|
|
|
reg_write(ohci, OHCI1394_HCControlSet,
|
|
|
|
OHCI1394_HCControl_linkEnable |
|
|
|
|
OHCI1394_HCControl_BIBimageValid);
|
2011-04-11 11:56:12 +04:00
|
|
|
|
|
|
|
reg_write(ohci, OHCI1394_LinkControlSet,
|
|
|
|
OHCI1394_LinkControl_rcvSelfID |
|
|
|
|
OHCI1394_LinkControl_rcvPhyPkt);
|
|
|
|
|
|
|
|
ar_context_run(&ohci->ar_request_ctx);
|
2011-05-16 10:10:10 +04:00
|
|
|
ar_context_run(&ohci->ar_response_ctx);
|
|
|
|
|
|
|
|
flush_writes(ohci);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2010-07-08 18:09:06 +04:00
|
|
|
/* We are ready to go, reset bus to finish initialization. */
|
|
|
|
fw_schedule_bus_reset(&ohci->card, false, true);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-12-14 23:47:04 +03:00
|
|
|
static int ohci_set_config_rom(struct fw_card *card,
|
2009-10-08 02:41:59 +04:00
|
|
|
const __be32 *config_rom, size_t length)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
|
|
|
struct fw_ohci *ohci;
|
|
|
|
__be32 *next_config_rom;
|
treewide: Remove uninitialized_var() usage
Using uninitialized_var() is dangerous as it papers over real bugs[1]
(or can in the future), and suppresses unrelated compiler warnings
(e.g. "unused variable"). If the compiler thinks it is uninitialized,
either simply initialize the variable or make compiler changes.
In preparation for removing[2] the[3] macro[4], remove all remaining
needless uses with the following script:
git grep '\buninitialized_var\b' | cut -d: -f1 | sort -u | \
xargs perl -pi -e \
's/\buninitialized_var\(([^\)]+)\)/\1/g;
s:\s*/\* (GCC be quiet|to make compiler happy) \*/$::g;'
drivers/video/fbdev/riva/riva_hw.c was manually tweaked to avoid
pathological white-space.
No outstanding warnings were found building allmodconfig with GCC 9.3.0
for x86_64, i386, arm64, arm, powerpc, powerpc64le, s390x, mips, sparc64,
alpha, and m68k.
[1] https://lore.kernel.org/lkml/20200603174714.192027-1-glider@google.com/
[2] https://lore.kernel.org/lkml/CA+55aFw+Vbj0i=1TGqCR5vQkCzWJ0QxK6CernOU6eedsudAixw@mail.gmail.com/
[3] https://lore.kernel.org/lkml/CA+55aFwgbgqhbp1fkxvRKEpzyR5J8n1vKT1VZdz9knmPuXhOeg@mail.gmail.com/
[4] https://lore.kernel.org/lkml/CA+55aFz2500WfbKXAx8s67wrm9=yVJu65TpLgN_ybYNv0VEOKA@mail.gmail.com/
Reviewed-by: Leon Romanovsky <leonro@mellanox.com> # drivers/infiniband and mlx4/mlx5
Acked-by: Jason Gunthorpe <jgg@mellanox.com> # IB
Acked-by: Kalle Valo <kvalo@codeaurora.org> # wireless drivers
Reviewed-by: Chao Yu <yuchao0@huawei.com> # erofs
Signed-off-by: Kees Cook <keescook@chromium.org>
2020-06-03 23:09:38 +03:00
|
|
|
dma_addr_t next_config_rom_bus;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
ohci = fw_ohci(card);
|
|
|
|
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
|
|
|
* When the OHCI controller is enabled, the config rom update
|
2006-12-20 03:58:35 +03:00
|
|
|
* mechanism is a bit tricky, but easy enough to use. See
|
|
|
|
* section 5.5.6 in the OHCI specification.
|
|
|
|
*
|
|
|
|
* The OHCI controller caches the new config rom address in a
|
|
|
|
* shadow register (ConfigROMmapNext) and needs a bus reset
|
|
|
|
* for the changes to take place. When the bus reset is
|
|
|
|
* detected, the controller loads the new values for the
|
|
|
|
* ConfigRomHeader and BusOptions registers from the specified
|
|
|
|
* config rom and loads ConfigROMmap from the ConfigROMmapNext
|
|
|
|
* shadow register. All automatically and atomically.
|
|
|
|
*
|
|
|
|
* Now, there's a twist to this story. The automatic load of
|
|
|
|
* ConfigRomHeader and BusOptions doesn't honor the
|
|
|
|
* noByteSwapData bit, so with a be32 config rom, the
|
|
|
|
* controller will load be32 values in to these registers
|
|
|
|
* during the atomic update, even on litte endian
|
|
|
|
* architectures. The workaround we use is to put a 0 in the
|
|
|
|
* header quadlet; 0 is endian agnostic and means that the
|
|
|
|
* config rom isn't ready yet. In the bus reset tasklet we
|
|
|
|
* then set up the real values for the two registers.
|
|
|
|
*
|
|
|
|
* We use ohci->lock to avoid racing with the code that sets
|
2011-07-26 00:16:24 +04:00
|
|
|
* ohci->next_config_rom to NULL (see bus_reset_work).
|
2006-12-20 03:58:35 +03:00
|
|
|
*/
|
|
|
|
|
|
|
|
next_config_rom =
|
|
|
|
dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
|
|
|
|
&next_config_rom_bus, GFP_KERNEL);
|
|
|
|
if (next_config_rom == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2012-04-09 23:40:33 +04:00
|
|
|
spin_lock_irq(&ohci->lock);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2011-05-02 21:33:42 +04:00
|
|
|
/*
|
|
|
|
* If there is not an already pending config_rom update,
|
|
|
|
* push our new allocation into the ohci->next_config_rom
|
|
|
|
* and then mark the local variable as null so that we
|
|
|
|
* won't deallocate the new buffer.
|
|
|
|
*
|
|
|
|
* OTOH, if there is a pending config_rom update, just
|
|
|
|
* use that buffer with the new config_rom data, and
|
|
|
|
* let this routine free the unused DMA allocation.
|
|
|
|
*/
|
|
|
|
|
2006-12-20 03:58:35 +03:00
|
|
|
if (ohci->next_config_rom == NULL) {
|
|
|
|
ohci->next_config_rom = next_config_rom;
|
|
|
|
ohci->next_config_rom_bus = next_config_rom_bus;
|
2011-05-02 21:33:42 +04:00
|
|
|
next_config_rom = NULL;
|
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2011-05-02 21:33:42 +04:00
|
|
|
copy_config_rom(ohci->next_config_rom, config_rom, length);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2011-05-02 21:33:42 +04:00
|
|
|
ohci->next_header = config_rom[0];
|
|
|
|
ohci->next_config_rom[0] = 0;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2011-05-02 21:33:42 +04:00
|
|
|
reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2012-04-09 23:40:33 +04:00
|
|
|
spin_unlock_irq(&ohci->lock);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2011-05-02 21:33:42 +04:00
|
|
|
/* If we didn't use the DMA allocation, delete it. */
|
|
|
|
if (next_config_rom != NULL)
|
|
|
|
dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
|
|
|
|
next_config_rom, next_config_rom_bus);
|
|
|
|
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
|
|
|
* Now initiate a bus reset to have the changes take
|
2006-12-20 03:58:35 +03:00
|
|
|
* effect. We clean up the old config rom memory and DMA
|
|
|
|
* mappings in the bus reset tasklet, since the OHCI
|
|
|
|
* controller could need to access it before the bus reset
|
2007-05-08 04:33:32 +04:00
|
|
|
* takes effect.
|
|
|
|
*/
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2011-05-02 21:33:42 +04:00
|
|
|
fw_schedule_bus_reset(&ohci->card, true, true);
|
|
|
|
|
|
|
|
return 0;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
|
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = fw_ohci(card);
|
|
|
|
|
|
|
|
at_context_transmit(&ohci->at_request_ctx, packet);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
|
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = fw_ohci(card);
|
|
|
|
|
|
|
|
at_context_transmit(&ohci->at_response_ctx, packet);
|
|
|
|
}
|
|
|
|
|
2007-02-06 22:49:32 +03:00
|
|
|
static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
|
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = fw_ohci(card);
|
2007-03-07 20:12:49 +03:00
|
|
|
struct context *ctx = &ohci->at_request_ctx;
|
|
|
|
struct driver_data *driver_data = packet->driver_data;
|
2008-12-14 23:45:45 +03:00
|
|
|
int ret = -ENOENT;
|
2007-02-06 22:49:32 +03:00
|
|
|
|
2021-03-09 11:42:16 +03:00
|
|
|
tasklet_disable_in_atomic(&ctx->tasklet);
|
2007-02-06 22:49:32 +03:00
|
|
|
|
2007-03-07 20:12:49 +03:00
|
|
|
if (packet->ack != 0)
|
|
|
|
goto out;
|
2007-02-06 22:49:32 +03:00
|
|
|
|
2009-10-14 22:40:10 +04:00
|
|
|
if (packet->payload_mapped)
|
2008-12-10 02:20:38 +03:00
|
|
|
dma_unmap_single(ohci->card.device, packet->payload_bus,
|
|
|
|
packet->payload_length, DMA_TO_DEVICE);
|
|
|
|
|
2011-12-21 00:32:46 +04:00
|
|
|
log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
|
2007-03-07 20:12:49 +03:00
|
|
|
driver_data->packet = NULL;
|
|
|
|
packet->ack = RCODE_CANCELLED;
|
|
|
|
packet->callback(packet, &ohci->card, packet->ack);
|
2008-12-14 23:45:45 +03:00
|
|
|
ret = 0;
|
2007-03-07 20:12:49 +03:00
|
|
|
out:
|
|
|
|
tasklet_enable(&ctx->tasklet);
|
2007-02-06 22:49:32 +03:00
|
|
|
|
2008-12-14 23:45:45 +03:00
|
|
|
return ret;
|
2007-02-06 22:49:32 +03:00
|
|
|
}
|
|
|
|
|
2008-12-14 23:47:04 +03:00
|
|
|
static int ohci_enable_phys_dma(struct fw_card *card,
|
|
|
|
int node_id, int generation)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = fw_ohci(card);
|
|
|
|
unsigned long flags;
|
2008-12-14 23:45:45 +03:00
|
|
|
int n, ret = 0;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2013-12-22 14:34:22 +04:00
|
|
|
if (param_remote_dma)
|
|
|
|
return 0;
|
|
|
|
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
|
|
|
* FIXME: Make sure this bitmask is cleared when we clear the busReset
|
|
|
|
* interrupt bit. Clear physReqResourceAllBuses on bus reset.
|
|
|
|
*/
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
spin_lock_irqsave(&ohci->lock, flags);
|
|
|
|
|
|
|
|
if (ohci->generation != generation) {
|
2008-12-14 23:45:45 +03:00
|
|
|
ret = -ESTALE;
|
2006-12-20 03:58:35 +03:00
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
|
|
|
* Note, if the node ID contains a non-local bus ID, physical DMA is
|
|
|
|
* enabled for _all_ nodes on remote buses.
|
|
|
|
*/
|
2007-01-23 23:11:43 +03:00
|
|
|
|
|
|
|
n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
|
|
|
|
if (n < 32)
|
|
|
|
reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
|
|
|
|
else
|
|
|
|
reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
|
|
|
|
|
2006-12-20 03:58:35 +03:00
|
|
|
flush_writes(ohci);
|
|
|
|
out:
|
2007-01-21 22:46:45 +03:00
|
|
|
spin_unlock_irqrestore(&ohci->lock, flags);
|
2008-12-14 23:45:45 +03:00
|
|
|
|
|
|
|
return ret;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
2007-03-04 16:45:18 +03:00
|
|
|
|
2010-06-12 22:35:52 +04:00
|
|
|
static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
|
2010-01-20 11:58:02 +03:00
|
|
|
{
|
2010-06-10 10:24:35 +04:00
|
|
|
struct fw_ohci *ohci = fw_ohci(card);
|
2010-06-10 10:33:07 +04:00
|
|
|
unsigned long flags;
|
|
|
|
u32 value;
|
2010-06-10 10:24:35 +04:00
|
|
|
|
|
|
|
switch (csr_offset) {
|
2010-06-10 10:36:37 +04:00
|
|
|
case CSR_STATE_CLEAR:
|
|
|
|
case CSR_STATE_SET:
|
|
|
|
if (ohci->is_root &&
|
|
|
|
(reg_read(ohci, OHCI1394_LinkControlSet) &
|
|
|
|
OHCI1394_LinkControl_cycleMaster))
|
2010-06-12 22:34:50 +04:00
|
|
|
value = CSR_STATE_BIT_CMSTR;
|
2010-06-10 10:36:37 +04:00
|
|
|
else
|
2010-06-12 22:34:50 +04:00
|
|
|
value = 0;
|
|
|
|
if (ohci->csr_state_setclear_abdicate)
|
|
|
|
value |= CSR_STATE_BIT_ABDICATE;
|
2010-01-20 11:58:02 +03:00
|
|
|
|
2010-06-12 22:34:50 +04:00
|
|
|
return value;
|
2010-02-21 00:24:43 +03:00
|
|
|
|
2010-06-10 10:25:19 +04:00
|
|
|
case CSR_NODE_IDS:
|
|
|
|
return reg_read(ohci, OHCI1394_NodeID) << 16;
|
|
|
|
|
2010-06-10 10:24:35 +04:00
|
|
|
case CSR_CYCLE_TIME:
|
|
|
|
return get_cycle_time(ohci);
|
|
|
|
|
2010-06-10 10:33:07 +04:00
|
|
|
case CSR_BUS_TIME:
|
|
|
|
/*
|
|
|
|
* We might be called just after the cycle timer has wrapped
|
|
|
|
* around but just before the cycle64Seconds handler, so we
|
|
|
|
* better check here, too, if the bus time needs to be updated.
|
|
|
|
*/
|
|
|
|
spin_lock_irqsave(&ohci->lock, flags);
|
|
|
|
value = update_bus_time(ohci);
|
|
|
|
spin_unlock_irqrestore(&ohci->lock, flags);
|
|
|
|
return value;
|
|
|
|
|
2010-06-10 10:34:13 +04:00
|
|
|
case CSR_BUSY_TIMEOUT:
|
|
|
|
value = reg_read(ohci, OHCI1394_ATRetries);
|
|
|
|
return (value >> 4) & 0x0ffff00f;
|
|
|
|
|
2010-06-10 10:35:06 +04:00
|
|
|
case CSR_PRIORITY_BUDGET:
|
|
|
|
return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
|
|
|
|
(ohci->pri_req_max << 8);
|
|
|
|
|
2010-06-10 10:24:35 +04:00
|
|
|
default:
|
|
|
|
WARN_ON(1);
|
|
|
|
return 0;
|
|
|
|
}
|
2010-01-20 11:58:02 +03:00
|
|
|
}
|
|
|
|
|
2010-06-12 22:35:52 +04:00
|
|
|
static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
|
2007-03-07 20:12:56 +03:00
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = fw_ohci(card);
|
2010-06-10 10:33:07 +04:00
|
|
|
unsigned long flags;
|
2007-03-07 20:12:56 +03:00
|
|
|
|
2010-06-10 10:25:19 +04:00
|
|
|
switch (csr_offset) {
|
2010-06-10 10:36:37 +04:00
|
|
|
case CSR_STATE_CLEAR:
|
|
|
|
if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
|
|
|
|
reg_write(ohci, OHCI1394_LinkControlClear,
|
|
|
|
OHCI1394_LinkControl_cycleMaster);
|
|
|
|
flush_writes(ohci);
|
|
|
|
}
|
2010-06-12 22:34:50 +04:00
|
|
|
if (value & CSR_STATE_BIT_ABDICATE)
|
|
|
|
ohci->csr_state_setclear_abdicate = false;
|
2010-06-10 10:36:37 +04:00
|
|
|
break;
|
2010-02-21 00:24:43 +03:00
|
|
|
|
2010-06-10 10:36:37 +04:00
|
|
|
case CSR_STATE_SET:
|
|
|
|
if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
|
|
|
|
reg_write(ohci, OHCI1394_LinkControlSet,
|
|
|
|
OHCI1394_LinkControl_cycleMaster);
|
|
|
|
flush_writes(ohci);
|
|
|
|
}
|
2010-06-12 22:34:50 +04:00
|
|
|
if (value & CSR_STATE_BIT_ABDICATE)
|
|
|
|
ohci->csr_state_setclear_abdicate = true;
|
2010-06-10 10:36:37 +04:00
|
|
|
break;
|
2007-03-07 20:12:56 +03:00
|
|
|
|
2010-06-10 10:25:19 +04:00
|
|
|
case CSR_NODE_IDS:
|
|
|
|
reg_write(ohci, OHCI1394_NodeID, value >> 16);
|
|
|
|
flush_writes(ohci);
|
|
|
|
break;
|
|
|
|
|
2010-06-10 10:26:48 +04:00
|
|
|
case CSR_CYCLE_TIME:
|
|
|
|
reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
|
|
|
|
reg_write(ohci, OHCI1394_IntEventSet,
|
|
|
|
OHCI1394_cycleInconsistent);
|
|
|
|
flush_writes(ohci);
|
|
|
|
break;
|
|
|
|
|
2010-06-10 10:33:07 +04:00
|
|
|
case CSR_BUS_TIME:
|
|
|
|
spin_lock_irqsave(&ohci->lock, flags);
|
2012-05-24 21:29:19 +04:00
|
|
|
ohci->bus_time = (update_bus_time(ohci) & 0x40) |
|
|
|
|
(value & ~0x7f);
|
2010-06-10 10:33:07 +04:00
|
|
|
spin_unlock_irqrestore(&ohci->lock, flags);
|
|
|
|
break;
|
|
|
|
|
2010-06-10 10:34:13 +04:00
|
|
|
case CSR_BUSY_TIMEOUT:
|
|
|
|
value = (value & 0xf) | ((value & 0xf) << 4) |
|
|
|
|
((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
|
|
|
|
reg_write(ohci, OHCI1394_ATRetries, value);
|
|
|
|
flush_writes(ohci);
|
|
|
|
break;
|
|
|
|
|
2010-06-10 10:35:06 +04:00
|
|
|
case CSR_PRIORITY_BUDGET:
|
|
|
|
reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
|
|
|
|
flush_writes(ohci);
|
|
|
|
break;
|
|
|
|
|
2010-06-10 10:25:19 +04:00
|
|
|
default:
|
|
|
|
WARN_ON(1);
|
|
|
|
break;
|
|
|
|
}
|
2007-03-07 20:12:56 +03:00
|
|
|
}
|
|
|
|
|
2012-03-18 22:04:43 +04:00
|
|
|
static void flush_iso_completions(struct iso_context *ctx)
|
2008-07-23 10:23:40 +04:00
|
|
|
{
|
2012-03-18 22:04:43 +04:00
|
|
|
ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
|
|
|
|
ctx->header_length, ctx->header,
|
|
|
|
ctx->base.callback_data);
|
|
|
|
ctx->header_length = 0;
|
|
|
|
}
|
2008-07-23 10:23:40 +04:00
|
|
|
|
2012-03-18 22:04:05 +04:00
|
|
|
static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
|
2008-07-23 10:23:40 +04:00
|
|
|
{
|
2012-03-18 22:04:05 +04:00
|
|
|
u32 *ctx_hdr;
|
2008-07-23 10:23:40 +04:00
|
|
|
|
2013-07-22 23:32:09 +04:00
|
|
|
if (ctx->header_length + ctx->base.header_size > PAGE_SIZE) {
|
|
|
|
if (ctx->base.drop_overflow_headers)
|
|
|
|
return;
|
2012-03-18 22:05:29 +04:00
|
|
|
flush_iso_completions(ctx);
|
2013-07-22 23:32:09 +04:00
|
|
|
}
|
2008-07-23 10:23:40 +04:00
|
|
|
|
2012-03-18 22:04:05 +04:00
|
|
|
ctx_hdr = ctx->header + ctx->header_length;
|
2012-03-18 22:04:43 +04:00
|
|
|
ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
|
2008-07-23 10:23:40 +04:00
|
|
|
|
|
|
|
/*
|
2012-03-18 22:01:39 +04:00
|
|
|
* The two iso header quadlets are byteswapped to little
|
|
|
|
* endian by the controller, but we want to present them
|
|
|
|
* as big endian for consistency with the bus endianness.
|
2008-07-23 10:23:40 +04:00
|
|
|
*/
|
|
|
|
if (ctx->base.header_size > 0)
|
2012-03-18 22:04:05 +04:00
|
|
|
ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
|
2008-07-23 10:23:40 +04:00
|
|
|
if (ctx->base.header_size > 4)
|
2012-03-18 22:04:05 +04:00
|
|
|
ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
|
2008-07-23 10:23:40 +04:00
|
|
|
if (ctx->base.header_size > 8)
|
2012-03-18 22:04:05 +04:00
|
|
|
memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
|
2008-07-23 10:23:40 +04:00
|
|
|
ctx->header_length += ctx->base.header_size;
|
|
|
|
}
|
|
|
|
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
static int handle_ir_packet_per_buffer(struct context *context,
|
|
|
|
struct descriptor *d,
|
|
|
|
struct descriptor *last)
|
|
|
|
{
|
|
|
|
struct iso_context *ctx =
|
|
|
|
container_of(context, struct iso_context, context);
|
2007-12-19 23:26:38 +03:00
|
|
|
struct descriptor *pd;
|
2011-10-16 01:12:23 +04:00
|
|
|
u32 buffer_dma;
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
|
2010-07-29 20:19:22 +04:00
|
|
|
for (pd = d; pd <= last; pd++)
|
2007-12-19 23:26:38 +03:00
|
|
|
if (pd->transfer_status)
|
|
|
|
break;
|
|
|
|
if (pd > last)
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
/* Descriptor(s) not done yet, stop iteration */
|
|
|
|
return 0;
|
|
|
|
|
2011-10-16 01:12:23 +04:00
|
|
|
while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
|
|
|
|
d++;
|
|
|
|
buffer_dma = le32_to_cpu(d->data_address);
|
|
|
|
dma_sync_single_range_for_cpu(context->ohci->card.device,
|
|
|
|
buffer_dma & PAGE_MASK,
|
|
|
|
buffer_dma & ~PAGE_MASK,
|
|
|
|
le16_to_cpu(d->req_count),
|
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
}
|
|
|
|
|
2012-03-18 22:04:43 +04:00
|
|
|
copy_iso_headers(ctx, (u32 *) (last + 1));
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
|
2012-03-18 22:04:43 +04:00
|
|
|
if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
|
|
|
|
flush_iso_completions(ctx);
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2010-07-29 20:19:22 +04:00
|
|
|
/* d == last because each descriptor block is only a single descriptor. */
|
|
|
|
static int handle_ir_buffer_fill(struct context *context,
|
|
|
|
struct descriptor *d,
|
|
|
|
struct descriptor *last)
|
|
|
|
{
|
|
|
|
struct iso_context *ctx =
|
|
|
|
container_of(context, struct iso_context, context);
|
2012-03-18 22:06:39 +04:00
|
|
|
unsigned int req_count, res_count, completed;
|
2011-10-16 01:12:23 +04:00
|
|
|
u32 buffer_dma;
|
2010-07-29 20:19:22 +04:00
|
|
|
|
2012-03-18 22:06:39 +04:00
|
|
|
req_count = le16_to_cpu(last->req_count);
|
locking/atomics: COCCINELLE/treewide: Convert trivial ACCESS_ONCE() patterns to READ_ONCE()/WRITE_ONCE()
Please do not apply this to mainline directly, instead please re-run the
coccinelle script shown below and apply its output.
For several reasons, it is desirable to use {READ,WRITE}_ONCE() in
preference to ACCESS_ONCE(), and new code is expected to use one of the
former. So far, there's been no reason to change most existing uses of
ACCESS_ONCE(), as these aren't harmful, and changing them results in
churn.
However, for some features, the read/write distinction is critical to
correct operation. To distinguish these cases, separate read/write
accessors must be used. This patch migrates (most) remaining
ACCESS_ONCE() instances to {READ,WRITE}_ONCE(), using the following
coccinelle script:
----
// Convert trivial ACCESS_ONCE() uses to equivalent READ_ONCE() and
// WRITE_ONCE()
// $ make coccicheck COCCI=/home/mark/once.cocci SPFLAGS="--include-headers" MODE=patch
virtual patch
@ depends on patch @
expression E1, E2;
@@
- ACCESS_ONCE(E1) = E2
+ WRITE_ONCE(E1, E2)
@ depends on patch @
expression E;
@@
- ACCESS_ONCE(E)
+ READ_ONCE(E)
----
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: davem@davemloft.net
Cc: linux-arch@vger.kernel.org
Cc: mpe@ellerman.id.au
Cc: shuah@kernel.org
Cc: snitzer@redhat.com
Cc: thor.thayer@linux.intel.com
Cc: tj@kernel.org
Cc: viro@zeniv.linux.org.uk
Cc: will.deacon@arm.com
Link: http://lkml.kernel.org/r/1508792849-3115-19-git-send-email-paulmck@linux.vnet.ibm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2017-10-24 00:07:29 +03:00
|
|
|
res_count = le16_to_cpu(READ_ONCE(last->res_count));
|
2012-03-18 22:06:39 +04:00
|
|
|
completed = req_count - res_count;
|
|
|
|
buffer_dma = le32_to_cpu(last->data_address);
|
|
|
|
|
|
|
|
if (completed > 0) {
|
|
|
|
ctx->mc_buffer_bus = buffer_dma;
|
|
|
|
ctx->mc_completed = completed;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (res_count != 0)
|
2010-07-29 20:19:22 +04:00
|
|
|
/* Descriptor(s) not done yet, stop iteration */
|
|
|
|
return 0;
|
|
|
|
|
2011-10-16 01:12:23 +04:00
|
|
|
dma_sync_single_range_for_cpu(context->ohci->card.device,
|
|
|
|
buffer_dma & PAGE_MASK,
|
|
|
|
buffer_dma & ~PAGE_MASK,
|
2012-03-18 22:06:39 +04:00
|
|
|
completed, DMA_FROM_DEVICE);
|
2011-10-16 01:12:23 +04:00
|
|
|
|
2012-03-18 22:06:39 +04:00
|
|
|
if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS)) {
|
2010-07-29 20:19:22 +04:00
|
|
|
ctx->base.callback.mc(&ctx->base,
|
2012-03-18 22:06:39 +04:00
|
|
|
buffer_dma + completed,
|
2010-07-29 20:19:22 +04:00
|
|
|
ctx->base.callback_data);
|
2012-03-18 22:06:39 +04:00
|
|
|
ctx->mc_completed = 0;
|
|
|
|
}
|
2010-07-29 20:19:22 +04:00
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2012-03-18 22:06:39 +04:00
|
|
|
static void flush_ir_buffer_fill(struct iso_context *ctx)
|
|
|
|
{
|
|
|
|
dma_sync_single_range_for_cpu(ctx->context.ohci->card.device,
|
|
|
|
ctx->mc_buffer_bus & PAGE_MASK,
|
|
|
|
ctx->mc_buffer_bus & ~PAGE_MASK,
|
|
|
|
ctx->mc_completed, DMA_FROM_DEVICE);
|
|
|
|
|
|
|
|
ctx->base.callback.mc(&ctx->base,
|
|
|
|
ctx->mc_buffer_bus + ctx->mc_completed,
|
|
|
|
ctx->base.callback_data);
|
|
|
|
ctx->mc_completed = 0;
|
|
|
|
}
|
|
|
|
|
2011-10-16 01:12:23 +04:00
|
|
|
static inline void sync_it_packet_for_cpu(struct context *context,
|
|
|
|
struct descriptor *pd)
|
|
|
|
{
|
|
|
|
__le16 control;
|
|
|
|
u32 buffer_dma;
|
|
|
|
|
|
|
|
/* only packets beginning with OUTPUT_MORE* have data buffers */
|
|
|
|
if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
|
|
|
|
pd += 2;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
|
|
|
|
* data buffer is in the context program's coherent page and must not
|
|
|
|
* be synced.
|
|
|
|
*/
|
|
|
|
if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
|
|
|
|
(context->current_bus & PAGE_MASK)) {
|
|
|
|
if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
|
|
|
|
return;
|
|
|
|
pd++;
|
|
|
|
}
|
|
|
|
|
|
|
|
do {
|
|
|
|
buffer_dma = le32_to_cpu(pd->data_address);
|
|
|
|
dma_sync_single_range_for_cpu(context->ohci->card.device,
|
|
|
|
buffer_dma & PAGE_MASK,
|
|
|
|
buffer_dma & ~PAGE_MASK,
|
|
|
|
le16_to_cpu(pd->req_count),
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
control = pd->control;
|
|
|
|
pd++;
|
|
|
|
} while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
|
|
|
|
}
|
|
|
|
|
2007-02-17 01:34:39 +03:00
|
|
|
static int handle_it_packet(struct context *context,
|
|
|
|
struct descriptor *d,
|
|
|
|
struct descriptor *last)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
2007-02-17 01:34:39 +03:00
|
|
|
struct iso_context *ctx =
|
|
|
|
container_of(context, struct iso_context, context);
|
2009-11-21 02:05:56 +03:00
|
|
|
struct descriptor *pd;
|
2012-03-18 22:04:05 +04:00
|
|
|
__be32 *ctx_hdr;
|
2007-03-04 16:45:18 +03:00
|
|
|
|
2009-11-21 02:05:56 +03:00
|
|
|
for (pd = d; pd <= last; pd++)
|
|
|
|
if (pd->transfer_status)
|
|
|
|
break;
|
|
|
|
if (pd > last)
|
|
|
|
/* Descriptor(s) not done yet, stop iteration */
|
2007-02-17 01:34:39 +03:00
|
|
|
return 0;
|
|
|
|
|
2011-10-16 01:12:23 +04:00
|
|
|
sync_it_packet_for_cpu(context, d);
|
|
|
|
|
2013-07-22 23:32:09 +04:00
|
|
|
if (ctx->header_length + 4 > PAGE_SIZE) {
|
|
|
|
if (ctx->base.drop_overflow_headers)
|
|
|
|
return 1;
|
2012-03-18 22:05:29 +04:00
|
|
|
flush_iso_completions(ctx);
|
2013-07-22 23:32:09 +04:00
|
|
|
}
|
2012-03-18 22:04:43 +04:00
|
|
|
|
2012-03-18 22:05:29 +04:00
|
|
|
ctx_hdr = ctx->header + ctx->header_length;
|
2012-03-18 22:04:43 +04:00
|
|
|
ctx->last_timestamp = le16_to_cpu(last->res_count);
|
2012-03-18 22:05:29 +04:00
|
|
|
/* Present this value as big-endian to match the receive code */
|
|
|
|
*ctx_hdr = cpu_to_be32((le16_to_cpu(pd->transfer_status) << 16) |
|
|
|
|
le16_to_cpu(pd->res_count));
|
|
|
|
ctx->header_length += 4;
|
|
|
|
|
2012-03-18 22:04:43 +04:00
|
|
|
if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
|
|
|
|
flush_iso_completions(ctx);
|
|
|
|
|
2007-02-17 01:34:39 +03:00
|
|
|
return 1;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2010-07-29 20:19:22 +04:00
|
|
|
static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
|
|
|
|
{
|
|
|
|
u32 hi = channels >> 32, lo = channels;
|
|
|
|
|
|
|
|
reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
|
|
|
|
reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
|
|
|
|
reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
|
|
|
|
reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
|
|
|
|
ohci->mc_channels = channels;
|
|
|
|
}
|
|
|
|
|
2008-12-14 23:47:04 +03:00
|
|
|
static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
|
2008-12-21 18:39:46 +03:00
|
|
|
int type, int channel, size_t header_size)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = fw_ohci(card);
|
treewide: Remove uninitialized_var() usage
Using uninitialized_var() is dangerous as it papers over real bugs[1]
(or can in the future), and suppresses unrelated compiler warnings
(e.g. "unused variable"). If the compiler thinks it is uninitialized,
either simply initialize the variable or make compiler changes.
In preparation for removing[2] the[3] macro[4], remove all remaining
needless uses with the following script:
git grep '\buninitialized_var\b' | cut -d: -f1 | sort -u | \
xargs perl -pi -e \
's/\buninitialized_var\(([^\)]+)\)/\1/g;
s:\s*/\* (GCC be quiet|to make compiler happy) \*/$::g;'
drivers/video/fbdev/riva/riva_hw.c was manually tweaked to avoid
pathological white-space.
No outstanding warnings were found building allmodconfig with GCC 9.3.0
for x86_64, i386, arm64, arm, powerpc, powerpc64le, s390x, mips, sparc64,
alpha, and m68k.
[1] https://lore.kernel.org/lkml/20200603174714.192027-1-glider@google.com/
[2] https://lore.kernel.org/lkml/CA+55aFw+Vbj0i=1TGqCR5vQkCzWJ0QxK6CernOU6eedsudAixw@mail.gmail.com/
[3] https://lore.kernel.org/lkml/CA+55aFwgbgqhbp1fkxvRKEpzyR5J8n1vKT1VZdz9knmPuXhOeg@mail.gmail.com/
[4] https://lore.kernel.org/lkml/CA+55aFz2500WfbKXAx8s67wrm9=yVJu65TpLgN_ybYNv0VEOKA@mail.gmail.com/
Reviewed-by: Leon Romanovsky <leonro@mellanox.com> # drivers/infiniband and mlx4/mlx5
Acked-by: Jason Gunthorpe <jgg@mellanox.com> # IB
Acked-by: Kalle Valo <kvalo@codeaurora.org> # wireless drivers
Reviewed-by: Chao Yu <yuchao0@huawei.com> # erofs
Signed-off-by: Kees Cook <keescook@chromium.org>
2020-06-03 23:09:38 +03:00
|
|
|
struct iso_context *ctx;
|
|
|
|
descriptor_callback_t callback;
|
|
|
|
u64 *channels;
|
|
|
|
u32 *mask, regs;
|
2010-07-29 20:19:22 +04:00
|
|
|
int index, ret = -EBUSY;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2012-04-09 23:40:33 +04:00
|
|
|
spin_lock_irq(&ohci->lock);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2010-07-29 20:19:22 +04:00
|
|
|
switch (type) {
|
|
|
|
case FW_ISO_CONTEXT_TRANSMIT:
|
|
|
|
mask = &ohci->it_context_mask;
|
2007-02-17 01:34:39 +03:00
|
|
|
callback = handle_it_packet;
|
2010-07-29 20:19:22 +04:00
|
|
|
index = ffs(*mask) - 1;
|
|
|
|
if (index >= 0) {
|
|
|
|
*mask &= ~(1 << index);
|
|
|
|
regs = OHCI1394_IsoXmitContextBase(index);
|
|
|
|
ctx = &ohci->it_context_list[index];
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case FW_ISO_CONTEXT_RECEIVE:
|
2008-12-21 18:39:46 +03:00
|
|
|
channels = &ohci->ir_context_channels;
|
2010-07-29 20:19:22 +04:00
|
|
|
mask = &ohci->ir_context_mask;
|
2010-02-21 19:57:05 +03:00
|
|
|
callback = handle_ir_packet_per_buffer;
|
2010-07-29 20:19:22 +04:00
|
|
|
index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
|
|
|
|
if (index >= 0) {
|
|
|
|
*channels &= ~(1ULL << channel);
|
|
|
|
*mask &= ~(1 << index);
|
|
|
|
regs = OHCI1394_IsoRcvContextBase(index);
|
|
|
|
ctx = &ohci->ir_context_list[index];
|
|
|
|
}
|
|
|
|
break;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2010-07-29 20:19:22 +04:00
|
|
|
case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
|
|
|
|
mask = &ohci->ir_context_mask;
|
|
|
|
callback = handle_ir_buffer_fill;
|
|
|
|
index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
|
|
|
|
if (index >= 0) {
|
|
|
|
ohci->mc_allocated = true;
|
|
|
|
*mask &= ~(1 << index);
|
|
|
|
regs = OHCI1394_IsoRcvContextBase(index);
|
|
|
|
ctx = &ohci->ir_context_list[index];
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
index = -1;
|
|
|
|
ret = -ENOSYS;
|
2008-12-21 18:39:46 +03:00
|
|
|
}
|
2010-07-29 20:19:22 +04:00
|
|
|
|
2012-04-09 23:40:33 +04:00
|
|
|
spin_unlock_irq(&ohci->lock);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
if (index < 0)
|
2010-07-29 20:19:22 +04:00
|
|
|
return ERR_PTR(ret);
|
2007-03-04 16:45:18 +03:00
|
|
|
|
2007-05-10 03:23:14 +04:00
|
|
|
memset(ctx, 0, sizeof(*ctx));
|
2007-02-17 01:34:44 +03:00
|
|
|
ctx->header_length = 0;
|
|
|
|
ctx->header = (void *) __get_free_page(GFP_KERNEL);
|
2010-07-29 20:19:22 +04:00
|
|
|
if (ctx->header == NULL) {
|
|
|
|
ret = -ENOMEM;
|
2007-02-17 01:34:44 +03:00
|
|
|
goto out;
|
2010-07-29 20:19:22 +04:00
|
|
|
}
|
2008-12-14 23:45:45 +03:00
|
|
|
ret = context_init(&ctx->context, ohci, regs, callback);
|
|
|
|
if (ret < 0)
|
2007-02-17 01:34:44 +03:00
|
|
|
goto out_with_header;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2012-03-18 22:06:39 +04:00
|
|
|
if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL) {
|
2010-07-29 20:19:22 +04:00
|
|
|
set_multichannel_mask(ohci, 0);
|
2012-03-18 22:06:39 +04:00
|
|
|
ctx->mc_completed = 0;
|
|
|
|
}
|
2010-07-29 20:19:22 +04:00
|
|
|
|
2006-12-20 03:58:35 +03:00
|
|
|
return &ctx->base;
|
2007-02-17 01:34:44 +03:00
|
|
|
|
|
|
|
out_with_header:
|
|
|
|
free_page((unsigned long)ctx->header);
|
|
|
|
out:
|
2012-04-09 23:40:33 +04:00
|
|
|
spin_lock_irq(&ohci->lock);
|
2010-07-29 20:19:22 +04:00
|
|
|
|
|
|
|
switch (type) {
|
|
|
|
case FW_ISO_CONTEXT_RECEIVE:
|
|
|
|
*channels |= 1ULL << channel;
|
|
|
|
break;
|
|
|
|
|
|
|
|
case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
|
|
|
|
ohci->mc_allocated = false;
|
|
|
|
break;
|
|
|
|
}
|
2007-02-17 01:34:44 +03:00
|
|
|
*mask |= 1 << index;
|
2010-07-29 20:19:22 +04:00
|
|
|
|
2012-04-09 23:40:33 +04:00
|
|
|
spin_unlock_irq(&ohci->lock);
|
2007-02-17 01:34:44 +03:00
|
|
|
|
2008-12-14 23:45:45 +03:00
|
|
|
return ERR_PTR(ret);
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2007-03-15 00:34:54 +03:00
|
|
|
static int ohci_start_iso(struct fw_iso_context *base,
|
|
|
|
s32 cycle, u32 sync, u32 tags)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
2007-03-04 16:45:18 +03:00
|
|
|
struct iso_context *ctx = container_of(base, struct iso_context, base);
|
2007-02-17 01:34:39 +03:00
|
|
|
struct fw_ohci *ohci = ctx->context.ohci;
|
2010-07-29 20:19:22 +04:00
|
|
|
u32 control = IR_CONTEXT_ISOCH_HEADER, match;
|
2006-12-20 03:58:35 +03:00
|
|
|
int index;
|
|
|
|
|
2011-02-23 11:27:40 +03:00
|
|
|
/* the controller cannot start without any queued packets */
|
|
|
|
if (ctx->context.last->branch_address == 0)
|
|
|
|
return -ENODATA;
|
|
|
|
|
2010-07-29 20:19:22 +04:00
|
|
|
switch (ctx->base.type) {
|
|
|
|
case FW_ISO_CONTEXT_TRANSMIT:
|
2007-02-17 01:34:40 +03:00
|
|
|
index = ctx - ohci->it_context_list;
|
2007-03-28 22:26:10 +04:00
|
|
|
match = 0;
|
|
|
|
if (cycle >= 0)
|
|
|
|
match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
|
2007-02-17 01:34:40 +03:00
|
|
|
(cycle & 0x7fff) << 16;
|
2007-02-17 01:34:50 +03:00
|
|
|
|
2007-02-17 01:34:40 +03:00
|
|
|
reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
|
|
|
|
reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
|
2007-03-28 22:26:10 +04:00
|
|
|
context_run(&ctx->context, match);
|
2010-07-29 20:19:22 +04:00
|
|
|
break;
|
|
|
|
|
|
|
|
case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
|
|
|
|
control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
|
2020-08-24 01:36:59 +03:00
|
|
|
fallthrough;
|
2010-07-29 20:19:22 +04:00
|
|
|
case FW_ISO_CONTEXT_RECEIVE:
|
2007-02-17 01:34:40 +03:00
|
|
|
index = ctx - ohci->ir_context_list;
|
2007-03-28 22:26:10 +04:00
|
|
|
match = (tags << 28) | (sync << 8) | ctx->base.channel;
|
|
|
|
if (cycle >= 0) {
|
|
|
|
match |= (cycle & 0x07fff) << 12;
|
|
|
|
control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
|
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-02-17 01:34:40 +03:00
|
|
|
reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
|
|
|
|
reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
|
2007-05-08 04:33:35 +04:00
|
|
|
reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
|
2007-03-28 22:26:10 +04:00
|
|
|
context_run(&ctx->context, control);
|
2010-11-29 05:09:50 +03:00
|
|
|
|
|
|
|
ctx->sync = sync;
|
|
|
|
ctx->tags = tags;
|
|
|
|
|
2010-07-29 20:19:22 +04:00
|
|
|
break;
|
2007-02-17 01:34:40 +03:00
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-02-17 01:34:42 +03:00
|
|
|
static int ohci_stop_iso(struct fw_iso_context *base)
|
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = fw_ohci(base->card);
|
2007-03-04 16:45:18 +03:00
|
|
|
struct iso_context *ctx = container_of(base, struct iso_context, base);
|
2007-02-17 01:34:42 +03:00
|
|
|
int index;
|
|
|
|
|
2010-07-29 20:19:22 +04:00
|
|
|
switch (ctx->base.type) {
|
|
|
|
case FW_ISO_CONTEXT_TRANSMIT:
|
2007-02-17 01:34:42 +03:00
|
|
|
index = ctx - ohci->it_context_list;
|
|
|
|
reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
|
2010-07-29 20:19:22 +04:00
|
|
|
break;
|
|
|
|
|
|
|
|
case FW_ISO_CONTEXT_RECEIVE:
|
|
|
|
case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
|
2007-02-17 01:34:42 +03:00
|
|
|
index = ctx - ohci->ir_context_list;
|
|
|
|
reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
|
2010-07-29 20:19:22 +04:00
|
|
|
break;
|
2007-02-17 01:34:42 +03:00
|
|
|
}
|
|
|
|
flush_writes(ohci);
|
|
|
|
context_stop(&ctx->context);
|
2011-02-16 12:32:11 +03:00
|
|
|
tasklet_kill(&ctx->context.tasklet);
|
2007-02-17 01:34:42 +03:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2006-12-20 03:58:35 +03:00
|
|
|
static void ohci_free_iso_context(struct fw_iso_context *base)
|
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = fw_ohci(base->card);
|
2007-03-04 16:45:18 +03:00
|
|
|
struct iso_context *ctx = container_of(base, struct iso_context, base);
|
2006-12-20 03:58:35 +03:00
|
|
|
unsigned long flags;
|
|
|
|
int index;
|
|
|
|
|
2007-02-17 01:34:42 +03:00
|
|
|
ohci_stop_iso(base);
|
|
|
|
context_release(&ctx->context);
|
2007-02-17 01:34:44 +03:00
|
|
|
free_page((unsigned long)ctx->header);
|
2007-02-17 01:34:42 +03:00
|
|
|
|
2006-12-20 03:58:35 +03:00
|
|
|
spin_lock_irqsave(&ohci->lock, flags);
|
|
|
|
|
2010-07-29 20:19:22 +04:00
|
|
|
switch (base->type) {
|
|
|
|
case FW_ISO_CONTEXT_TRANSMIT:
|
2006-12-20 03:58:35 +03:00
|
|
|
index = ctx - ohci->it_context_list;
|
|
|
|
ohci->it_context_mask |= 1 << index;
|
2010-07-29 20:19:22 +04:00
|
|
|
break;
|
|
|
|
|
|
|
|
case FW_ISO_CONTEXT_RECEIVE:
|
2006-12-20 03:58:35 +03:00
|
|
|
index = ctx - ohci->ir_context_list;
|
|
|
|
ohci->ir_context_mask |= 1 << index;
|
2008-12-21 18:39:46 +03:00
|
|
|
ohci->ir_context_channels |= 1ULL << base->channel;
|
2010-07-29 20:19:22 +04:00
|
|
|
break;
|
|
|
|
|
|
|
|
case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
|
|
|
|
index = ctx - ohci->ir_context_list;
|
|
|
|
ohci->ir_context_mask |= 1 << index;
|
|
|
|
ohci->ir_context_channels |= ohci->mc_channels;
|
|
|
|
ohci->mc_channels = 0;
|
|
|
|
ohci->mc_allocated = false;
|
|
|
|
break;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&ohci->lock, flags);
|
|
|
|
}
|
|
|
|
|
2010-07-29 20:19:22 +04:00
|
|
|
static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
|
|
|
|
{
|
|
|
|
struct fw_ohci *ohci = fw_ohci(base->card);
|
|
|
|
unsigned long flags;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
switch (base->type) {
|
|
|
|
case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ohci->lock, flags);
|
|
|
|
|
|
|
|
/* Don't allow multichannel to grab other contexts' channels. */
|
|
|
|
if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
|
|
|
|
*channels = ohci->ir_context_channels;
|
|
|
|
ret = -EBUSY;
|
|
|
|
} else {
|
|
|
|
set_multichannel_mask(ohci, *channels);
|
|
|
|
ret = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&ohci->lock, flags);
|
|
|
|
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ret = -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2010-11-29 05:09:50 +03:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static void ohci_resume_iso_dma(struct fw_ohci *ohci)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
struct iso_context *ctx;
|
|
|
|
|
|
|
|
for (i = 0 ; i < ohci->n_ir ; i++) {
|
|
|
|
ctx = &ohci->ir_context_list[i];
|
2011-01-01 17:17:05 +03:00
|
|
|
if (ctx->context.running)
|
2010-11-29 05:09:50 +03:00
|
|
|
ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0 ; i < ohci->n_it ; i++) {
|
|
|
|
ctx = &ohci->it_context_list[i];
|
2011-01-01 17:17:05 +03:00
|
|
|
if (ctx->context.running)
|
2010-11-29 05:09:50 +03:00
|
|
|
ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-07-29 20:19:22 +04:00
|
|
|
static int queue_iso_transmit(struct iso_context *ctx,
|
|
|
|
struct fw_iso_packet *packet,
|
|
|
|
struct fw_iso_buffer *buffer,
|
|
|
|
unsigned long payload)
|
2006-12-20 03:58:35 +03:00
|
|
|
{
|
2007-02-17 01:34:39 +03:00
|
|
|
struct descriptor *d, *last, *pd;
|
2006-12-20 03:58:35 +03:00
|
|
|
struct fw_iso_packet *p;
|
|
|
|
__le32 *header;
|
2007-02-17 01:34:38 +03:00
|
|
|
dma_addr_t d_bus, page_bus;
|
2006-12-20 03:58:35 +03:00
|
|
|
u32 z, header_z, payload_z, irq;
|
|
|
|
u32 payload_index, payload_end_index, next_page_index;
|
2007-02-17 01:34:39 +03:00
|
|
|
int page, end_page, i, length, offset;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
p = packet;
|
2007-02-17 01:34:38 +03:00
|
|
|
payload_index = payload;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
if (p->skip)
|
|
|
|
z = 1;
|
|
|
|
else
|
|
|
|
z = 2;
|
|
|
|
if (p->header_length > 0)
|
|
|
|
z++;
|
|
|
|
|
|
|
|
/* Determine the first page the payload isn't contained in. */
|
|
|
|
end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
|
|
|
|
if (p->payload_length > 0)
|
|
|
|
payload_z = end_page - (payload_index >> PAGE_SHIFT);
|
|
|
|
else
|
|
|
|
payload_z = 0;
|
|
|
|
|
|
|
|
z += payload_z;
|
|
|
|
|
|
|
|
/* Get header size in number of descriptors. */
|
2007-05-10 03:23:14 +04:00
|
|
|
header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-02-17 01:34:39 +03:00
|
|
|
d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
|
|
|
|
if (d == NULL)
|
|
|
|
return -ENOMEM;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
if (!p->skip) {
|
2007-05-08 04:33:35 +04:00
|
|
|
d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
|
2006-12-20 03:58:35 +03:00
|
|
|
d[0].req_count = cpu_to_le16(8);
|
2010-02-08 10:30:03 +03:00
|
|
|
/*
|
|
|
|
* Link the skip address to this descriptor itself. This causes
|
|
|
|
* a context to skip a cycle whenever lost cycles or FIFO
|
|
|
|
* overruns occur, without dropping the data. The application
|
|
|
|
* should then decide whether this is an error condition or not.
|
|
|
|
* FIXME: Make the context's cycle-lost behaviour configurable?
|
|
|
|
*/
|
|
|
|
d[0].branch_address = cpu_to_le32(d_bus | z);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
header = (__le32 *) &d[1];
|
2007-05-08 04:33:35 +04:00
|
|
|
header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
|
|
|
|
IT_HEADER_TAG(p->tag) |
|
|
|
|
IT_HEADER_TCODE(TCODE_STREAM_DATA) |
|
|
|
|
IT_HEADER_CHANNEL(ctx->base.channel) |
|
|
|
|
IT_HEADER_SPEED(ctx->base.speed));
|
2006-12-20 03:58:35 +03:00
|
|
|
header[1] =
|
2007-05-08 04:33:35 +04:00
|
|
|
cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
|
2006-12-20 03:58:35 +03:00
|
|
|
p->payload_length));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (p->header_length > 0) {
|
|
|
|
d[2].req_count = cpu_to_le16(p->header_length);
|
2007-05-10 03:23:14 +04:00
|
|
|
d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
|
2006-12-20 03:58:35 +03:00
|
|
|
memcpy(&d[z], p->header, p->header_length);
|
|
|
|
}
|
|
|
|
|
|
|
|
pd = d + z - payload_z;
|
|
|
|
payload_end_index = payload_index + p->payload_length;
|
|
|
|
for (i = 0; i < payload_z; i++) {
|
|
|
|
page = payload_index >> PAGE_SHIFT;
|
|
|
|
offset = payload_index & ~PAGE_MASK;
|
|
|
|
next_page_index = (page + 1) << PAGE_SHIFT;
|
|
|
|
length =
|
|
|
|
min(next_page_index, payload_end_index) - payload_index;
|
|
|
|
pd[i].req_count = cpu_to_le16(length);
|
2007-02-17 01:34:38 +03:00
|
|
|
|
|
|
|
page_bus = page_private(buffer->pages[page]);
|
|
|
|
pd[i].data_address = cpu_to_le32(page_bus + offset);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2011-10-16 01:12:23 +04:00
|
|
|
dma_sync_single_range_for_device(ctx->context.ohci->card.device,
|
|
|
|
page_bus, offset, length,
|
|
|
|
DMA_TO_DEVICE);
|
|
|
|
|
2006-12-20 03:58:35 +03:00
|
|
|
payload_index += length;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (p->interrupt)
|
2007-05-08 04:33:35 +04:00
|
|
|
irq = DESCRIPTOR_IRQ_ALWAYS;
|
2006-12-20 03:58:35 +03:00
|
|
|
else
|
2007-05-08 04:33:35 +04:00
|
|
|
irq = DESCRIPTOR_NO_IRQ;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-02-17 01:34:39 +03:00
|
|
|
last = z == 2 ? d : d + z - 1;
|
2007-05-08 04:33:35 +04:00
|
|
|
last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
|
|
|
|
DESCRIPTOR_STATUS |
|
|
|
|
DESCRIPTOR_BRANCH_ALWAYS |
|
2007-02-17 01:34:35 +03:00
|
|
|
irq);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2007-02-17 01:34:39 +03:00
|
|
|
context_append(&ctx->context, d, z, header_z);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2007-03-04 16:45:18 +03:00
|
|
|
|
2010-07-29 20:19:22 +04:00
|
|
|
static int queue_iso_packet_per_buffer(struct iso_context *ctx,
|
|
|
|
struct fw_iso_packet *packet,
|
|
|
|
struct fw_iso_buffer *buffer,
|
|
|
|
unsigned long payload)
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
{
|
2011-10-16 01:12:23 +04:00
|
|
|
struct device *device = ctx->context.ohci->card.device;
|
2009-12-11 22:23:58 +03:00
|
|
|
struct descriptor *d, *pd;
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
dma_addr_t d_bus, page_bus;
|
|
|
|
u32 z, header_z, rest;
|
2007-12-19 23:26:38 +03:00
|
|
|
int i, j, length;
|
|
|
|
int page, offset, packet_count, header_size, payload_per_buffer;
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
|
|
|
|
/*
|
2008-07-23 10:23:40 +04:00
|
|
|
* The OHCI controller puts the isochronous header and trailer in the
|
|
|
|
* buffer, so we need at least 8 bytes.
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
*/
|
2010-07-29 20:19:22 +04:00
|
|
|
packet_count = packet->header_length / ctx->base.header_size;
|
2008-07-23 10:23:40 +04:00
|
|
|
header_size = max(ctx->base.header_size, (size_t)8);
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
|
|
|
|
/* Get header size in number of descriptors. */
|
|
|
|
header_z = DIV_ROUND_UP(header_size, sizeof(*d));
|
|
|
|
page = payload >> PAGE_SHIFT;
|
|
|
|
offset = payload & ~PAGE_MASK;
|
2010-07-29 20:19:22 +04:00
|
|
|
payload_per_buffer = packet->payload_length / packet_count;
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
|
|
|
|
for (i = 0; i < packet_count; i++) {
|
|
|
|
/* d points to the header descriptor */
|
2007-12-19 23:26:38 +03:00
|
|
|
z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
d = context_get_descriptors(&ctx->context,
|
2007-12-19 23:26:38 +03:00
|
|
|
z + header_z, &d_bus);
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
if (d == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2007-12-19 23:26:38 +03:00
|
|
|
d->control = cpu_to_le16(DESCRIPTOR_STATUS |
|
|
|
|
DESCRIPTOR_INPUT_MORE);
|
2010-07-29 20:19:22 +04:00
|
|
|
if (packet->skip && i == 0)
|
2007-12-19 23:26:38 +03:00
|
|
|
d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
d->req_count = cpu_to_le16(header_size);
|
|
|
|
d->res_count = d->req_count;
|
2007-12-19 23:26:38 +03:00
|
|
|
d->transfer_status = 0;
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
|
|
|
|
|
2007-12-19 23:26:38 +03:00
|
|
|
rest = payload_per_buffer;
|
2009-12-11 22:23:58 +03:00
|
|
|
pd = d;
|
2007-12-19 23:26:38 +03:00
|
|
|
for (j = 1; j < z; j++) {
|
2009-12-11 22:23:58 +03:00
|
|
|
pd++;
|
2007-12-19 23:26:38 +03:00
|
|
|
pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
|
|
|
|
DESCRIPTOR_INPUT_MORE);
|
|
|
|
|
|
|
|
if (offset + rest < PAGE_SIZE)
|
|
|
|
length = rest;
|
|
|
|
else
|
|
|
|
length = PAGE_SIZE - offset;
|
|
|
|
pd->req_count = cpu_to_le16(length);
|
|
|
|
pd->res_count = pd->req_count;
|
|
|
|
pd->transfer_status = 0;
|
|
|
|
|
|
|
|
page_bus = page_private(buffer->pages[page]);
|
|
|
|
pd->data_address = cpu_to_le32(page_bus + offset);
|
|
|
|
|
2011-10-16 01:12:23 +04:00
|
|
|
dma_sync_single_range_for_device(device, page_bus,
|
|
|
|
offset, length,
|
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
|
2007-12-19 23:26:38 +03:00
|
|
|
offset = (offset + length) & ~PAGE_MASK;
|
|
|
|
rest -= length;
|
|
|
|
if (offset == 0)
|
|
|
|
page++;
|
|
|
|
}
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
|
|
|
|
DESCRIPTOR_INPUT_LAST |
|
|
|
|
DESCRIPTOR_BRANCH_ALWAYS);
|
2010-07-29 20:19:22 +04:00
|
|
|
if (packet->interrupt && i == packet_count - 1)
|
firewire: OHCI 1.0 Isochronous Receive support
Third rendition of FireWire OHCI 1.0 Isochronous Receive support, using a
zer-copy method similar to OHCI 1.1 which puts the IR data payload directly
into the userspace buffer. The zero-copy implementation eliminates the
video artifacts, audio popping, and buffer underrun problems seen with
version 1 of this patch, as well as fixing a regression in OHCI 1.1 support
introduced by version 2 of this patch.
Successfully tested in OHCI 1.1 mode on the following chipsets:
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
- Ti TSB41AB2 (rev 01), OHCI 1.1 (PCI on SB Audigy)
- Apple UniNorth 2 (rev 81), OHCI 1.1 (PowerBook G4 onboard)
Successfully tested in OHCI 1.0 mode on the following chipsets:
- Agere FW323 (rev 06), OHCI 1.0 (Mac Mini onboard)
- Agere FW323 (rev 06), OHCI 1.0 (PCI)
- Via VT6306 (rev 46), OHCI 1.0 (PCI)
- NEC OrangeLink (rev 01), OHCI 1.0 (PCI)
- NEC uPD72847 (rev 01), OHCI 1.1 (PCI)
- Ti XIO2200(A) (rev 01), OHCI 1.1 (PCIe)
The bulk of testing was done in an x86_64 system, but was also successfully
sanity-tested on other systems, including a PPC(32) PowerBook G4 and an i686
EPIA M10k. Crude benchmarking (watching top during capture) puts the cpu
utilization during capture on the EPIA's 1GHz Via C3 processor around 13%,
which is down from 30% with the v1 code.
Some implementation details:
To maintain the same userspace API as dual-buffer mode, we set up two
descriptors for every incoming packet. The first is an INPUT_MORE descriptor,
pointing to a buffer large enough to hold just the packet's iso headers,
immediately followed by an INPUT_LAST descriptor, pointing to a chunk of the
userspace buffer big enough for the packet's data payload. With this setup,
each incoming packet fills in these two descriptors in a manner that very
closely emulates dual-buffer receive, to the point where the bulk of the
handle_ir_* code is now identical between the two (and probably primed for
some restructuring to share code between them).
The only caveat I have at the moment is that neither of my OHCI 1.0 Via
VT6307-based FireWire controllers work particularly well with this code
for reasons I have yet to figure out.
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2007-12-03 21:43:12 +03:00
|
|
|
pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
|
|
|
|
|
|
|
|
context_append(&ctx->context, d, z, header_z);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-07-29 20:19:22 +04:00
|
|
|
static int queue_iso_buffer_fill(struct iso_context *ctx,
|
|
|
|
struct fw_iso_packet *packet,
|
|
|
|
struct fw_iso_buffer *buffer,
|
|
|
|
unsigned long payload)
|
|
|
|
{
|
|
|
|
struct descriptor *d;
|
|
|
|
dma_addr_t d_bus, page_bus;
|
|
|
|
int page, offset, rest, z, i, length;
|
|
|
|
|
|
|
|
page = payload >> PAGE_SHIFT;
|
|
|
|
offset = payload & ~PAGE_MASK;
|
|
|
|
rest = packet->payload_length;
|
|
|
|
|
|
|
|
/* We need one descriptor for each page in the buffer. */
|
|
|
|
z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
|
|
|
|
|
|
|
|
if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
|
|
|
|
return -EFAULT;
|
|
|
|
|
|
|
|
for (i = 0; i < z; i++) {
|
|
|
|
d = context_get_descriptors(&ctx->context, 1, &d_bus);
|
|
|
|
if (d == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
|
|
|
|
DESCRIPTOR_BRANCH_ALWAYS);
|
|
|
|
if (packet->skip && i == 0)
|
|
|
|
d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
|
|
|
|
if (packet->interrupt && i == z - 1)
|
|
|
|
d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
|
|
|
|
|
|
|
|
if (offset + rest < PAGE_SIZE)
|
|
|
|
length = rest;
|
|
|
|
else
|
|
|
|
length = PAGE_SIZE - offset;
|
|
|
|
d->req_count = cpu_to_le16(length);
|
|
|
|
d->res_count = d->req_count;
|
|
|
|
d->transfer_status = 0;
|
|
|
|
|
|
|
|
page_bus = page_private(buffer->pages[page]);
|
|
|
|
d->data_address = cpu_to_le32(page_bus + offset);
|
|
|
|
|
2011-10-16 01:12:23 +04:00
|
|
|
dma_sync_single_range_for_device(ctx->context.ohci->card.device,
|
|
|
|
page_bus, offset, length,
|
|
|
|
DMA_FROM_DEVICE);
|
|
|
|
|
2010-07-29 20:19:22 +04:00
|
|
|
rest -= length;
|
|
|
|
offset = 0;
|
|
|
|
page++;
|
|
|
|
|
|
|
|
context_append(&ctx->context, d, 1, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-12-14 23:47:04 +03:00
|
|
|
static int ohci_queue_iso(struct fw_iso_context *base,
|
|
|
|
struct fw_iso_packet *packet,
|
|
|
|
struct fw_iso_buffer *buffer,
|
|
|
|
unsigned long payload)
|
2007-02-17 01:34:40 +03:00
|
|
|
{
|
2007-02-17 01:34:49 +03:00
|
|
|
struct iso_context *ctx = container_of(base, struct iso_context, base);
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
unsigned long flags;
|
2010-07-29 20:19:22 +04:00
|
|
|
int ret = -ENOSYS;
|
2007-02-17 01:34:49 +03:00
|
|
|
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
spin_lock_irqsave(&ctx->context.ohci->lock, flags);
|
2010-07-29 20:19:22 +04:00
|
|
|
switch (base->type) {
|
|
|
|
case FW_ISO_CONTEXT_TRANSMIT:
|
|
|
|
ret = queue_iso_transmit(ctx, packet, buffer, payload);
|
|
|
|
break;
|
|
|
|
case FW_ISO_CONTEXT_RECEIVE:
|
|
|
|
ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
|
|
|
|
break;
|
|
|
|
case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
|
|
|
|
ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
|
|
|
|
break;
|
|
|
|
}
|
firewire: fw-ohci: Dynamically allocate buffers for DMA descriptors
Previously, the fw-ohci driver used fixed-length buffers for storing
descriptors for isochronous receive DMA programs. If an application
(such as libdc1394) generated a DMA program that was too large, fw-ohci
would reach the limit of its fixed-sized buffer and return an error to
userspace.
This patch replaces the fixed-length ring-buffer with a linked-list of
page-sized buffers. Additional buffers can be dynamically allocated and
appended to the list when necessary. For a particular context, buffers
are kept around after use and reused as necessary, so there is no
allocation taking place after the DMA program is generated for the first
time.
In addition, the buffers it uses are coherent for DMA so there is no
syncing required before and after writes. This syncing wasn't properly
done in the previous version of the code.
-
This is the fourth version of my patch that replaces a fixed-length
buffer for DMA descriptors with a dynamically allocated linked-list of
buffers.
As we discovered with the last attempt, new context programs are
sometimes queued from interrupt context, making it unacceptable to call
tasklet_disable() from context_get_descriptors().
This version of the patch uses ohci->lock for all locking needs instead
of tasklet_disable/enable. There is a new requirement that
context_get_descriptors() be called while holding ohci->lock. It was
already held for the AT context, so adding the requirement for the iso
context did not seem particularly onerous. In addition, this has the
side benefit of allowing iso queue to be safely called from concurrent
user-space threads, which previously was not safe.
Signed-off-by: David Moore <dcm@acm.org>
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Jarod Wilson <jwilson@redhat.com>
-
Fixes the following issues:
- Isochronous reception stopped prematurely if an application used a
larger buffer. (Reproduced with coriander.)
- Isochronous reception stopped after one or a few frames on VT630x
in OHCI 1.0 mode. (Fixes reception in coriander, but dvgrab still
doesn't work with these chips.)
Patch update: struct member alignment, whitespace nits
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2008-01-07 01:21:41 +03:00
|
|
|
spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
|
|
|
|
|
2008-12-14 23:45:45 +03:00
|
|
|
return ret;
|
2007-02-17 01:34:40 +03:00
|
|
|
}
|
|
|
|
|
2011-05-02 11:33:56 +04:00
|
|
|
static void ohci_flush_queue_iso(struct fw_iso_context *base)
|
|
|
|
{
|
|
|
|
struct context *ctx =
|
|
|
|
&container_of(base, struct iso_context, base)->context;
|
|
|
|
|
|
|
|
reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
|
|
|
|
}
|
|
|
|
|
2012-03-18 22:06:39 +04:00
|
|
|
static int ohci_flush_iso_completions(struct fw_iso_context *base)
|
|
|
|
{
|
|
|
|
struct iso_context *ctx = container_of(base, struct iso_context, base);
|
|
|
|
int ret = 0;
|
|
|
|
|
2021-03-09 11:42:16 +03:00
|
|
|
tasklet_disable_in_atomic(&ctx->context.tasklet);
|
2012-03-18 22:06:39 +04:00
|
|
|
|
|
|
|
if (!test_and_set_bit_lock(0, &ctx->flushing_completions)) {
|
|
|
|
context_tasklet((unsigned long)&ctx->context);
|
|
|
|
|
|
|
|
switch (base->type) {
|
|
|
|
case FW_ISO_CONTEXT_TRANSMIT:
|
|
|
|
case FW_ISO_CONTEXT_RECEIVE:
|
|
|
|
if (ctx->header_length != 0)
|
|
|
|
flush_iso_completions(ctx);
|
|
|
|
break;
|
|
|
|
case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
|
|
|
|
if (ctx->mc_completed != 0)
|
|
|
|
flush_ir_buffer_fill(ctx);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
ret = -ENOSYS;
|
|
|
|
}
|
|
|
|
|
|
|
|
clear_bit_unlock(0, &ctx->flushing_completions);
|
2014-03-17 21:06:10 +04:00
|
|
|
smp_mb__after_atomic();
|
2012-03-18 22:06:39 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
tasklet_enable(&ctx->context.tasklet);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2007-01-14 17:29:07 +03:00
|
|
|
static const struct fw_card_driver ohci_driver = {
|
2006-12-20 03:58:35 +03:00
|
|
|
.enable = ohci_enable,
|
2010-07-08 18:09:06 +04:00
|
|
|
.read_phy_reg = ohci_read_phy_reg,
|
2006-12-20 03:58:35 +03:00
|
|
|
.update_phy_reg = ohci_update_phy_reg,
|
|
|
|
.set_config_rom = ohci_set_config_rom,
|
|
|
|
.send_request = ohci_send_request,
|
|
|
|
.send_response = ohci_send_response,
|
2007-02-06 22:49:32 +03:00
|
|
|
.cancel_packet = ohci_cancel_packet,
|
2006-12-20 03:58:35 +03:00
|
|
|
.enable_phys_dma = ohci_enable_phys_dma,
|
2010-06-12 22:35:52 +04:00
|
|
|
.read_csr = ohci_read_csr,
|
|
|
|
.write_csr = ohci_write_csr,
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
.allocate_iso_context = ohci_allocate_iso_context,
|
|
|
|
.free_iso_context = ohci_free_iso_context,
|
2010-07-29 20:19:22 +04:00
|
|
|
.set_iso_channels = ohci_set_iso_channels,
|
2006-12-20 03:58:35 +03:00
|
|
|
.queue_iso = ohci_queue_iso,
|
2011-05-02 11:33:56 +04:00
|
|
|
.flush_queue_iso = ohci_flush_queue_iso,
|
2012-03-18 22:06:39 +04:00
|
|
|
.flush_iso_completions = ohci_flush_iso_completions,
|
2007-02-17 01:34:41 +03:00
|
|
|
.start_iso = ohci_start_iso,
|
2007-02-17 01:34:42 +03:00
|
|
|
.stop_iso = ohci_stop_iso,
|
2006-12-20 03:58:35 +03:00
|
|
|
};
|
|
|
|
|
2008-03-01 04:42:56 +03:00
|
|
|
#ifdef CONFIG_PPC_PMAC
|
2010-04-02 16:05:02 +04:00
|
|
|
static void pmac_ohci_on(struct pci_dev *dev)
|
2008-03-01 14:35:29 +03:00
|
|
|
{
|
2008-03-01 04:42:56 +03:00
|
|
|
if (machine_is(powermac)) {
|
|
|
|
struct device_node *ofn = pci_device_to_OF_node(dev);
|
|
|
|
|
|
|
|
if (ofn) {
|
|
|
|
pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
|
|
|
|
pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
|
|
|
|
}
|
|
|
|
}
|
2008-03-01 14:35:29 +03:00
|
|
|
}
|
|
|
|
|
2010-04-02 16:05:02 +04:00
|
|
|
static void pmac_ohci_off(struct pci_dev *dev)
|
2008-03-01 14:35:29 +03:00
|
|
|
{
|
|
|
|
if (machine_is(powermac)) {
|
|
|
|
struct device_node *ofn = pci_device_to_OF_node(dev);
|
|
|
|
|
|
|
|
if (ofn) {
|
|
|
|
pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
|
|
|
|
pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#else
|
2010-04-02 16:05:02 +04:00
|
|
|
static inline void pmac_ohci_on(struct pci_dev *dev) {}
|
|
|
|
static inline void pmac_ohci_off(struct pci_dev *dev) {}
|
2008-03-01 04:42:56 +03:00
|
|
|
#endif /* CONFIG_PPC_PMAC */
|
|
|
|
|
2012-11-19 22:22:57 +04:00
|
|
|
static int pci_probe(struct pci_dev *dev,
|
2008-12-14 23:47:04 +03:00
|
|
|
const struct pci_device_id *ent)
|
2008-03-01 14:35:29 +03:00
|
|
|
{
|
|
|
|
struct fw_ohci *ohci;
|
2010-10-17 16:09:12 +04:00
|
|
|
u32 bus_options, max_receive, link_speed, version;
|
2008-03-01 14:35:29 +03:00
|
|
|
u64 guid;
|
2010-11-29 05:09:50 +03:00
|
|
|
int i, err;
|
2008-03-01 14:35:29 +03:00
|
|
|
size_t size;
|
|
|
|
|
2011-07-10 02:23:03 +04:00
|
|
|
if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
|
|
|
|
dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
|
|
|
|
return -ENOSYS;
|
|
|
|
}
|
|
|
|
|
2007-05-10 03:23:14 +04:00
|
|
|
ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
|
2006-12-20 03:58:35 +03:00
|
|
|
if (ohci == NULL) {
|
2008-10-26 11:50:31 +03:00
|
|
|
err = -ENOMEM;
|
|
|
|
goto fail;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
|
|
|
|
|
2010-04-02 16:05:02 +04:00
|
|
|
pmac_ohci_on(dev);
|
2008-03-24 22:55:28 +03:00
|
|
|
|
2007-05-10 03:23:15 +04:00
|
|
|
err = pci_enable_device(dev);
|
|
|
|
if (err) {
|
2011-12-21 00:32:46 +04:00
|
|
|
dev_err(&dev->dev, "failed to enable OHCI hardware\n");
|
2008-02-24 20:59:55 +03:00
|
|
|
goto fail_free;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
pci_set_master(dev);
|
|
|
|
pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
|
|
|
|
pci_set_drvdata(dev, ohci);
|
|
|
|
|
|
|
|
spin_lock_init(&ohci->lock);
|
2010-07-08 18:09:06 +04:00
|
|
|
mutex_init(&ohci->phy_reg_mutex);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2011-07-26 00:16:24 +04:00
|
|
|
INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2012-06-04 23:28:07 +04:00
|
|
|
if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM) ||
|
|
|
|
pci_resource_len(dev, 0) < OHCI1394_REGISTER_SIZE) {
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "invalid MMIO resource\n");
|
2012-06-04 23:28:07 +04:00
|
|
|
err = -ENXIO;
|
|
|
|
goto fail_disable;
|
|
|
|
}
|
|
|
|
|
2007-05-10 03:23:15 +04:00
|
|
|
err = pci_request_region(dev, 0, ohci_driver_name);
|
|
|
|
if (err) {
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "MMIO resource unavailable\n");
|
2007-05-10 03:23:15 +04:00
|
|
|
goto fail_disable;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
|
|
|
|
if (ohci->registers == NULL) {
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "failed to remap registers\n");
|
2007-05-10 03:23:15 +04:00
|
|
|
err = -ENXIO;
|
|
|
|
goto fail_iomem;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2010-02-21 19:58:01 +03:00
|
|
|
for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
|
2010-12-07 22:32:40 +03:00
|
|
|
if ((ohci_quirks[i].vendor == dev->vendor) &&
|
|
|
|
(ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
|
|
|
|
ohci_quirks[i].device == dev->device) &&
|
|
|
|
(ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
|
|
|
|
ohci_quirks[i].revision >= dev->revision)) {
|
2010-02-21 19:58:01 +03:00
|
|
|
ohci->quirks = ohci_quirks[i].flags;
|
|
|
|
break;
|
|
|
|
}
|
2010-02-21 19:58:29 +03:00
|
|
|
if (param_quirks)
|
|
|
|
ohci->quirks = param_quirks;
|
2010-01-20 11:58:02 +03:00
|
|
|
|
2010-11-30 10:25:17 +03:00
|
|
|
/*
|
|
|
|
* Because dma_alloc_coherent() allocates at least one page,
|
|
|
|
* we save space by using a common buffer for the AR request/
|
|
|
|
* response descriptors and the self IDs buffer.
|
|
|
|
*/
|
|
|
|
BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
|
|
|
|
BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
|
|
|
|
ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
|
|
|
|
PAGE_SIZE,
|
|
|
|
&ohci->misc_buffer_bus,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!ohci->misc_buffer) {
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto fail_iounmap;
|
|
|
|
}
|
|
|
|
|
|
|
|
err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
|
2010-11-26 10:57:31 +03:00
|
|
|
OHCI1394_AsReqRcvContextControlSet);
|
|
|
|
if (err < 0)
|
2010-11-30 10:25:17 +03:00
|
|
|
goto fail_misc_buf;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2010-11-30 10:25:17 +03:00
|
|
|
err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
|
2010-11-26 10:57:31 +03:00
|
|
|
OHCI1394_AsRspRcvContextControlSet);
|
|
|
|
if (err < 0)
|
|
|
|
goto fail_arreq_ctx;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2010-11-30 10:24:01 +03:00
|
|
|
err = context_init(&ohci->at_request_ctx, ohci,
|
|
|
|
OHCI1394_AsReqTrContextControlSet, handle_at_packet);
|
|
|
|
if (err < 0)
|
|
|
|
goto fail_arrsp_ctx;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2010-11-30 10:24:01 +03:00
|
|
|
err = context_init(&ohci->at_response_ctx, ohci,
|
|
|
|
OHCI1394_AsRspTrContextControlSet, handle_at_packet);
|
|
|
|
if (err < 0)
|
|
|
|
goto fail_atreq_ctx;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
|
2010-02-21 19:58:52 +03:00
|
|
|
ohci->ir_context_channels = ~0ULL;
|
2011-01-10 19:21:35 +03:00
|
|
|
ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
|
2006-12-20 03:58:35 +03:00
|
|
|
reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
|
2011-01-10 19:21:35 +03:00
|
|
|
ohci->ir_context_mask = ohci->ir_context_support;
|
2010-11-29 05:09:50 +03:00
|
|
|
ohci->n_ir = hweight32(ohci->ir_context_mask);
|
|
|
|
size = sizeof(struct iso_context) * ohci->n_ir;
|
2010-02-21 19:58:52 +03:00
|
|
|
ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
|
2011-01-10 19:21:35 +03:00
|
|
|
ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
|
firewire: ohci: fix JMicron JMB38x IT context discovery
Reported by Clifford and Craig for JMicron OHCI-1394 + SDHCI combo
controllers: Often or even most of the time, the controller is
initialized with the message "added OHCI v1.10 device as card 0, 4 IR +
0 IT contexts, quirks 0x10". With 0 isochronous transmit DMA contexts
(IT contexts), applications like audio output are impossible.
However, OHCI-1394 demands that at least 4 IT contexts are implemented
by the link layer controller, and indeed JMicron JMB38x do implement
four of them. Only their IsoXmitIntMask register is unreliable at early
access.
With my own JMB381 single function controller I found:
- I can reproduce the problem with a lower probability than Craig's.
- If I put a loop around the section which clears and reads
IsoXmitIntMask, then either the first or the second attempt will
return the correct initial mask of 0x0000000f. I never encountered
a case of needing more than a second attempt.
- Consequently, if I put a dummy reg_read(...IsoXmitIntMaskSet)
before the first write, the subsequent read will return the correct
result.
- If I merely ignore a wrong read result and force the known real
result, later isochronous transmit DMA usage works just fine.
So let's just fix this chip bug up by the latter method. Tested with
JMB381 on kernel 3.13 and 4.3.
Since OHCI-1394 generally requires 4 IT contexts at a minium, this
workaround is simply applied whenever the initial read of IsoXmitIntMask
returns 0, regardless whether it's a JMicron chip or not. I never heard
of this issue together with any other chip though.
I am not 100% sure that this fix works on the OHCI-1394 part of JMB380
and JMB388 combo controllers exactly the same as on the JMB381 single-
function controller, but so far I haven't had a chance to let an owner
of a combo chip run a patched kernel.
Strangely enough, IsoRecvIntMask is always reported correctly, even
though it is probed right before IsoXmitIntMask.
Reported-by: Clifford Dunn
Reported-by: Craig Moore <craig.moore@qenos.com>
Cc: stable@vger.kernel.org
Signed-off-by: Stefan Richter <stefanr@s5r6.in-berlin.de>
2015-11-03 03:46:21 +03:00
|
|
|
/* JMicron JMB38x often shows 0 at first read, just ignore it */
|
|
|
|
if (!ohci->it_context_support) {
|
|
|
|
ohci_notice(ohci, "overriding IsoXmitIntMask\n");
|
|
|
|
ohci->it_context_support = 0xf;
|
|
|
|
}
|
2006-12-20 03:58:35 +03:00
|
|
|
reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
|
2011-01-10 19:21:35 +03:00
|
|
|
ohci->it_context_mask = ohci->it_context_support;
|
2010-11-29 05:09:50 +03:00
|
|
|
ohci->n_it = hweight32(ohci->it_context_mask);
|
|
|
|
size = sizeof(struct iso_context) * ohci->n_it;
|
2010-02-21 19:58:52 +03:00
|
|
|
ohci->it_context_list = kzalloc(size, GFP_KERNEL);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
|
2007-05-10 03:23:15 +04:00
|
|
|
err = -ENOMEM;
|
2008-10-26 11:50:31 +03:00
|
|
|
goto fail_contexts;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2013-08-05 17:10:38 +04:00
|
|
|
ohci->self_id = ohci->misc_buffer + PAGE_SIZE/2;
|
2010-11-30 10:25:17 +03:00
|
|
|
ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
bus_options = reg_read(ohci, OHCI1394_BusOptions);
|
|
|
|
max_receive = (bus_options >> 12) & 0xf;
|
|
|
|
link_speed = bus_options & 0x7;
|
|
|
|
guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
|
|
|
|
reg_read(ohci, OHCI1394_GUIDLo);
|
|
|
|
|
2013-03-27 14:59:58 +04:00
|
|
|
if (!(ohci->quirks & QUIRK_NO_MSI))
|
|
|
|
pci_enable_msi(dev);
|
|
|
|
if (request_irq(dev->irq, irq_handler,
|
|
|
|
pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
|
|
|
|
ohci_driver_name, ohci)) {
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "failed to allocate interrupt %d\n", dev->irq);
|
2013-03-27 14:59:58 +04:00
|
|
|
err = -EIO;
|
|
|
|
goto fail_msi;
|
|
|
|
}
|
|
|
|
|
2007-05-10 03:23:15 +04:00
|
|
|
err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
|
2009-02-03 19:55:19 +03:00
|
|
|
if (err)
|
2013-03-27 14:59:58 +04:00
|
|
|
goto fail_irq;
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2010-02-21 19:59:14 +03:00
|
|
|
version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_notice(ohci,
|
|
|
|
"added OHCI v%x.%x device as card %d, "
|
2014-01-18 20:32:20 +04:00
|
|
|
"%d IR + %d IT contexts, quirks 0x%x%s\n",
|
2013-03-26 19:54:06 +04:00
|
|
|
version >> 16, version & 0xff, ohci->card.index,
|
2014-01-18 20:32:20 +04:00
|
|
|
ohci->n_ir, ohci->n_it, ohci->quirks,
|
|
|
|
reg_read(ohci, OHCI1394_PhyUpperBound) ?
|
2014-05-29 17:23:26 +04:00
|
|
|
", physUB" : "");
|
2009-02-03 19:55:19 +03:00
|
|
|
|
2006-12-20 03:58:35 +03:00
|
|
|
return 0;
|
2007-05-10 03:23:15 +04:00
|
|
|
|
2013-03-27 14:59:58 +04:00
|
|
|
fail_irq:
|
|
|
|
free_irq(dev->irq, ohci);
|
|
|
|
fail_msi:
|
|
|
|
pci_disable_msi(dev);
|
2008-10-26 11:50:31 +03:00
|
|
|
fail_contexts:
|
2007-05-10 03:23:15 +04:00
|
|
|
kfree(ohci->ir_context_list);
|
2008-10-26 11:50:31 +03:00
|
|
|
kfree(ohci->it_context_list);
|
|
|
|
context_release(&ohci->at_response_ctx);
|
2010-11-30 10:24:01 +03:00
|
|
|
fail_atreq_ctx:
|
2008-10-26 11:50:31 +03:00
|
|
|
context_release(&ohci->at_request_ctx);
|
2010-11-30 10:24:01 +03:00
|
|
|
fail_arrsp_ctx:
|
2008-10-26 11:50:31 +03:00
|
|
|
ar_context_release(&ohci->ar_response_ctx);
|
2010-11-26 10:57:31 +03:00
|
|
|
fail_arreq_ctx:
|
2008-10-26 11:50:31 +03:00
|
|
|
ar_context_release(&ohci->ar_request_ctx);
|
2010-11-30 10:25:17 +03:00
|
|
|
fail_misc_buf:
|
|
|
|
dma_free_coherent(ohci->card.device, PAGE_SIZE,
|
|
|
|
ohci->misc_buffer, ohci->misc_buffer_bus);
|
2010-11-26 10:57:31 +03:00
|
|
|
fail_iounmap:
|
2007-05-10 03:23:15 +04:00
|
|
|
pci_iounmap(dev, ohci->registers);
|
|
|
|
fail_iomem:
|
|
|
|
pci_release_region(dev, 0);
|
|
|
|
fail_disable:
|
|
|
|
pci_disable_device(dev);
|
2008-02-24 20:59:55 +03:00
|
|
|
fail_free:
|
2011-03-11 04:17:27 +03:00
|
|
|
kfree(ohci);
|
2010-04-02 16:05:02 +04:00
|
|
|
pmac_ohci_off(dev);
|
2008-10-26 11:50:31 +03:00
|
|
|
fail:
|
2007-05-10 03:23:15 +04:00
|
|
|
return err;
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pci_remove(struct pci_dev *dev)
|
|
|
|
{
|
2013-03-27 14:59:59 +04:00
|
|
|
struct fw_ohci *ohci = pci_get_drvdata(dev);
|
2006-12-20 03:58:35 +03:00
|
|
|
|
2013-03-27 14:59:59 +04:00
|
|
|
/*
|
|
|
|
* If the removal is happening from the suspend state, LPS won't be
|
|
|
|
* enabled and host registers (eg., IntMaskClear) won't be accessible.
|
|
|
|
*/
|
|
|
|
if (reg_read(ohci, OHCI1394_HCControlSet) & OHCI1394_HCControl_LPS) {
|
|
|
|
reg_write(ohci, OHCI1394_IntMaskClear, ~0);
|
|
|
|
flush_writes(ohci);
|
|
|
|
}
|
2011-07-26 00:16:24 +04:00
|
|
|
cancel_work_sync(&ohci->bus_reset_work);
|
2006-12-20 03:58:35 +03:00
|
|
|
fw_core_remove_card(&ohci->card);
|
|
|
|
|
2007-05-08 04:33:32 +04:00
|
|
|
/*
|
|
|
|
* FIXME: Fail all pending packets here, now that the upper
|
|
|
|
* layers can't queue any more.
|
|
|
|
*/
|
2006-12-20 03:58:35 +03:00
|
|
|
|
|
|
|
software_reset(ohci);
|
|
|
|
free_irq(dev->irq, ohci);
|
2008-10-22 23:59:42 +04:00
|
|
|
|
|
|
|
if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
|
|
|
|
dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
|
|
|
|
ohci->next_config_rom, ohci->next_config_rom_bus);
|
|
|
|
if (ohci->config_rom)
|
|
|
|
dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
|
|
|
|
ohci->config_rom, ohci->config_rom_bus);
|
|
|
|
ar_context_release(&ohci->ar_request_ctx);
|
|
|
|
ar_context_release(&ohci->ar_response_ctx);
|
2010-11-30 10:25:17 +03:00
|
|
|
dma_free_coherent(ohci->card.device, PAGE_SIZE,
|
|
|
|
ohci->misc_buffer, ohci->misc_buffer_bus);
|
2008-10-22 23:59:42 +04:00
|
|
|
context_release(&ohci->at_request_ctx);
|
|
|
|
context_release(&ohci->at_response_ctx);
|
2007-05-10 03:23:15 +04:00
|
|
|
kfree(ohci->it_context_list);
|
|
|
|
kfree(ohci->ir_context_list);
|
2010-06-05 14:31:25 +04:00
|
|
|
pci_disable_msi(dev);
|
2007-05-10 03:23:15 +04:00
|
|
|
pci_iounmap(dev, ohci->registers);
|
|
|
|
pci_release_region(dev, 0);
|
|
|
|
pci_disable_device(dev);
|
2011-03-11 04:17:27 +03:00
|
|
|
kfree(ohci);
|
2010-04-02 16:05:02 +04:00
|
|
|
pmac_ohci_off(dev);
|
2008-03-01 04:42:56 +03:00
|
|
|
|
2011-12-21 00:32:46 +04:00
|
|
|
dev_notice(&dev->dev, "removed fw-ohci device\n");
|
2006-12-20 03:58:35 +03:00
|
|
|
}
|
|
|
|
|
2007-05-31 03:06:35 +04:00
|
|
|
#ifdef CONFIG_PM
|
2008-03-01 14:35:29 +03:00
|
|
|
static int pci_suspend(struct pci_dev *dev, pm_message_t state)
|
2007-05-31 03:06:35 +04:00
|
|
|
{
|
2008-03-01 14:35:29 +03:00
|
|
|
struct fw_ohci *ohci = pci_get_drvdata(dev);
|
2007-05-31 03:06:35 +04:00
|
|
|
int err;
|
|
|
|
|
|
|
|
software_reset(ohci);
|
2008-03-01 14:35:29 +03:00
|
|
|
err = pci_save_state(dev);
|
2007-05-31 03:06:35 +04:00
|
|
|
if (err) {
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "pci_save_state failed\n");
|
2007-05-31 03:06:35 +04:00
|
|
|
return err;
|
|
|
|
}
|
2008-03-01 14:35:29 +03:00
|
|
|
err = pci_set_power_state(dev, pci_choose_state(dev, state));
|
2007-09-06 11:50:30 +04:00
|
|
|
if (err)
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "pci_set_power_state failed with %d\n", err);
|
2010-04-02 16:05:02 +04:00
|
|
|
pmac_ohci_off(dev);
|
2008-03-01 04:42:56 +03:00
|
|
|
|
2007-05-31 03:06:35 +04:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-03-01 14:35:29 +03:00
|
|
|
static int pci_resume(struct pci_dev *dev)
|
2007-05-31 03:06:35 +04:00
|
|
|
{
|
2008-03-01 14:35:29 +03:00
|
|
|
struct fw_ohci *ohci = pci_get_drvdata(dev);
|
2007-05-31 03:06:35 +04:00
|
|
|
int err;
|
|
|
|
|
2010-04-02 16:05:02 +04:00
|
|
|
pmac_ohci_on(dev);
|
2008-03-01 14:35:29 +03:00
|
|
|
pci_set_power_state(dev, PCI_D0);
|
|
|
|
pci_restore_state(dev);
|
|
|
|
err = pci_enable_device(dev);
|
2007-05-31 03:06:35 +04:00
|
|
|
if (err) {
|
2013-03-26 19:54:06 +04:00
|
|
|
ohci_err(ohci, "pci_enable_device failed\n");
|
2007-05-31 03:06:35 +04:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2010-11-29 05:09:49 +03:00
|
|
|
/* Some systems don't setup GUID register on resume from ram */
|
|
|
|
if (!reg_read(ohci, OHCI1394_GUIDLo) &&
|
|
|
|
!reg_read(ohci, OHCI1394_GUIDHi)) {
|
|
|
|
reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
|
|
|
|
reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
|
|
|
|
}
|
|
|
|
|
2010-11-29 05:09:50 +03:00
|
|
|
err = ohci_enable(&ohci->card, NULL, 0);
|
|
|
|
if (err)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
ohci_resume_iso_dma(ohci);
|
2011-01-01 17:17:05 +03:00
|
|
|
|
2010-11-29 05:09:50 +03:00
|
|
|
return 0;
|
2007-05-31 03:06:35 +04:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2010-01-10 15:14:26 +03:00
|
|
|
static const struct pci_device_id pci_table[] = {
|
2006-12-20 03:58:35 +03:00
|
|
|
{ PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
MODULE_DEVICE_TABLE(pci, pci_table);
|
|
|
|
|
|
|
|
static struct pci_driver fw_ohci_pci_driver = {
|
|
|
|
.name = ohci_driver_name,
|
|
|
|
.id_table = pci_table,
|
|
|
|
.probe = pci_probe,
|
|
|
|
.remove = pci_remove,
|
2007-05-31 03:06:35 +04:00
|
|
|
#ifdef CONFIG_PM
|
|
|
|
.resume = pci_resume,
|
|
|
|
.suspend = pci_suspend,
|
|
|
|
#endif
|
2006-12-20 03:58:35 +03:00
|
|
|
};
|
|
|
|
|
2013-08-26 22:50:04 +04:00
|
|
|
static int __init fw_ohci_init(void)
|
|
|
|
{
|
2013-08-26 22:50:05 +04:00
|
|
|
selfid_workqueue = alloc_workqueue(KBUILD_MODNAME, WQ_MEM_RECLAIM, 0);
|
|
|
|
if (!selfid_workqueue)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2013-08-26 22:50:04 +04:00
|
|
|
return pci_register_driver(&fw_ohci_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit fw_ohci_cleanup(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&fw_ohci_pci_driver);
|
2013-08-26 22:50:05 +04:00
|
|
|
destroy_workqueue(selfid_workqueue);
|
2013-08-26 22:50:04 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
module_init(fw_ohci_init);
|
|
|
|
module_exit(fw_ohci_cleanup);
|
2012-04-03 06:07:01 +04:00
|
|
|
|
2006-12-20 03:58:35 +03:00
|
|
|
MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
|
|
|
|
MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|
2007-05-06 01:17:13 +04:00
|
|
|
/* Provide a module alias so root-on-sbp2 initrds don't break. */
|
|
|
|
MODULE_ALIAS("ohci1394");
|