2018-12-17 17:01:20 +03:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 NXP
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* Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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2019-02-20 14:40:51 +03:00
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#include <linux/of_irq.h>
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2018-12-17 17:01:20 +03:00
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#include <linux/of_platform.h>
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#include <linux/spinlock.h>
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2019-02-20 14:40:47 +03:00
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#define CTRL_STRIDE_OFF(_t, _r) (_t * 4 * _r)
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2018-12-17 17:01:20 +03:00
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#define CHANCTRL 0x0
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#define CHANMASK(n, t) (CTRL_STRIDE_OFF(t, 0) + 0x4 * (n) + 0x4)
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#define CHANSET(n, t) (CTRL_STRIDE_OFF(t, 1) + 0x4 * (n) + 0x4)
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#define CHANSTATUS(n, t) (CTRL_STRIDE_OFF(t, 2) + 0x4 * (n) + 0x4)
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#define CHAN_MINTDIS(t) (CTRL_STRIDE_OFF(t, 3) + 0x4)
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#define CHAN_MASTRSTAT(t) (CTRL_STRIDE_OFF(t, 3) + 0x8)
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2019-02-20 14:40:51 +03:00
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#define CHAN_MAX_OUTPUT_INT 0x8
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2018-12-17 17:01:20 +03:00
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struct irqsteer_data {
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void __iomem *regs;
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struct clk *ipg_clk;
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2019-02-20 14:40:51 +03:00
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int irq[CHAN_MAX_OUTPUT_INT];
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int irq_count;
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2018-12-17 17:01:20 +03:00
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raw_spinlock_t lock;
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2019-02-20 14:40:47 +03:00
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int reg_num;
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2018-12-17 17:01:20 +03:00
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int channel;
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struct irq_domain *domain;
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u32 *saved_reg;
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};
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static int imx_irqsteer_get_reg_index(struct irqsteer_data *data,
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unsigned long irqnum)
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{
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2019-02-20 14:40:47 +03:00
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return (data->reg_num - irqnum / 32 - 1);
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2018-12-17 17:01:20 +03:00
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}
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static void imx_irqsteer_irq_unmask(struct irq_data *d)
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{
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struct irqsteer_data *data = d->chip_data;
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int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
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unsigned long flags;
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u32 val;
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raw_spin_lock_irqsave(&data->lock, flags);
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2019-02-20 14:40:47 +03:00
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val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
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2018-12-17 17:01:20 +03:00
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val |= BIT(d->hwirq % 32);
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2019-02-20 14:40:47 +03:00
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writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
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2018-12-17 17:01:20 +03:00
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raw_spin_unlock_irqrestore(&data->lock, flags);
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}
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static void imx_irqsteer_irq_mask(struct irq_data *d)
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{
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struct irqsteer_data *data = d->chip_data;
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int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
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unsigned long flags;
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u32 val;
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raw_spin_lock_irqsave(&data->lock, flags);
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2019-02-20 14:40:47 +03:00
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val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
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2018-12-17 17:01:20 +03:00
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val &= ~BIT(d->hwirq % 32);
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2019-02-20 14:40:47 +03:00
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writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
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2018-12-17 17:01:20 +03:00
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raw_spin_unlock_irqrestore(&data->lock, flags);
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}
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static struct irq_chip imx_irqsteer_irq_chip = {
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.name = "irqsteer",
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.irq_mask = imx_irqsteer_irq_mask,
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.irq_unmask = imx_irqsteer_irq_unmask,
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};
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static int imx_irqsteer_irq_map(struct irq_domain *h, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_status_flags(irq, IRQ_LEVEL);
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irq_set_chip_data(irq, h->host_data);
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irq_set_chip_and_handler(irq, &imx_irqsteer_irq_chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops imx_irqsteer_domain_ops = {
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.map = imx_irqsteer_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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2019-02-20 14:40:51 +03:00
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static int imx_irqsteer_get_hwirq_base(struct irqsteer_data *data, u32 irq)
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{
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int i;
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for (i = 0; i < data->irq_count; i++) {
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if (data->irq[i] == irq)
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return i * 64;
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}
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return -EINVAL;
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}
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2018-12-17 17:01:20 +03:00
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static void imx_irqsteer_irq_handler(struct irq_desc *desc)
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{
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struct irqsteer_data *data = irq_desc_get_handler_data(desc);
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2019-02-20 14:40:51 +03:00
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int hwirq;
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int irq, i;
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2018-12-17 17:01:20 +03:00
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chained_irq_enter(irq_desc_get_chip(desc), desc);
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2019-02-20 14:40:51 +03:00
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irq = irq_desc_get_irq(desc);
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hwirq = imx_irqsteer_get_hwirq_base(data, irq);
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if (hwirq < 0) {
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pr_warn("%s: unable to get hwirq base for irq %d\n",
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__func__, irq);
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return;
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}
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for (i = 0; i < 2; i++, hwirq += 32) {
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int idx = imx_irqsteer_get_reg_index(data, hwirq);
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2018-12-17 17:01:20 +03:00
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unsigned long irqmap;
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2021-05-04 19:42:18 +03:00
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int pos;
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2018-12-17 17:01:20 +03:00
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2019-02-20 14:40:51 +03:00
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if (hwirq >= data->reg_num * 32)
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break;
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2018-12-17 17:01:20 +03:00
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irqmap = readl_relaxed(data->regs +
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2019-02-20 14:40:47 +03:00
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CHANSTATUS(idx, data->reg_num));
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2018-12-17 17:01:20 +03:00
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2021-05-04 19:42:18 +03:00
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for_each_set_bit(pos, &irqmap, 32)
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generic_handle_domain_irq(data->domain, pos + hwirq);
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2018-12-17 17:01:20 +03:00
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}
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chained_irq_exit(irq_desc_get_chip(desc), desc);
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}
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static int imx_irqsteer_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct irqsteer_data *data;
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2019-02-20 14:40:51 +03:00
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u32 irqs_num;
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int i, ret;
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2018-12-17 17:01:20 +03:00
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data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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2019-04-01 09:21:51 +03:00
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data->regs = devm_platform_ioremap_resource(pdev, 0);
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2018-12-17 17:01:20 +03:00
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if (IS_ERR(data->regs)) {
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dev_err(&pdev->dev, "failed to initialize reg\n");
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return PTR_ERR(data->regs);
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}
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data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
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2020-08-11 09:16:16 +03:00
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if (IS_ERR(data->ipg_clk))
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return dev_err_probe(&pdev->dev, PTR_ERR(data->ipg_clk),
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"failed to get ipg clk\n");
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2018-12-17 17:01:20 +03:00
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raw_spin_lock_init(&data->lock);
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2019-03-04 23:02:18 +03:00
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ret = of_property_read_u32(np, "fsl,num-irqs", &irqs_num);
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if (ret)
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return ret;
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ret = of_property_read_u32(np, "fsl,channel", &data->channel);
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if (ret)
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return ret;
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2018-12-17 17:01:20 +03:00
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2019-02-20 14:40:51 +03:00
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/*
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* There is one output irq for each group of 64 inputs.
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* One register bit map can represent 32 input interrupts.
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*/
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data->irq_count = DIV_ROUND_UP(irqs_num, 64);
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data->reg_num = irqs_num / 32;
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2019-02-20 14:40:47 +03:00
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2018-12-17 17:01:20 +03:00
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if (IS_ENABLED(CONFIG_PM_SLEEP)) {
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data->saved_reg = devm_kzalloc(&pdev->dev,
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2019-02-20 14:40:47 +03:00
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sizeof(u32) * data->reg_num,
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2018-12-17 17:01:20 +03:00
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GFP_KERNEL);
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if (!data->saved_reg)
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return -ENOMEM;
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}
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ret = clk_prepare_enable(data->ipg_clk);
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if (ret) {
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dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
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return ret;
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}
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/* steer all IRQs into configured channel */
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writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
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2019-02-20 14:40:47 +03:00
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data->domain = irq_domain_add_linear(np, data->reg_num * 32,
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2018-12-17 17:01:20 +03:00
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&imx_irqsteer_domain_ops, data);
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if (!data->domain) {
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dev_err(&pdev->dev, "failed to create IRQ domain\n");
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2019-02-20 14:40:51 +03:00
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ret = -ENOMEM;
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goto out;
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2018-12-17 17:01:20 +03:00
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}
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2019-02-20 14:40:51 +03:00
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if (!data->irq_count || data->irq_count > CHAN_MAX_OUTPUT_INT) {
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ret = -EINVAL;
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goto out;
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}
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for (i = 0; i < data->irq_count; i++) {
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data->irq[i] = irq_of_parse_and_map(np, i);
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if (!data->irq[i]) {
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ret = -EINVAL;
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goto out;
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}
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irq_set_chained_handler_and_data(data->irq[i],
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imx_irqsteer_irq_handler,
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data);
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}
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2018-12-17 17:01:20 +03:00
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platform_set_drvdata(pdev, data);
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return 0;
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2019-02-20 14:40:51 +03:00
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out:
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clk_disable_unprepare(data->ipg_clk);
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return ret;
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2018-12-17 17:01:20 +03:00
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}
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static int imx_irqsteer_remove(struct platform_device *pdev)
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{
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struct irqsteer_data *irqsteer_data = platform_get_drvdata(pdev);
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2019-02-20 14:40:51 +03:00
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int i;
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for (i = 0; i < irqsteer_data->irq_count; i++)
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irq_set_chained_handler_and_data(irqsteer_data->irq[i],
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NULL, NULL);
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2018-12-17 17:01:20 +03:00
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irq_domain_remove(irqsteer_data->domain);
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clk_disable_unprepare(irqsteer_data->ipg_clk);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static void imx_irqsteer_save_regs(struct irqsteer_data *data)
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{
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int i;
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2019-02-20 14:40:47 +03:00
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for (i = 0; i < data->reg_num; i++)
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2018-12-17 17:01:20 +03:00
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data->saved_reg[i] = readl_relaxed(data->regs +
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2019-02-20 14:40:47 +03:00
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CHANMASK(i, data->reg_num));
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2018-12-17 17:01:20 +03:00
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}
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static void imx_irqsteer_restore_regs(struct irqsteer_data *data)
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{
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int i;
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writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
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2019-02-20 14:40:47 +03:00
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for (i = 0; i < data->reg_num; i++)
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2018-12-17 17:01:20 +03:00
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writel_relaxed(data->saved_reg[i],
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2019-02-20 14:40:47 +03:00
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data->regs + CHANMASK(i, data->reg_num));
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2018-12-17 17:01:20 +03:00
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}
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static int imx_irqsteer_suspend(struct device *dev)
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{
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struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
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imx_irqsteer_save_regs(irqsteer_data);
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clk_disable_unprepare(irqsteer_data->ipg_clk);
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return 0;
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}
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static int imx_irqsteer_resume(struct device *dev)
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{
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struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
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int ret;
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ret = clk_prepare_enable(irqsteer_data->ipg_clk);
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if (ret) {
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dev_err(dev, "failed to enable ipg clk: %d\n", ret);
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return ret;
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}
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imx_irqsteer_restore_regs(irqsteer_data);
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return 0;
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}
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#endif
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static const struct dev_pm_ops imx_irqsteer_pm_ops = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_irqsteer_suspend, imx_irqsteer_resume)
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};
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static const struct of_device_id imx_irqsteer_dt_ids[] = {
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{ .compatible = "fsl,imx-irqsteer", },
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{},
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};
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static struct platform_driver imx_irqsteer_driver = {
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.driver = {
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.name = "imx-irqsteer",
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.of_match_table = imx_irqsteer_dt_ids,
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.pm = &imx_irqsteer_pm_ops,
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},
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.probe = imx_irqsteer_probe,
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.remove = imx_irqsteer_remove,
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};
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builtin_platform_driver(imx_irqsteer_driver);
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