2019-05-27 09:55:21 +03:00
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// SPDX-License-Identifier: GPL-2.0-only
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2017-04-07 11:06:36 +03:00
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/*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: Youlin.Pei <youlin.pei@mediatek.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/syscore_ops.h>
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#define CIRQ_ACK 0x40
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#define CIRQ_MASK_SET 0xc0
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#define CIRQ_MASK_CLR 0x100
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#define CIRQ_SENS_SET 0x180
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#define CIRQ_SENS_CLR 0x1c0
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#define CIRQ_POL_SET 0x240
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#define CIRQ_POL_CLR 0x280
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#define CIRQ_CONTROL 0x300
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#define CIRQ_EN 0x1
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#define CIRQ_EDGE 0x2
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#define CIRQ_FLUSH 0x4
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struct mtk_cirq_chip_data {
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void __iomem *base;
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unsigned int ext_irq_start;
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unsigned int ext_irq_end;
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struct irq_domain *domain;
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};
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static struct mtk_cirq_chip_data *cirq_data;
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static void mtk_cirq_write_mask(struct irq_data *data, unsigned int offset)
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{
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struct mtk_cirq_chip_data *chip_data = data->chip_data;
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unsigned int cirq_num = data->hwirq;
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u32 mask = 1 << (cirq_num % 32);
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writel_relaxed(mask, chip_data->base + offset + (cirq_num / 32) * 4);
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}
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static void mtk_cirq_mask(struct irq_data *data)
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{
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mtk_cirq_write_mask(data, CIRQ_MASK_SET);
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irq_chip_mask_parent(data);
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}
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static void mtk_cirq_unmask(struct irq_data *data)
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{
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mtk_cirq_write_mask(data, CIRQ_MASK_CLR);
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irq_chip_unmask_parent(data);
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}
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static int mtk_cirq_set_type(struct irq_data *data, unsigned int type)
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{
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int ret;
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_FALLING:
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mtk_cirq_write_mask(data, CIRQ_POL_CLR);
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mtk_cirq_write_mask(data, CIRQ_SENS_CLR);
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break;
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case IRQ_TYPE_EDGE_RISING:
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mtk_cirq_write_mask(data, CIRQ_POL_SET);
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mtk_cirq_write_mask(data, CIRQ_SENS_CLR);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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mtk_cirq_write_mask(data, CIRQ_POL_CLR);
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mtk_cirq_write_mask(data, CIRQ_SENS_SET);
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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mtk_cirq_write_mask(data, CIRQ_POL_SET);
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mtk_cirq_write_mask(data, CIRQ_SENS_SET);
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break;
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default:
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break;
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}
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data = data->parent_data;
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ret = data->chip->irq_set_type(data, type);
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return ret;
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}
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static struct irq_chip mtk_cirq_chip = {
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.name = "MT_CIRQ",
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.irq_mask = mtk_cirq_mask,
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.irq_unmask = mtk_cirq_unmask,
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.irq_eoi = irq_chip_eoi_parent,
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.irq_set_type = mtk_cirq_set_type,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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};
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static int mtk_cirq_domain_translate(struct irq_domain *d,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 3)
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return -EINVAL;
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/* No PPI should point to this domain */
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if (fwspec->param[0] != 0)
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return -EINVAL;
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/* cirq support irq number check */
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if (fwspec->param[1] < cirq_data->ext_irq_start ||
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fwspec->param[1] > cirq_data->ext_irq_end)
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return -EINVAL;
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*hwirq = fwspec->param[1] - cirq_data->ext_irq_start;
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*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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return -EINVAL;
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}
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static int mtk_cirq_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *arg)
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{
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int ret;
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irq_hw_number_t hwirq;
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unsigned int type;
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struct irq_fwspec *fwspec = arg;
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struct irq_fwspec parent_fwspec = *fwspec;
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ret = mtk_cirq_domain_translate(domain, fwspec, &hwirq, &type);
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if (ret)
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return ret;
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if (WARN_ON(nr_irqs != 1))
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return -EINVAL;
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irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
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&mtk_cirq_chip,
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domain->host_data);
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parent_fwspec.fwnode = domain->parent->fwnode;
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return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs,
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&parent_fwspec);
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}
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static const struct irq_domain_ops cirq_domain_ops = {
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.translate = mtk_cirq_domain_translate,
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.alloc = mtk_cirq_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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#ifdef CONFIG_PM_SLEEP
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static int mtk_cirq_suspend(void)
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{
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u32 value, mask;
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unsigned int irq, hwirq_num;
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bool pending, masked;
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int i, pendret, maskret;
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/*
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* When external interrupts happened, CIRQ will record the status
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* even CIRQ is not enabled. When execute flush command, CIRQ will
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* resend the signals according to the status. So if don't clear the
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* status, CIRQ will resend the wrong signals.
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*
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* arch_suspend_disable_irqs() will be called before CIRQ suspend
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* callback. If clear all the status simply, the external interrupts
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* which happened between arch_suspend_disable_irqs and CIRQ suspend
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* callback will be lost. Using following steps to avoid this issue;
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*
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* - Iterate over all the CIRQ supported interrupts;
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* - For each interrupt, inspect its pending and masked status at GIC
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* level;
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* - If pending and unmasked, it happened between
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* arch_suspend_disable_irqs and CIRQ suspend callback, don't ACK
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* it. Otherwise, ACK it.
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*/
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hwirq_num = cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1;
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for (i = 0; i < hwirq_num; i++) {
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irq = irq_find_mapping(cirq_data->domain, i);
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if (irq) {
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pendret = irq_get_irqchip_state(irq,
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IRQCHIP_STATE_PENDING,
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&pending);
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maskret = irq_get_irqchip_state(irq,
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IRQCHIP_STATE_MASKED,
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&masked);
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if (pendret == 0 && maskret == 0 &&
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(pending && !masked))
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continue;
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}
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mask = 1 << (i % 32);
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writel_relaxed(mask, cirq_data->base + CIRQ_ACK + (i / 32) * 4);
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}
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/* set edge_only mode, record edge-triggerd interrupts */
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/* enable cirq */
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value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
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value |= (CIRQ_EDGE | CIRQ_EN);
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writel_relaxed(value, cirq_data->base + CIRQ_CONTROL);
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return 0;
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}
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static void mtk_cirq_resume(void)
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{
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u32 value;
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2021-03-22 06:21:30 +03:00
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/* flush recorded interrupts, will send signals to parent controller */
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2017-04-07 11:06:36 +03:00
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value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
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writel_relaxed(value | CIRQ_FLUSH, cirq_data->base + CIRQ_CONTROL);
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/* disable cirq */
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value = readl_relaxed(cirq_data->base + CIRQ_CONTROL);
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value &= ~(CIRQ_EDGE | CIRQ_EN);
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writel_relaxed(value, cirq_data->base + CIRQ_CONTROL);
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}
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static struct syscore_ops mtk_cirq_syscore_ops = {
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.suspend = mtk_cirq_suspend,
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.resume = mtk_cirq_resume,
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};
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static void mtk_cirq_syscore_init(void)
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{
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register_syscore_ops(&mtk_cirq_syscore_ops);
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}
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#else
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static inline void mtk_cirq_syscore_init(void) {}
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#endif
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static int __init mtk_cirq_of_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *domain, *domain_parent;
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unsigned int irq_num;
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int ret;
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domain_parent = irq_find_host(parent);
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if (!domain_parent) {
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pr_err("mtk_cirq: interrupt-parent not found\n");
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return -EINVAL;
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}
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cirq_data = kzalloc(sizeof(*cirq_data), GFP_KERNEL);
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if (!cirq_data)
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return -ENOMEM;
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cirq_data->base = of_iomap(node, 0);
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if (!cirq_data->base) {
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pr_err("mtk_cirq: unable to map cirq register\n");
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ret = -ENXIO;
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goto out_free;
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}
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ret = of_property_read_u32_index(node, "mediatek,ext-irq-range", 0,
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&cirq_data->ext_irq_start);
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if (ret)
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goto out_unmap;
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ret = of_property_read_u32_index(node, "mediatek,ext-irq-range", 1,
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&cirq_data->ext_irq_end);
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if (ret)
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goto out_unmap;
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irq_num = cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1;
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domain = irq_domain_add_hierarchy(domain_parent, 0,
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irq_num, node,
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&cirq_domain_ops, cirq_data);
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if (!domain) {
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ret = -ENOMEM;
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goto out_unmap;
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}
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cirq_data->domain = domain;
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mtk_cirq_syscore_init();
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return 0;
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out_unmap:
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iounmap(cirq_data->base);
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out_free:
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kfree(cirq_data);
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return ret;
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}
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2020-08-25 12:38:39 +03:00
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IRQCHIP_DECLARE(mtk_cirq, "mediatek,mtk-cirq", mtk_cirq_of_init);
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