2019-06-04 11:11:33 +03:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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drm/exynos: added hdmi display support
This patch is hdmi display support for exynos drm driver.
There is already v4l2 based exynos hdmi driver in drivers/media/video/s5p-tv
and some low level code is already in s5p-tv and even headers for register
define are almost same. but in this patch, we decide not to consider separated
common code with s5p-tv.
Exynos HDMI is composed of 5 blocks, mixer, vp, hdmi, hdmiphy and ddc.
1. mixer. The piece of hardware responsible for mixing and blending multiple
data inputs before passing it to an output device. The mixer is capable of
handling up to three image layers. One is the output of VP. Other two are
images in RGB format. The blending factor, and layers' priority are controlled
by mixer's registers. The output is passed to HDMI.
2. vp (video processor). It is used for processing of NV12/NV21 data. An image
stored in RAM is accessed by DMA. The output in YCbCr444 format is send to
mixer.
3. hdmi. The piece of HW responsible for generation of HDMI packets. It takes
pixel data from mixer and transforms it into data frames. The output is send
to HDMIPHY interface.
4. hdmiphy. Physical interface for HDMI. Its duties are sending HDMI packets to
HDMI connector. Basically, it contains a PLL that produces source clock for
mixer, vp and hdmi.
5. ddc (display data channel). It is dedicated i2c channel to exchange display
information as edid with display monitor.
With plane support, exynos hdmi driver fully supports two mixer layes and vp
layer. Also vp layer supports multi buffer plane pixel formats having non
contigus memory spaces.
In exynos drm driver, common drm_hdmi driver to interface with drm framework
has opertion pointers for mixer and hdmi. this drm_hdmi driver is registered as
sub driver of exynos_drm. hdmi has hdmiphy and ddc i2c clients and controls
them. mixer controls all overlay layers in both mixer and vp.
Vblank interrupts for hdmi are handled by mixer internally because drm
framework cannot support multiple irq id. And pipe number is used to check
which display device irq happens.
History
v2: this version
- drm plane feature support to handle overlay layers.
- multi buffer plane pixel format support for vp layer.
- vp layer support
RFCv1: original
- at https://lkml.org/lkml/2011/11/4/164
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
2011-12-21 12:39:39 +04:00
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/*
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*
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* Cloned from drivers/media/video/s5p-tv/regs-vp.h
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* Video processor register header file for Samsung Mixer driver
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*/
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#ifndef SAMSUNG_REGS_VP_H
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#define SAMSUNG_REGS_VP_H
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/*
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* Register part
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*/
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#define VP_ENABLE 0x0000
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#define VP_SRESET 0x0004
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#define VP_SHADOW_UPDATE 0x0008
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#define VP_FIELD_ID 0x000C
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#define VP_MODE 0x0010
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#define VP_IMG_SIZE_Y 0x0014
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#define VP_IMG_SIZE_C 0x0018
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#define VP_PER_RATE_CTRL 0x001C
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#define VP_TOP_Y_PTR 0x0028
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#define VP_BOT_Y_PTR 0x002C
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#define VP_TOP_C_PTR 0x0030
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#define VP_BOT_C_PTR 0x0034
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#define VP_ENDIAN_MODE 0x03CC
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#define VP_SRC_H_POSITION 0x0044
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#define VP_SRC_V_POSITION 0x0048
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#define VP_SRC_WIDTH 0x004C
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#define VP_SRC_HEIGHT 0x0050
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#define VP_DST_H_POSITION 0x0054
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#define VP_DST_V_POSITION 0x0058
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#define VP_DST_WIDTH 0x005C
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#define VP_DST_HEIGHT 0x0060
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#define VP_H_RATIO 0x0064
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#define VP_V_RATIO 0x0068
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#define VP_POLY8_Y0_LL 0x006C
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#define VP_POLY4_Y0_LL 0x00EC
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#define VP_POLY4_C0_LL 0x012C
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/*
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* Bit definition part
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*/
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/* generates mask for range of bits */
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#define VP_MASK(high_bit, low_bit) \
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(((2 << ((high_bit) - (low_bit))) - 1) << (low_bit))
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#define VP_MASK_VAL(val, high_bit, low_bit) \
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(((val) << (low_bit)) & VP_MASK(high_bit, low_bit))
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/* VP_ENABLE */
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#define VP_ENABLE_ON (1 << 0)
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/* VP_SRESET */
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#define VP_SRESET_PROCESSING (1 << 0)
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/* VP_SHADOW_UPDATE */
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#define VP_SHADOW_UPDATE_ENABLE (1 << 0)
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/* VP_MODE */
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#define VP_MODE_NV12 (0 << 6)
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#define VP_MODE_NV21 (1 << 6)
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#define VP_MODE_LINE_SKIP (1 << 5)
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#define VP_MODE_MEM_LINEAR (0 << 4)
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#define VP_MODE_MEM_TILED (1 << 4)
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#define VP_MODE_FMT_MASK (5 << 4)
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#define VP_MODE_FIELD_ID_AUTO_TOGGLING (1 << 2)
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#define VP_MODE_2D_IPC (1 << 1)
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/* VP_IMG_SIZE_Y */
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/* VP_IMG_SIZE_C */
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#define VP_IMG_HSIZE(x) VP_MASK_VAL(x, 29, 16)
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#define VP_IMG_VSIZE(x) VP_MASK_VAL(x, 13, 0)
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/* VP_SRC_H_POSITION */
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#define VP_SRC_H_POSITION_VAL(x) VP_MASK_VAL(x, 14, 4)
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/* VP_ENDIAN_MODE */
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#define VP_ENDIAN_MODE_LITTLE (1 << 0)
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#endif /* SAMSUNG_REGS_VP_H */
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