2019-05-28 20:10:04 +03:00
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// SPDX-License-Identifier: GPL-2.0-only
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2012-10-31 13:41:17 +04:00
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/*
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* CPU complex suspend & resume functions for Tegra SoCs
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*
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* Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
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*/
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2014-07-11 11:44:49 +04:00
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#include <linux/clk/tegra.h>
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2012-10-31 13:41:17 +04:00
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#include <linux/cpumask.h>
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2012-10-31 13:41:21 +04:00
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#include <linux/cpu_pm.h>
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2014-07-11 11:44:49 +04:00
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#include <linux/delay.h>
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2012-10-31 13:41:21 +04:00
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#include <linux/err.h>
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2014-07-11 11:44:49 +04:00
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#include <linux/io.h>
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#include <linux/kernel.h>
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2014-01-29 03:10:37 +04:00
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#include <linux/slab.h>
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2014-07-11 11:44:49 +04:00
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#include <linux/spinlock.h>
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#include <linux/suspend.h>
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2012-10-31 13:41:21 +04:00
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2019-04-10 11:47:28 +03:00
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#include <linux/firmware/trusted_foundations.h>
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2017-03-28 15:42:54 +03:00
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#include <soc/tegra/flowctrl.h>
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2014-07-11 11:52:41 +04:00
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#include <soc/tegra/fuse.h>
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2014-07-11 15:19:06 +04:00
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#include <soc/tegra/pm.h>
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#include <soc/tegra/pmc.h>
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2014-07-11 11:52:41 +04:00
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2012-10-31 13:41:21 +04:00
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#include <asm/cacheflush.h>
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2019-03-18 01:52:10 +03:00
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#include <asm/firmware.h>
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2012-10-31 13:41:21 +04:00
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#include <asm/idmap.h>
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#include <asm/proc-fns.h>
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2014-07-11 11:44:49 +04:00
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#include <asm/smp_plat.h>
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#include <asm/suspend.h>
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2012-10-31 13:41:21 +04:00
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#include <asm/tlbflush.h>
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2012-10-31 13:41:17 +04:00
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2014-07-11 11:44:49 +04:00
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#include "iomap.h"
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#include "pm.h"
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#include "reset.h"
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2012-10-31 13:41:21 +04:00
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#include "sleep.h"
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2012-10-31 13:41:17 +04:00
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#ifdef CONFIG_PM_SLEEP
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static DEFINE_SPINLOCK(tegra_lp2_lock);
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2013-08-12 13:40:03 +04:00
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static u32 iram_save_size;
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static void *iram_save_addr;
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struct tegra_lp1_iram tegra_lp1_iram;
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2012-10-31 13:41:21 +04:00
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void (*tegra_tear_down_cpu)(void);
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2013-08-12 13:40:03 +04:00
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void (*tegra_sleep_core_finish)(unsigned long v2p);
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static int (*tegra_sleep_func)(unsigned long v2p);
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2012-10-31 13:41:17 +04:00
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2013-06-04 14:47:33 +04:00
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static void tegra_tear_down_cpu_init(void)
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{
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2014-07-11 11:52:41 +04:00
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switch (tegra_get_chip_id()) {
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2013-06-04 14:47:33 +04:00
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case TEGRA20:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
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tegra_tear_down_cpu = tegra20_tear_down_cpu;
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break;
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case TEGRA30:
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2013-07-03 13:50:42 +04:00
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case TEGRA114:
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2013-10-11 13:58:38 +04:00
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case TEGRA124:
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2013-07-03 13:50:42 +04:00
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
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2013-10-11 13:58:38 +04:00
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IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
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2013-06-04 14:47:33 +04:00
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tegra_tear_down_cpu = tegra30_tear_down_cpu;
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break;
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}
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}
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2012-10-31 13:41:21 +04:00
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/*
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* restore_cpu_complex
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*
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* restores cpu clock setting, clears flow controller
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*
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* Always called on CPU 0.
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*/
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static void restore_cpu_complex(void)
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{
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int cpu = smp_processor_id();
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BUG_ON(cpu != 0);
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#ifdef CONFIG_SMP
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cpu = cpu_logical_map(cpu);
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#endif
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/* Restore the CPU clock settings */
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tegra_cpu_clock_resume();
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flowctrl_cpu_suspend_exit(cpu);
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}
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/*
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* suspend_cpu_complex
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*
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* saves pll state for use by restart_plls, prepares flow controller for
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* transition to suspend state
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*
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* Must always be called on cpu 0.
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*/
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static void suspend_cpu_complex(void)
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{
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int cpu = smp_processor_id();
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BUG_ON(cpu != 0);
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#ifdef CONFIG_SMP
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cpu = cpu_logical_map(cpu);
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#endif
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/* Save the CPU clock settings */
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tegra_cpu_clock_suspend();
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flowctrl_cpu_suspend_enter(cpu);
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}
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2020-02-25 01:40:47 +03:00
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void tegra_pm_clear_cpu_in_lp2(void)
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2012-10-31 13:41:17 +04:00
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{
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2013-06-04 14:47:35 +04:00
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int phy_cpu_id = cpu_logical_map(smp_processor_id());
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2012-10-31 13:41:17 +04:00
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u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
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spin_lock(&tegra_lp2_lock);
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BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
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*cpu_in_lp2 &= ~BIT(phy_cpu_id);
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spin_unlock(&tegra_lp2_lock);
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}
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2020-02-25 01:40:47 +03:00
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void tegra_pm_set_cpu_in_lp2(void)
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2012-10-31 13:41:17 +04:00
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{
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2013-06-04 14:47:35 +04:00
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int phy_cpu_id = cpu_logical_map(smp_processor_id());
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2012-10-31 13:41:17 +04:00
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u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
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spin_lock(&tegra_lp2_lock);
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BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
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*cpu_in_lp2 |= BIT(phy_cpu_id);
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spin_unlock(&tegra_lp2_lock);
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}
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2012-10-31 13:41:21 +04:00
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static int tegra_sleep_cpu(unsigned long v2p)
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{
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2020-02-25 01:40:48 +03:00
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if (tegra_cpu_car_ops->rail_off_ready &&
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WARN_ON(!tegra_cpu_rail_off_ready()))
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return -EBUSY;
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2019-03-18 01:52:10 +03:00
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/*
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* L2 cache disabling using kernel API only allowed when all
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* secondary CPU's are offline. Cache have to be disabled with
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* MMU-on if cache maintenance is done via Trusted Foundations
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* firmware. Note that CPUIDLE won't ever enter powergate on Tegra30
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* if any of secondary CPU's is online and this is the LP2-idle
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* code-path only for Tegra20/30.
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*/
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2020-02-25 01:40:48 +03:00
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#ifdef CONFIG_OUTER_CACHE
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if (trusted_foundations_registered() && outer_cache.disable)
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outer_cache.disable();
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#endif
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2019-03-18 01:52:10 +03:00
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/*
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* Note that besides of setting up CPU reset vector this firmware
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* call may also do the following, depending on the FW version:
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* 1) Disable L2. But this doesn't matter since we already
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* disabled the L2.
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* 2) Disable D-cache. This need to be taken into account in
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* particular by the tegra_disable_clean_inv_dcache() which
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* shall avoid the re-disable.
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*/
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call_firmware_op(prepare_idle, TF_PM_MODE_LP2);
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2013-03-25 22:19:11 +04:00
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setup_mm_for_reboot();
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2012-10-31 13:41:21 +04:00
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tegra_sleep_cpu_finish(v2p);
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/* should never here */
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BUG();
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return 0;
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}
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2014-07-11 15:19:06 +04:00
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static void tegra_pm_set(enum tegra_suspend_mode mode)
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{
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u32 value;
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switch (tegra_get_chip_id()) {
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case TEGRA20:
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case TEGRA30:
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break;
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default:
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/* Turn off CRAIL */
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value = flowctrl_read_cpu_csr(0);
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value &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
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value |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
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flowctrl_write_cpu_csr(0, value);
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break;
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}
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tegra_pmc_enter_suspend_mode(mode);
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}
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2020-02-25 01:40:47 +03:00
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int tegra_pm_enter_lp2(void)
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2012-10-31 13:41:21 +04:00
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{
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2020-02-25 01:40:45 +03:00
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int err;
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2014-07-11 15:19:06 +04:00
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tegra_pm_set(TEGRA_SUSPEND_LP2);
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2012-10-31 13:41:21 +04:00
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cpu_cluster_pm_enter();
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suspend_cpu_complex();
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2020-02-25 01:40:45 +03:00
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err = cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
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2012-10-31 13:41:21 +04:00
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2019-03-18 01:52:10 +03:00
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/*
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* Resume L2 cache if it wasn't re-enabled early during resume,
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* which is the case for Tegra30 that has to re-enable the cache
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* via firmware call. In other cases cache is already enabled and
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* hence re-enabling is a no-op. This is always a no-op on Tegra114+.
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*/
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outer_resume();
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2012-10-31 13:41:21 +04:00
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restore_cpu_complex();
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cpu_cluster_pm_exit();
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2020-02-25 01:40:45 +03:00
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2020-03-25 01:43:34 +03:00
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call_firmware_op(prepare_idle, TF_PM_MODE_NONE);
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2020-02-25 01:40:45 +03:00
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return err;
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2012-10-31 13:41:21 +04:00
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}
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2013-04-03 15:31:47 +04:00
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enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
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enum tegra_suspend_mode mode)
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{
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/*
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2013-08-12 13:40:03 +04:00
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* The Tegra devices support suspending to LP1 or lower currently.
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2013-04-03 15:31:47 +04:00
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*/
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2013-08-12 13:40:03 +04:00
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if (mode > TEGRA_SUSPEND_LP1)
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return TEGRA_SUSPEND_LP1;
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2013-04-03 15:31:47 +04:00
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return mode;
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}
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2013-08-12 13:40:03 +04:00
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static int tegra_sleep_core(unsigned long v2p)
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{
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2019-03-18 01:52:10 +03:00
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/*
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* Cache have to be disabled with MMU-on if cache maintenance is done
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* via Trusted Foundations firmware. This is a no-op on Tegra114+.
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*/
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if (trusted_foundations_registered())
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outer_disable();
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call_firmware_op(prepare_idle, TF_PM_MODE_LP1);
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2013-08-12 13:40:03 +04:00
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setup_mm_for_reboot();
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tegra_sleep_core_finish(v2p);
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/* should never here */
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BUG();
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return 0;
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}
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/*
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* tegra_lp1_iram_hook
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*
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* Hooking the address of LP1 reset vector and SDRAM self-refresh code in
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* SDRAM. These codes not be copied to IRAM in this fuction. We need to
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* copy these code to IRAM before LP0/LP1 suspend and restore the content
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* of IRAM after resume.
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*/
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static bool tegra_lp1_iram_hook(void)
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{
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2014-07-11 11:52:41 +04:00
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switch (tegra_get_chip_id()) {
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2013-08-12 13:40:05 +04:00
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case TEGRA20:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
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tegra20_lp1_iram_hook();
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break;
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ARM: tegra: add LP1 suspend support for Tegra30
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail
The sequence of LP1 resuming:
* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41
Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored, CCLK burst policy be set in PLLX. Then jumping to
"tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore
CPU context and back to kernel.
Based on the work by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 13:40:04 +04:00
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case TEGRA30:
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ARM: tegra: add LP1 suspend support for Tegra114
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail
The sequence of LP1 resuming:
* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41
Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored. Then jumping to "tegra_resume" that was expected to be stored
in PMC_SCRATCH41 to restore CPU context and back to kernel.
Based on the work by: Bo Yan <byan@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 13:40:06 +04:00
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case TEGRA114:
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2013-10-11 13:58:38 +04:00
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case TEGRA124:
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ARM: tegra: add LP1 suspend support for Tegra114
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail
The sequence of LP1 resuming:
* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41
Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored. Then jumping to "tegra_resume" that was expected to be stored
in PMC_SCRATCH41 to restore CPU context and back to kernel.
Based on the work by: Bo Yan <byan@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 13:40:06 +04:00
|
|
|
if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
|
2013-10-11 13:58:38 +04:00
|
|
|
IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
|
|
|
|
IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
|
ARM: tegra: add LP1 suspend support for Tegra30
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail
The sequence of LP1 resuming:
* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41
Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored, CCLK burst policy be set in PLLX. Then jumping to
"tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore
CPU context and back to kernel.
Based on the work by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 13:40:04 +04:00
|
|
|
tegra30_lp1_iram_hook();
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2013-08-12 13:40:03 +04:00
|
|
|
if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;
|
|
|
|
iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL);
|
|
|
|
if (!iram_save_addr)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool tegra_sleep_core_init(void)
|
|
|
|
{
|
2014-07-11 11:52:41 +04:00
|
|
|
switch (tegra_get_chip_id()) {
|
2013-08-12 13:40:05 +04:00
|
|
|
case TEGRA20:
|
|
|
|
if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
|
|
|
|
tegra20_sleep_core_init();
|
|
|
|
break;
|
ARM: tegra: add LP1 suspend support for Tegra30
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail
The sequence of LP1 resuming:
* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41
Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored, CCLK burst policy be set in PLLX. Then jumping to
"tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore
CPU context and back to kernel.
Based on the work by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 13:40:04 +04:00
|
|
|
case TEGRA30:
|
ARM: tegra: add LP1 suspend support for Tegra114
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail
The sequence of LP1 resuming:
* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41
Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored. Then jumping to "tegra_resume" that was expected to be stored
in PMC_SCRATCH41 to restore CPU context and back to kernel.
Based on the work by: Bo Yan <byan@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 13:40:06 +04:00
|
|
|
case TEGRA114:
|
2013-10-11 13:58:38 +04:00
|
|
|
case TEGRA124:
|
ARM: tegra: add LP1 suspend support for Tegra114
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail
The sequence of LP1 resuming:
* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41
Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored. Then jumping to "tegra_resume" that was expected to be stored
in PMC_SCRATCH41 to restore CPU context and back to kernel.
Based on the work by: Bo Yan <byan@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 13:40:06 +04:00
|
|
|
if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
|
2013-10-11 13:58:38 +04:00
|
|
|
IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
|
|
|
|
IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
|
ARM: tegra: add LP1 suspend support for Tegra30
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put
SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The
sequence when LP1 suspending:
* tunning off L1 data cache and the MMU
* storing some EMC registers, DPD (deep power down) status, clk source of
mselect and SCLK burst policy
* putting SDRAM into self-refresh
* switching CPU to CLK_M (12MHz OSC)
* tunning off PLLM, PLLP, PLLA, PLLC and PLLX
* switching SCLK to CLK_S (32KHz OSC)
* shutting off the CPU rail
The sequence of LP1 resuming:
* re-enabling PLLM, PLLP, PLLA, PLLC and PLLX
* restoring the clk source of mselect and SCLK burst policy
* setting up CCLK burst policy to PLLX
* restoring DPD status and some EMC registers
* resuming SDRAM to normal mode
* jumping to the "tegra_resume" from PMC_SCRATCH41
Due to the SDRAM will be put into self-refresh mode, the low level
procedures of LP1 suspending and resuming should be copied to
TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before
restoring the CPU context when resuming, the SDRAM needs to be switched
back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy
be restored, CCLK burst policy be set in PLLX. Then jumping to
"tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore
CPU context and back to kernel.
Based on the work by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2013-08-12 13:40:04 +04:00
|
|
|
tegra30_sleep_core_init();
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2013-08-12 13:40:03 +04:00
|
|
|
if (!tegra_sleep_core_finish)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_suspend_enter_lp1(void)
|
|
|
|
{
|
|
|
|
/* copy the reset vector & SDRAM shutdown code into IRAM */
|
2013-08-21 02:19:15 +04:00
|
|
|
memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
|
2013-08-12 13:40:03 +04:00
|
|
|
iram_save_size);
|
2013-08-21 02:19:15 +04:00
|
|
|
memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
|
|
|
|
tegra_lp1_iram.start_addr, iram_save_size);
|
2013-08-12 13:40:03 +04:00
|
|
|
|
|
|
|
*((u32 *)tegra_cpu_lp1_mask) = 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tegra_suspend_exit_lp1(void)
|
|
|
|
{
|
|
|
|
/* restore IRAM */
|
2013-08-21 02:19:15 +04:00
|
|
|
memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr,
|
2013-08-12 13:40:03 +04:00
|
|
|
iram_save_size);
|
|
|
|
|
|
|
|
*(u32 *)tegra_cpu_lp1_mask = 0;
|
|
|
|
}
|
|
|
|
|
2013-04-03 15:31:47 +04:00
|
|
|
static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
|
|
|
|
[TEGRA_SUSPEND_NONE] = "none",
|
|
|
|
[TEGRA_SUSPEND_LP2] = "LP2",
|
|
|
|
[TEGRA_SUSPEND_LP1] = "LP1",
|
|
|
|
[TEGRA_SUSPEND_LP0] = "LP0",
|
|
|
|
};
|
|
|
|
|
2013-06-17 23:43:14 +04:00
|
|
|
static int tegra_suspend_enter(suspend_state_t state)
|
2013-04-03 15:31:47 +04:00
|
|
|
{
|
|
|
|
enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
|
|
|
|
|
|
|
|
if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
|
|
|
|
mode >= TEGRA_MAX_SUSPEND_MODE))
|
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
pr_info("Entering suspend state %s\n", lp_state[mode]);
|
|
|
|
|
2014-07-11 15:19:06 +04:00
|
|
|
tegra_pm_set(mode);
|
2013-04-03 15:31:47 +04:00
|
|
|
|
|
|
|
local_fiq_disable();
|
|
|
|
|
|
|
|
suspend_cpu_complex();
|
|
|
|
switch (mode) {
|
2013-08-12 13:40:03 +04:00
|
|
|
case TEGRA_SUSPEND_LP1:
|
|
|
|
tegra_suspend_enter_lp1();
|
|
|
|
break;
|
2013-04-03 15:31:47 +04:00
|
|
|
case TEGRA_SUSPEND_LP2:
|
2020-02-25 01:40:47 +03:00
|
|
|
tegra_pm_set_cpu_in_lp2();
|
2013-04-03 15:31:47 +04:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2013-08-12 13:40:03 +04:00
|
|
|
cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
|
2013-04-03 15:31:47 +04:00
|
|
|
|
2019-03-18 01:52:10 +03:00
|
|
|
/*
|
|
|
|
* Resume L2 cache if it wasn't re-enabled early during resume,
|
|
|
|
* which is the case for Tegra30 that has to re-enable the cache
|
|
|
|
* via firmware call. In other cases cache is already enabled and
|
|
|
|
* hence re-enabling is a no-op.
|
|
|
|
*/
|
|
|
|
outer_resume();
|
|
|
|
|
2013-04-03 15:31:47 +04:00
|
|
|
switch (mode) {
|
2013-08-12 13:40:03 +04:00
|
|
|
case TEGRA_SUSPEND_LP1:
|
|
|
|
tegra_suspend_exit_lp1();
|
|
|
|
break;
|
2013-04-03 15:31:47 +04:00
|
|
|
case TEGRA_SUSPEND_LP2:
|
2020-02-25 01:40:47 +03:00
|
|
|
tegra_pm_clear_cpu_in_lp2();
|
2013-04-03 15:31:47 +04:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
restore_cpu_complex();
|
|
|
|
|
|
|
|
local_fiq_enable();
|
|
|
|
|
2020-03-25 01:43:34 +03:00
|
|
|
call_firmware_op(prepare_idle, TF_PM_MODE_NONE);
|
|
|
|
|
2013-04-03 15:31:47 +04:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct platform_suspend_ops tegra_suspend_ops = {
|
|
|
|
.valid = suspend_valid_only_mem,
|
|
|
|
.enter = tegra_suspend_enter,
|
|
|
|
};
|
|
|
|
|
2021-07-19 00:27:05 +03:00
|
|
|
void tegra_pm_init_suspend(void)
|
2013-04-03 15:31:47 +04:00
|
|
|
{
|
2013-08-12 13:40:03 +04:00
|
|
|
enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
|
|
|
|
|
|
|
|
if (mode == TEGRA_SUSPEND_NONE)
|
2013-04-03 15:31:47 +04:00
|
|
|
return;
|
|
|
|
|
2013-06-04 14:47:33 +04:00
|
|
|
tegra_tear_down_cpu_init();
|
2013-04-03 15:31:47 +04:00
|
|
|
|
2013-08-12 13:40:03 +04:00
|
|
|
if (mode >= TEGRA_SUSPEND_LP1) {
|
|
|
|
if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) {
|
|
|
|
pr_err("%s: unable to allocate memory for SDRAM"
|
|
|
|
"self-refresh -- LP0/LP1 unavailable\n",
|
|
|
|
__func__);
|
|
|
|
tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2);
|
|
|
|
mode = TEGRA_SUSPEND_LP2;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* set up sleep function for cpu_suspend */
|
|
|
|
switch (mode) {
|
|
|
|
case TEGRA_SUSPEND_LP1:
|
|
|
|
tegra_sleep_func = tegra_sleep_core;
|
|
|
|
break;
|
|
|
|
case TEGRA_SUSPEND_LP2:
|
|
|
|
tegra_sleep_func = tegra_sleep_cpu;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2013-04-03 15:31:47 +04:00
|
|
|
suspend_set_ops(&tegra_suspend_ops);
|
|
|
|
}
|
2020-02-25 01:40:42 +03:00
|
|
|
|
|
|
|
int tegra_pm_park_secondary_cpu(unsigned long cpu)
|
|
|
|
{
|
|
|
|
if (cpu > 0) {
|
|
|
|
tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS);
|
|
|
|
|
|
|
|
if (tegra_get_chip_id() == TEGRA20)
|
|
|
|
tegra20_hotplug_shutdown();
|
|
|
|
else
|
|
|
|
tegra30_hotplug_shutdown();
|
|
|
|
}
|
|
|
|
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
2012-10-31 13:41:17 +04:00
|
|
|
#endif
|