2018-11-06 15:11:42 +03:00
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// SPDX-License-Identifier: GPL-2.0
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2010-10-28 02:33:21 +04:00
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/*
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2011-10-28 04:23:33 +04:00
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* Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
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2010-10-28 02:33:21 +04:00
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*/
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2020-04-14 20:48:57 +03:00
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#include <linux/bits.h>
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2018-05-24 15:29:30 +03:00
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#include <linux/gpio/driver.h>
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2011-07-21 04:19:59 +04:00
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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2018-09-04 14:26:25 +03:00
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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2014-05-27 17:15:21 +04:00
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#include <linux/slab.h>
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2011-07-21 04:19:59 +04:00
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#define PCH_EDGE_FALLING 0
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2020-04-14 20:48:57 +03:00
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#define PCH_EDGE_RISING 1
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#define PCH_LEVEL_L 2
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#define PCH_LEVEL_H 3
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#define PCH_EDGE_BOTH 4
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#define PCH_IM_MASK GENMASK(2, 0)
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2011-07-21 04:19:59 +04:00
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#define PCH_IRQ_BASE 24
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2010-10-28 02:33:21 +04:00
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struct pch_regs {
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u32 ien;
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u32 istatus;
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u32 idisp;
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u32 iclr;
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u32 imask;
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u32 imaskclr;
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u32 po;
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u32 pi;
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u32 pm;
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u32 im0;
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u32 im1;
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2011-07-21 04:19:58 +04:00
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u32 reserved[3];
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u32 gpio_use_sel;
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2010-10-28 02:33:21 +04:00
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u32 reset;
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};
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2011-07-21 04:19:57 +04:00
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enum pch_type_t {
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INTEL_EG20T_PCH,
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2011-10-28 04:23:33 +04:00
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OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
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OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */
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2011-07-21 04:19:57 +04:00
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};
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/* Specifies number of GPIO PINS */
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static int gpio_pins[] = {
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[INTEL_EG20T_PCH] = 12,
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[OKISEMI_ML7223m_IOH] = 8,
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[OKISEMI_ML7223n_IOH] = 8,
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};
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2010-10-28 02:33:21 +04:00
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/**
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* struct pch_gpio_reg_data - The register store data.
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2011-07-21 04:19:59 +04:00
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* @ien_reg: To store contents of IEN register.
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* @imask_reg: To store contents of IMASK register.
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2010-10-28 02:33:21 +04:00
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* @po_reg: To store contents of PO register.
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* @pm_reg: To store contents of PM register.
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2011-07-21 04:19:58 +04:00
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* @im0_reg: To store contents of IM0 register.
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* @im1_reg: To store contents of IM1 register.
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* @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register.
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* (Only ML7223 Bus-n)
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2010-10-28 02:33:21 +04:00
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*/
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struct pch_gpio_reg_data {
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2011-07-21 04:19:59 +04:00
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u32 ien_reg;
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u32 imask_reg;
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2010-10-28 02:33:21 +04:00
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u32 po_reg;
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u32 pm_reg;
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2011-07-21 04:19:58 +04:00
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u32 im0_reg;
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u32 im1_reg;
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u32 gpio_use_sel_reg;
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2010-10-28 02:33:21 +04:00
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};
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/**
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* struct pch_gpio - GPIO private data structure.
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* @base: PCI base address of Memory mapped I/O register.
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* @reg: Memory mapped PCH GPIO register list.
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* @dev: Pointer to device structure.
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* @gpio: Data for GPIO infrastructure.
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* @pch_gpio_reg: Memory mapped Register data is saved here
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* when suspend.
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2011-07-21 04:19:59 +04:00
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* @lock: Used for register access protection
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* @irq_base: Save base of IRQ number for interrupt
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2011-07-21 04:19:57 +04:00
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* @ioh: IOH ID
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2012-07-29 06:55:54 +04:00
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* @spinlock: Used for register access protection
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2010-10-28 02:33:21 +04:00
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*/
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struct pch_gpio {
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void __iomem *base;
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struct pch_regs __iomem *reg;
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struct device *dev;
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struct gpio_chip gpio;
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struct pch_gpio_reg_data pch_gpio_reg;
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2011-07-21 04:19:59 +04:00
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int irq_base;
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2011-07-21 04:19:57 +04:00
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enum pch_type_t ioh;
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2011-07-21 04:19:55 +04:00
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spinlock_t spinlock;
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2010-10-28 02:33:21 +04:00
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};
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2020-07-21 17:50:45 +03:00
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static void pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val)
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2010-10-28 02:33:21 +04:00
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{
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u32 reg_val;
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2015-12-07 13:34:53 +03:00
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struct pch_gpio *chip = gpiochip_get_data(gpio);
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2012-07-29 06:55:54 +04:00
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unsigned long flags;
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2010-10-28 02:33:21 +04:00
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2012-07-29 06:55:54 +04:00
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spin_lock_irqsave(&chip->spinlock, flags);
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2010-10-28 02:33:21 +04:00
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reg_val = ioread32(&chip->reg->po);
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if (val)
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2020-04-14 20:48:57 +03:00
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reg_val |= BIT(nr);
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2010-10-28 02:33:21 +04:00
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else
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2020-04-14 20:48:57 +03:00
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reg_val &= ~BIT(nr);
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2010-10-28 02:33:21 +04:00
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iowrite32(reg_val, &chip->reg->po);
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2012-07-29 06:55:54 +04:00
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spin_unlock_irqrestore(&chip->spinlock, flags);
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2010-10-28 02:33:21 +04:00
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}
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2020-07-21 17:50:45 +03:00
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static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr)
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2010-10-28 02:33:21 +04:00
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{
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2015-12-07 13:34:53 +03:00
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struct pch_gpio *chip = gpiochip_get_data(gpio);
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2010-10-28 02:33:21 +04:00
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2020-04-14 20:48:57 +03:00
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return !!(ioread32(&chip->reg->pi) & BIT(nr));
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2010-10-28 02:33:21 +04:00
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}
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2020-07-21 17:50:45 +03:00
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static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr,
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2010-10-28 02:33:21 +04:00
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int val)
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{
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2015-12-07 13:34:53 +03:00
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struct pch_gpio *chip = gpiochip_get_data(gpio);
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2010-10-28 02:33:21 +04:00
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u32 pm;
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u32 reg_val;
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2012-07-29 06:55:54 +04:00
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unsigned long flags;
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2010-10-28 02:33:21 +04:00
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2012-07-29 06:55:54 +04:00
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spin_lock_irqsave(&chip->spinlock, flags);
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2010-10-28 02:33:21 +04:00
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reg_val = ioread32(&chip->reg->po);
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if (val)
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2020-04-14 20:48:57 +03:00
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reg_val |= BIT(nr);
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2010-10-28 02:33:21 +04:00
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else
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2020-04-14 20:48:57 +03:00
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reg_val &= ~BIT(nr);
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2011-03-25 18:04:00 +03:00
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iowrite32(reg_val, &chip->reg->po);
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2014-03-25 13:32:47 +04:00
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2020-04-14 20:48:57 +03:00
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pm = ioread32(&chip->reg->pm);
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pm &= BIT(gpio_pins[chip->ioh]) - 1;
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pm |= BIT(nr);
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2014-03-25 13:32:47 +04:00
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iowrite32(pm, &chip->reg->pm);
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2012-07-29 06:55:54 +04:00
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spin_unlock_irqrestore(&chip->spinlock, flags);
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2010-10-28 02:33:21 +04:00
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return 0;
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}
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2020-07-21 17:50:45 +03:00
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static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr)
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2010-10-28 02:33:21 +04:00
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{
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2015-12-07 13:34:53 +03:00
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struct pch_gpio *chip = gpiochip_get_data(gpio);
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2010-10-28 02:33:21 +04:00
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u32 pm;
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2012-07-29 06:55:54 +04:00
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unsigned long flags;
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2010-10-28 02:33:21 +04:00
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2012-07-29 06:55:54 +04:00
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spin_lock_irqsave(&chip->spinlock, flags);
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2020-04-14 20:48:57 +03:00
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pm = ioread32(&chip->reg->pm);
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pm &= BIT(gpio_pins[chip->ioh]) - 1;
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pm &= ~BIT(nr);
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2010-10-28 02:33:21 +04:00
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iowrite32(pm, &chip->reg->pm);
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2012-07-29 06:55:54 +04:00
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spin_unlock_irqrestore(&chip->spinlock, flags);
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2010-10-28 02:33:21 +04:00
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return 0;
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}
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/*
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* Save register configuration and disable interrupts.
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*/
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2018-11-07 22:19:45 +03:00
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static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip)
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2010-10-28 02:33:21 +04:00
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{
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2011-07-21 04:19:59 +04:00
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chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien);
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chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask);
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2010-10-28 02:33:21 +04:00
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chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po);
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chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm);
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2011-07-21 04:19:58 +04:00
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chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0);
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if (chip->ioh == INTEL_EG20T_PCH)
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chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1);
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if (chip->ioh == OKISEMI_ML7223n_IOH)
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2018-11-07 22:19:45 +03:00
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chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel);
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2010-10-28 02:33:21 +04:00
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}
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/*
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* This function restores the register configuration of the GPIO device.
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*/
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2018-11-07 22:19:45 +03:00
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static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip)
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2010-10-28 02:33:21 +04:00
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{
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2011-07-21 04:19:59 +04:00
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iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien);
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iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask);
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2010-10-28 02:33:21 +04:00
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/* to store contents of PO register */
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iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po);
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/* to store contents of PM register */
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iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm);
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2011-07-21 04:19:58 +04:00
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iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0);
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if (chip->ioh == INTEL_EG20T_PCH)
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iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1);
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if (chip->ioh == OKISEMI_ML7223n_IOH)
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2018-11-07 22:19:45 +03:00
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iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel);
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2010-10-28 02:33:21 +04:00
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}
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2020-07-21 17:50:45 +03:00
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static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned int offset)
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2011-07-21 04:19:59 +04:00
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{
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2015-12-07 13:34:53 +03:00
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struct pch_gpio *chip = gpiochip_get_data(gpio);
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2020-07-21 17:50:46 +03:00
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2011-07-21 04:19:59 +04:00
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return chip->irq_base + offset;
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}
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2010-10-28 02:33:21 +04:00
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static void pch_gpio_setup(struct pch_gpio *chip)
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{
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struct gpio_chip *gpio = &chip->gpio;
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gpio->label = dev_name(chip->dev);
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2015-11-04 11:56:26 +03:00
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gpio->parent = chip->dev;
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2010-10-28 02:33:21 +04:00
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gpio->owner = THIS_MODULE;
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gpio->direction_input = pch_gpio_direction_input;
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gpio->get = pch_gpio_get;
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gpio->direction_output = pch_gpio_direction_output;
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gpio->set = pch_gpio_set;
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gpio->base = -1;
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2011-07-21 04:19:57 +04:00
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gpio->ngpio = gpio_pins[chip->ioh];
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2013-12-04 17:42:46 +04:00
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gpio->can_sleep = false;
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2011-07-21 04:19:59 +04:00
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gpio->to_irq = pch_gpio_to_irq;
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}
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static int pch_irq_type(struct irq_data *d, unsigned int type)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct pch_gpio *chip = gc->private;
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2012-04-28 12:13:45 +04:00
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u32 im, im_pos, val;
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u32 __iomem *im_reg;
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unsigned long flags;
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int ch, irq = d->irq;
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2011-07-21 04:19:59 +04:00
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ch = irq - chip->irq_base;
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2020-04-14 20:48:59 +03:00
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if (irq < chip->irq_base + 8) {
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2011-07-21 04:19:59 +04:00
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im_reg = &chip->reg->im0;
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2020-04-14 20:48:59 +03:00
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im_pos = ch - 0;
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2011-07-21 04:19:59 +04:00
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} else {
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im_reg = &chip->reg->im1;
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im_pos = ch - 8;
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}
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2018-12-07 18:33:07 +03:00
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dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos);
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2011-07-21 04:19:59 +04:00
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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val = PCH_EDGE_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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val = PCH_EDGE_FALLING;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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val = PCH_EDGE_BOTH;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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val = PCH_LEVEL_H;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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val = PCH_LEVEL_L;
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break;
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default:
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2020-04-14 20:48:59 +03:00
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return 0;
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2011-07-21 04:19:59 +04:00
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}
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2020-04-14 20:48:59 +03:00
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spin_lock_irqsave(&chip->spinlock, flags);
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2011-07-21 04:19:59 +04:00
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/* Set interrupt mode */
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im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4));
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iowrite32(im | (val << (im_pos * 4)), im_reg);
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2012-04-28 12:13:45 +04:00
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/* And the handler */
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2020-04-14 20:49:00 +03:00
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if (type & IRQ_TYPE_LEVEL_MASK)
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2015-06-23 16:52:40 +03:00
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irq_set_handler_locked(d, handle_level_irq);
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2020-04-14 20:49:00 +03:00
|
|
|
else if (type & IRQ_TYPE_EDGE_BOTH)
|
2015-06-23 16:52:40 +03:00
|
|
|
irq_set_handler_locked(d, handle_edge_irq);
|
2011-07-21 04:19:59 +04:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&chip->spinlock, flags);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pch_irq_unmask(struct irq_data *d)
|
|
|
|
{
|
|
|
|
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
|
|
|
struct pch_gpio *chip = gc->private;
|
|
|
|
|
2020-04-14 20:48:57 +03:00
|
|
|
iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr);
|
2011-07-21 04:19:59 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pch_irq_mask(struct irq_data *d)
|
|
|
|
{
|
|
|
|
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
|
|
|
struct pch_gpio *chip = gc->private;
|
|
|
|
|
2020-04-14 20:48:57 +03:00
|
|
|
iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask);
|
2011-07-21 04:19:59 +04:00
|
|
|
}
|
|
|
|
|
2012-04-28 12:13:45 +04:00
|
|
|
static void pch_irq_ack(struct irq_data *d)
|
|
|
|
{
|
|
|
|
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
|
|
|
|
struct pch_gpio *chip = gc->private;
|
|
|
|
|
2020-04-14 20:48:57 +03:00
|
|
|
iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr);
|
2012-04-28 12:13:45 +04:00
|
|
|
}
|
|
|
|
|
2011-07-21 04:19:59 +04:00
|
|
|
static irqreturn_t pch_gpio_handler(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct pch_gpio *chip = dev_id;
|
2018-11-06 15:38:55 +03:00
|
|
|
unsigned long reg_val = ioread32(&chip->reg->istatus);
|
2020-04-14 20:48:58 +03:00
|
|
|
int i;
|
2011-07-21 04:19:59 +04:00
|
|
|
|
2020-07-01 18:20:46 +03:00
|
|
|
dev_vdbg(chip->dev, "irq=%d status=0x%lx\n", irq, reg_val);
|
2020-04-14 20:48:58 +03:00
|
|
|
|
|
|
|
reg_val &= BIT(gpio_pins[chip->ioh]) - 1;
|
2020-07-01 18:20:46 +03:00
|
|
|
|
2020-04-14 20:48:58 +03:00
|
|
|
for_each_set_bit(i, ®_val, gpio_pins[chip->ioh])
|
2018-11-06 15:38:55 +03:00
|
|
|
generic_handle_irq(chip->irq_base + i);
|
2020-04-14 20:48:58 +03:00
|
|
|
|
|
|
|
return IRQ_RETVAL(reg_val);
|
2011-07-21 04:19:59 +04:00
|
|
|
}
|
|
|
|
|
2017-05-25 11:37:36 +03:00
|
|
|
static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip,
|
|
|
|
unsigned int irq_start,
|
|
|
|
unsigned int num)
|
2011-07-21 04:19:59 +04:00
|
|
|
{
|
|
|
|
struct irq_chip_generic *gc;
|
|
|
|
struct irq_chip_type *ct;
|
2017-08-09 15:25:05 +03:00
|
|
|
int rv;
|
2011-07-21 04:19:59 +04:00
|
|
|
|
2017-08-09 15:25:05 +03:00
|
|
|
gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start,
|
|
|
|
chip->base, handle_simple_irq);
|
2017-05-25 11:37:36 +03:00
|
|
|
if (!gc)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2011-07-21 04:19:59 +04:00
|
|
|
gc->private = chip;
|
|
|
|
ct = gc->chip_types;
|
|
|
|
|
2012-04-28 12:13:45 +04:00
|
|
|
ct->chip.irq_ack = pch_irq_ack;
|
2011-07-21 04:19:59 +04:00
|
|
|
ct->chip.irq_mask = pch_irq_mask;
|
|
|
|
ct->chip.irq_unmask = pch_irq_unmask;
|
|
|
|
ct->chip.irq_set_type = pch_irq_type;
|
|
|
|
|
2017-08-09 15:25:05 +03:00
|
|
|
rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
|
|
|
|
IRQ_GC_INIT_MASK_CACHE,
|
|
|
|
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
|
2017-05-25 11:37:36 +03:00
|
|
|
|
2017-08-09 15:25:05 +03:00
|
|
|
return rv;
|
2010-10-28 02:33:21 +04:00
|
|
|
}
|
|
|
|
|
2012-11-19 22:22:34 +04:00
|
|
|
static int pch_gpio_probe(struct pci_dev *pdev,
|
2010-10-28 02:33:21 +04:00
|
|
|
const struct pci_device_id *id)
|
|
|
|
{
|
|
|
|
s32 ret;
|
|
|
|
struct pch_gpio *chip;
|
2011-07-21 04:19:59 +04:00
|
|
|
int irq_base;
|
2010-10-28 02:33:21 +04:00
|
|
|
|
2018-11-07 22:18:04 +03:00
|
|
|
chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
|
2010-10-28 02:33:21 +04:00
|
|
|
if (chip == NULL)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
chip->dev = &pdev->dev;
|
2018-11-07 22:18:04 +03:00
|
|
|
ret = pcim_enable_device(pdev);
|
2010-10-28 02:33:21 +04:00
|
|
|
if (ret) {
|
2018-12-07 18:33:07 +03:00
|
|
|
dev_err(&pdev->dev, "pci_enable_device FAILED");
|
2018-11-07 22:18:04 +03:00
|
|
|
return ret;
|
2010-10-28 02:33:21 +04:00
|
|
|
}
|
|
|
|
|
2020-04-14 20:48:57 +03:00
|
|
|
ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
|
2010-10-28 02:33:21 +04:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "pci_request_regions FAILED-%d", ret);
|
2018-11-07 22:18:04 +03:00
|
|
|
return ret;
|
2010-10-28 02:33:21 +04:00
|
|
|
}
|
|
|
|
|
2018-11-07 22:18:04 +03:00
|
|
|
chip->base = pcim_iomap_table(pdev)[1];
|
2010-10-28 02:33:21 +04:00
|
|
|
|
2011-07-21 04:19:57 +04:00
|
|
|
if (pdev->device == 0x8803)
|
|
|
|
chip->ioh = INTEL_EG20T_PCH;
|
|
|
|
else if (pdev->device == 0x8014)
|
|
|
|
chip->ioh = OKISEMI_ML7223m_IOH;
|
|
|
|
else if (pdev->device == 0x8043)
|
|
|
|
chip->ioh = OKISEMI_ML7223n_IOH;
|
|
|
|
|
2010-10-28 02:33:21 +04:00
|
|
|
chip->reg = chip->base;
|
|
|
|
pci_set_drvdata(pdev, chip);
|
2012-02-01 06:51:53 +04:00
|
|
|
spin_lock_init(&chip->spinlock);
|
2010-10-28 02:33:21 +04:00
|
|
|
pch_gpio_setup(chip);
|
2018-11-07 22:29:53 +03:00
|
|
|
|
2018-11-07 22:18:04 +03:00
|
|
|
ret = devm_gpiochip_add_data(&pdev->dev, &chip->gpio, chip);
|
2010-10-28 02:33:21 +04:00
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "PCH gpio: Failed to register GPIO\n");
|
2018-11-07 22:18:04 +03:00
|
|
|
return ret;
|
2010-10-28 02:33:21 +04:00
|
|
|
}
|
|
|
|
|
2017-03-04 19:23:32 +03:00
|
|
|
irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0,
|
|
|
|
gpio_pins[chip->ioh], NUMA_NO_NODE);
|
2011-07-21 04:19:59 +04:00
|
|
|
if (irq_base < 0) {
|
|
|
|
dev_warn(&pdev->dev, "PCH gpio: Failed to get IRQ base num\n");
|
|
|
|
chip->irq_base = -1;
|
2018-11-07 22:18:04 +03:00
|
|
|
return 0;
|
2011-07-21 04:19:59 +04:00
|
|
|
}
|
|
|
|
chip->irq_base = irq_base;
|
|
|
|
|
2012-04-28 12:13:45 +04:00
|
|
|
/* Mask all interrupts, but enable them */
|
2020-04-14 20:48:57 +03:00
|
|
|
iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask);
|
|
|
|
iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien);
|
2012-04-28 12:13:45 +04:00
|
|
|
|
2017-03-04 19:23:32 +03:00
|
|
|
ret = devm_request_irq(&pdev->dev, pdev->irq, pch_gpio_handler,
|
|
|
|
IRQF_SHARED, KBUILD_MODNAME, chip);
|
2018-11-07 22:18:04 +03:00
|
|
|
if (ret) {
|
2018-12-07 18:33:07 +03:00
|
|
|
dev_err(&pdev->dev, "request_irq failed\n");
|
2018-11-07 22:18:04 +03:00
|
|
|
return ret;
|
2011-07-21 04:19:59 +04:00
|
|
|
}
|
|
|
|
|
2018-11-07 22:18:04 +03:00
|
|
|
return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
|
2010-10-28 02:33:21 +04:00
|
|
|
}
|
|
|
|
|
2018-11-07 22:19:45 +03:00
|
|
|
static int __maybe_unused pch_gpio_suspend(struct device *dev)
|
2010-10-28 02:33:21 +04:00
|
|
|
{
|
2019-07-23 11:39:24 +03:00
|
|
|
struct pch_gpio *chip = dev_get_drvdata(dev);
|
2011-07-21 04:19:55 +04:00
|
|
|
unsigned long flags;
|
2010-10-28 02:33:21 +04:00
|
|
|
|
2011-07-21 04:19:55 +04:00
|
|
|
spin_lock_irqsave(&chip->spinlock, flags);
|
2010-10-28 02:33:21 +04:00
|
|
|
pch_gpio_save_reg_conf(chip);
|
2011-07-21 04:19:55 +04:00
|
|
|
spin_unlock_irqrestore(&chip->spinlock, flags);
|
2010-10-28 02:33:21 +04:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-11-07 22:19:45 +03:00
|
|
|
static int __maybe_unused pch_gpio_resume(struct device *dev)
|
2010-10-28 02:33:21 +04:00
|
|
|
{
|
2019-07-23 11:39:24 +03:00
|
|
|
struct pch_gpio *chip = dev_get_drvdata(dev);
|
2011-07-21 04:19:55 +04:00
|
|
|
unsigned long flags;
|
2010-10-28 02:33:21 +04:00
|
|
|
|
2011-07-21 04:19:55 +04:00
|
|
|
spin_lock_irqsave(&chip->spinlock, flags);
|
2010-10-28 02:33:21 +04:00
|
|
|
iowrite32(0x01, &chip->reg->reset);
|
|
|
|
iowrite32(0x00, &chip->reg->reset);
|
|
|
|
pch_gpio_restore_reg_conf(chip);
|
2011-07-21 04:19:55 +04:00
|
|
|
spin_unlock_irqrestore(&chip->spinlock, flags);
|
2010-10-28 02:33:21 +04:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2018-11-07 22:19:45 +03:00
|
|
|
|
|
|
|
static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
|
2010-10-28 02:33:21 +04:00
|
|
|
|
2013-12-03 03:08:45 +04:00
|
|
|
static const struct pci_device_id pch_gpio_pcidev_id[] = {
|
2010-10-28 02:33:21 +04:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803) },
|
2011-05-09 14:58:49 +04:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014) },
|
2011-07-21 04:19:56 +04:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043) },
|
2011-10-28 04:23:32 +04:00
|
|
|
{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803) },
|
2010-10-28 02:33:21 +04:00
|
|
|
{ 0, }
|
|
|
|
};
|
2011-03-12 01:58:30 +03:00
|
|
|
MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
|
2010-10-28 02:33:21 +04:00
|
|
|
|
|
|
|
static struct pci_driver pch_gpio_driver = {
|
|
|
|
.name = "pch_gpio",
|
|
|
|
.id_table = pch_gpio_pcidev_id,
|
|
|
|
.probe = pch_gpio_probe,
|
2018-11-07 22:19:45 +03:00
|
|
|
.driver = {
|
|
|
|
.pm = &pch_gpio_pm_ops,
|
|
|
|
},
|
2010-10-28 02:33:21 +04:00
|
|
|
};
|
|
|
|
|
2012-04-06 16:13:30 +04:00
|
|
|
module_pci_driver(pch_gpio_driver);
|
2010-10-28 02:33:21 +04:00
|
|
|
|
|
|
|
MODULE_DESCRIPTION("PCH GPIO PCI Driver");
|
2018-11-06 15:11:42 +03:00
|
|
|
MODULE_LICENSE("GPL v2");
|