2005-04-17 02:20:36 +04:00
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/*
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* Copyright (C) 1991, 1992, 1995 Linus Torvalds
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* Copyright (C) 2000, 2003 Maciej W. Rozycki
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*
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* This file contains the time handling details for PC-style clocks as
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* found in some MIPS systems.
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*
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*/
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#include <linux/bcd.h>
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#include <linux/init.h>
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#include <linux/mc146818rtc.h>
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#include <linux/param.h>
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2008-04-25 07:11:44 +04:00
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#include <asm/cpu-features.h>
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#include <asm/ds1287.h>
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#include <asm/time.h>
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2005-04-17 02:20:36 +04:00
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#include <asm/dec/interrupts.h>
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#include <asm/dec/ioasic.h>
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#include <asm/dec/machtype.h>
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2009-08-14 17:47:31 +04:00
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void read_persistent_clock(struct timespec *ts)
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2005-04-17 02:20:36 +04:00
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{
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unsigned int year, mon, day, hour, min, sec, real_year;
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2005-11-02 19:01:15 +03:00
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unsigned long flags;
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2005-04-17 02:20:36 +04:00
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2005-11-02 19:01:15 +03:00
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spin_lock_irqsave(&rtc_lock, flags);
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2006-03-28 13:56:06 +04:00
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2005-04-17 02:20:36 +04:00
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do {
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sec = CMOS_READ(RTC_SECONDS);
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min = CMOS_READ(RTC_MINUTES);
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hour = CMOS_READ(RTC_HOURS);
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day = CMOS_READ(RTC_DAY_OF_MONTH);
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mon = CMOS_READ(RTC_MONTH);
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year = CMOS_READ(RTC_YEAR);
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2006-03-28 13:56:06 +04:00
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/*
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* The PROM will reset the year to either '72 or '73.
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* Therefore we store the real year separately, in one
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* of unused BBU RAM locations.
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*/
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real_year = CMOS_READ(RTC_DEC_YEAR);
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2005-04-17 02:20:36 +04:00
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} while (sec != CMOS_READ(RTC_SECONDS));
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2006-03-28 13:56:06 +04:00
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spin_unlock_irqrestore(&rtc_lock, flags);
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2005-04-17 02:20:36 +04:00
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if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
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2008-10-19 07:28:44 +04:00
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sec = bcd2bin(sec);
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min = bcd2bin(min);
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hour = bcd2bin(hour);
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day = bcd2bin(day);
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mon = bcd2bin(mon);
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year = bcd2bin(year);
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2005-04-17 02:20:36 +04:00
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}
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2006-03-28 13:56:06 +04:00
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2005-04-17 02:20:36 +04:00
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year += real_year - 72 + 2000;
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2009-08-14 17:47:31 +04:00
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ts->tv_sec = mktime(year, mon, day, hour, min, sec);
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ts->tv_nsec = 0;
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2005-04-17 02:20:36 +04:00
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}
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/*
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2007-10-12 02:46:08 +04:00
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* In order to set the CMOS clock precisely, rtc_mips_set_mmss has to
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2005-04-17 02:20:36 +04:00
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* be called 500 ms after the second nowtime has started, because when
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* nowtime is written into the registers of the CMOS clock, it will
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* jump to the next second precisely 500 ms later. Check the Dallas
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* DS1287 data sheet for details.
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*/
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2007-10-12 02:46:08 +04:00
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int rtc_mips_set_mmss(unsigned long nowtime)
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2005-04-17 02:20:36 +04:00
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{
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int retval = 0;
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int real_seconds, real_minutes, cmos_minutes;
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unsigned char save_control, save_freq_select;
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2005-11-02 19:01:15 +03:00
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/* irq are locally disabled here */
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spin_lock(&rtc_lock);
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2005-04-17 02:20:36 +04:00
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/* tell the clock it's being set */
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save_control = CMOS_READ(RTC_CONTROL);
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CMOS_WRITE((save_control | RTC_SET), RTC_CONTROL);
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/* stop and reset prescaler */
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save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
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CMOS_WRITE((save_freq_select | RTC_DIV_RESET2), RTC_FREQ_SELECT);
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cmos_minutes = CMOS_READ(RTC_MINUTES);
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if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
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2008-10-19 07:28:44 +04:00
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cmos_minutes = bcd2bin(cmos_minutes);
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2005-04-17 02:20:36 +04:00
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/*
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* since we're only adjusting minutes and seconds,
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* don't interfere with hour overflow. This avoids
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* messing with unknown time zones but requires your
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* RTC not to be off by more than 15 minutes
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*/
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real_seconds = nowtime % 60;
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real_minutes = nowtime / 60;
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if (((abs(real_minutes - cmos_minutes) + 15) / 30) & 1)
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real_minutes += 30; /* correct for half hour time zone */
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real_minutes %= 60;
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if (abs(real_minutes - cmos_minutes) < 30) {
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if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
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2008-10-19 07:28:44 +04:00
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real_seconds = bin2bcd(real_seconds);
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real_minutes = bin2bcd(real_minutes);
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2005-04-17 02:20:36 +04:00
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}
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CMOS_WRITE(real_seconds, RTC_SECONDS);
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CMOS_WRITE(real_minutes, RTC_MINUTES);
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} else {
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2011-01-13 03:59:31 +03:00
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printk_once(KERN_NOTICE
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2005-04-17 02:20:36 +04:00
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"set_rtc_mmss: can't update from %d to %d\n",
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cmos_minutes, real_minutes);
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retval = -1;
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}
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/* The following flags have to be released exactly in this order,
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* otherwise the DS1287 will not reset the oscillator and will not
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* update precisely 500 ms later. You won't find this mentioned
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* in the Dallas Semiconductor data sheets, but who believes data
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* sheets anyway ... -- Markus Kuhn
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*/
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CMOS_WRITE(save_control, RTC_CONTROL);
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CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
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2005-11-02 19:01:15 +03:00
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spin_unlock(&rtc_lock);
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2005-04-17 02:20:36 +04:00
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return retval;
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}
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2008-04-25 07:11:44 +04:00
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void __init plat_time_init(void)
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2005-04-17 02:20:36 +04:00
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{
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2013-09-12 15:01:53 +04:00
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int ioasic_clock = 0;
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2008-04-25 07:11:44 +04:00
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u32 start, end;
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MIPS: DECstation HRT calibration bug fixes
This change corrects DECstation HRT calibration, by removing the following
bugs:
1. Calibration period selection -- HZ / 10 has been chosen, however on
DECstation computers, HZ never divides by 10, as the choice for HZ is
among 128, 256 and 1024. The choice therefore results in a systematic
calibration error, e.g. 6.25% for the usual choice of 128 for HZ:
128 / 10 * 10 = 120
(128 - 120) / 128 -> 6.25%
The change therefore makes calibration use HZ / 8 that is always
accurate for the HZ values available, getting rid of the systematic
error.
2. Calibration starting point synchronisation -- the duration of a number
of intervals between DS1287A periodic interrupt assertions is measured,
however code does not ensure at the beginning that the interrupt has
not been previously asserted. This results in a variable error of e.g.
up to another 6.25% for the period of HZ / 8 (8.(3)% with the original
HZ / 10 period) and the usual choice of 128 for HZ:
1 / 16 -> 6.25%
1 / 12 -> 8.(3)%
The change therefore adds an initial call to ds1287_timer_state that
clears any previous periodic interrupt pending.
The same issue applies to both I/O ASIC counter and R4k CP0 timer
calibration on DECstation systems as similar code is used in both cases
and both pieces of code are covered by this fix.
On an R3400 test system used this fix results in a change of the I/O ASIC
clock frequency reported from values like:
I/O ASIC clock frequency 23185830Hz
to:
I/O ASIC clock frequency 24999288Hz
removing the miscalculation by 6.25% from the systematic error and (for
the individual sample provided) a further 1.00% from the variable error,
accordingly. The nominal I/O ASIC clock frequency is 25MHz on this
system.
Here's another result, with the fix applied, from a system that has both
HRTs available (using an R4400 at 60MHz nominal):
MIPS counter frequency 59999328Hz
I/O ASIC clock frequency 24999432Hz
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5807/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-09-05 02:47:45 +04:00
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int i = HZ / 8;
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2005-04-17 02:20:36 +04:00
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2008-04-25 07:11:44 +04:00
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/* Set up the rate of periodic DS1287 interrupts. */
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ds1287_set_base_clock(HZ);
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2005-04-17 02:20:36 +04:00
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2013-09-12 15:01:53 +04:00
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/* On some I/O ASIC systems we have the I/O ASIC's counter. */
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if (IOASIC)
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ioasic_clock = dec_ioasic_clocksource_init() == 0;
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2008-04-25 07:11:44 +04:00
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if (cpu_has_counter) {
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MIPS: DECstation HRT calibration bug fixes
This change corrects DECstation HRT calibration, by removing the following
bugs:
1. Calibration period selection -- HZ / 10 has been chosen, however on
DECstation computers, HZ never divides by 10, as the choice for HZ is
among 128, 256 and 1024. The choice therefore results in a systematic
calibration error, e.g. 6.25% for the usual choice of 128 for HZ:
128 / 10 * 10 = 120
(128 - 120) / 128 -> 6.25%
The change therefore makes calibration use HZ / 8 that is always
accurate for the HZ values available, getting rid of the systematic
error.
2. Calibration starting point synchronisation -- the duration of a number
of intervals between DS1287A periodic interrupt assertions is measured,
however code does not ensure at the beginning that the interrupt has
not been previously asserted. This results in a variable error of e.g.
up to another 6.25% for the period of HZ / 8 (8.(3)% with the original
HZ / 10 period) and the usual choice of 128 for HZ:
1 / 16 -> 6.25%
1 / 12 -> 8.(3)%
The change therefore adds an initial call to ds1287_timer_state that
clears any previous periodic interrupt pending.
The same issue applies to both I/O ASIC counter and R4k CP0 timer
calibration on DECstation systems as similar code is used in both cases
and both pieces of code are covered by this fix.
On an R3400 test system used this fix results in a change of the I/O ASIC
clock frequency reported from values like:
I/O ASIC clock frequency 23185830Hz
to:
I/O ASIC clock frequency 24999288Hz
removing the miscalculation by 6.25% from the systematic error and (for
the individual sample provided) a further 1.00% from the variable error,
accordingly. The nominal I/O ASIC clock frequency is 25MHz on this
system.
Here's another result, with the fix applied, from a system that has both
HRTs available (using an R4400 at 60MHz nominal):
MIPS counter frequency 59999328Hz
I/O ASIC clock frequency 24999432Hz
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5807/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-09-05 02:47:45 +04:00
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ds1287_timer_state();
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2008-04-25 07:11:44 +04:00
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while (!ds1287_timer_state())
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;
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2005-04-17 02:20:36 +04:00
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2008-04-25 07:11:44 +04:00
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start = read_c0_count();
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2005-04-17 02:20:36 +04:00
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2008-04-25 07:11:44 +04:00
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while (i--)
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while (!ds1287_timer_state())
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;
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end = read_c0_count();
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2005-04-17 02:20:36 +04:00
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MIPS: DECstation HRT calibration bug fixes
This change corrects DECstation HRT calibration, by removing the following
bugs:
1. Calibration period selection -- HZ / 10 has been chosen, however on
DECstation computers, HZ never divides by 10, as the choice for HZ is
among 128, 256 and 1024. The choice therefore results in a systematic
calibration error, e.g. 6.25% for the usual choice of 128 for HZ:
128 / 10 * 10 = 120
(128 - 120) / 128 -> 6.25%
The change therefore makes calibration use HZ / 8 that is always
accurate for the HZ values available, getting rid of the systematic
error.
2. Calibration starting point synchronisation -- the duration of a number
of intervals between DS1287A periodic interrupt assertions is measured,
however code does not ensure at the beginning that the interrupt has
not been previously asserted. This results in a variable error of e.g.
up to another 6.25% for the period of HZ / 8 (8.(3)% with the original
HZ / 10 period) and the usual choice of 128 for HZ:
1 / 16 -> 6.25%
1 / 12 -> 8.(3)%
The change therefore adds an initial call to ds1287_timer_state that
clears any previous periodic interrupt pending.
The same issue applies to both I/O ASIC counter and R4k CP0 timer
calibration on DECstation systems as similar code is used in both cases
and both pieces of code are covered by this fix.
On an R3400 test system used this fix results in a change of the I/O ASIC
clock frequency reported from values like:
I/O ASIC clock frequency 23185830Hz
to:
I/O ASIC clock frequency 24999288Hz
removing the miscalculation by 6.25% from the systematic error and (for
the individual sample provided) a further 1.00% from the variable error,
accordingly. The nominal I/O ASIC clock frequency is 25MHz on this
system.
Here's another result, with the fix applied, from a system that has both
HRTs available (using an R4400 at 60MHz nominal):
MIPS counter frequency 59999328Hz
I/O ASIC clock frequency 24999432Hz
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5807/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2013-09-05 02:47:45 +04:00
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mips_hpt_frequency = (end - start) * 8;
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2008-04-25 07:11:44 +04:00
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printk(KERN_INFO "MIPS counter frequency %dHz\n",
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mips_hpt_frequency);
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2013-09-12 15:01:53 +04:00
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/*
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* All R4k DECstations suffer from the CP0 Count erratum,
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* so we can't use the timer as a clock source, and a clock
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* event both at a time. An accurate wall clock is more
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* important than a high-precision interval timer so only
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* use the timer as a clock source, and not a clock event
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* if there's no I/O ASIC counter available to serve as a
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* clock source.
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*/
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if (!ioasic_clock) {
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init_r4k_clocksource();
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mips_hpt_frequency = 0;
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}
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}
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2005-04-17 02:20:36 +04:00
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2008-04-25 07:11:44 +04:00
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ds1287_clockevent_init(dec_interrupt[DEC_IRQ_RTC]);
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2005-04-17 02:20:36 +04:00
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}
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