2008-01-07 15:03:18 +03:00
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/*
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* MPC8377E MDS Device Tree Source
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*
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* Copyright 2007 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "fsl,mpc8377emds";
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compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8377@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <0x20>;
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i-cache-line-size = <0x20>;
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d-cache-size = <0x8000>; // L1, 32K
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i-cache-size = <0x8000>; // L1, 32K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x20000000>; // 512MB at 0
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};
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soc@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0x0 0xe0000000 0x00100000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <0>;
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wdt@200 {
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compatible = "mpc83xx_wdt";
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reg = <0x200 0x100>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <0xe 0x8>;
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interrupt-parent = < &ipic >;
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dfsrr;
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};
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <0xf 0x8>;
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interrupt-parent = < &ipic >;
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dfsrr;
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};
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spi@7000 {
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2008-01-24 18:40:07 +03:00
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cell-index = <0>;
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compatible = "fsl,spi";
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2008-01-07 15:03:18 +03:00
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reg = <0x7000 0x1000>;
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interrupts = <0x10 0x8>;
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interrupt-parent = < &ipic >;
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mode = "cpu";
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};
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/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
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usb@23000 {
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compatible = "fsl-usb2-dr";
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reg = <0x23000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = < &ipic >;
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interrupts = <0x26 0x8>;
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phy_type = "utmi_wide";
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x24520 0x20>;
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phy2: ethernet-phy@2 {
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interrupt-parent = < &ipic >;
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interrupts = <0x11 0x8>;
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reg = <2>;
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device_type = "ethernet-phy";
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};
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phy3: ethernet-phy@3 {
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interrupt-parent = < &ipic >;
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interrupts = <0x12 0x8>;
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reg = <3>;
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device_type = "ethernet-phy";
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};
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};
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enet0: ethernet@24000 {
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cell-index = <0>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
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phy-connection-type = "mii";
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interrupt-parent = < &ipic >;
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phy-handle = < &phy2 >;
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};
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enet1: ethernet@25000 {
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cell-index = <1>;
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x25000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
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phy-connection-type = "mii";
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interrupt-parent = < &ipic >;
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phy-handle = < &phy3 >;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <0x9 0x8>;
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interrupt-parent = < &ipic >;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <0xa 0x8>;
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interrupt-parent = < &ipic >;
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};
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crypto@30000 {
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model = "SEC3";
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compatible = "talitos";
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reg = <0x30000 0x10000>;
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interrupts = <0xb 0x8>;
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interrupt-parent = < &ipic >;
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/* Rev. 3.0 geometry */
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num-channels = <4>;
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channel-fifo-len = <0x18>;
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exec-units-mask = <0x000001fe>;
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descriptor-types-mask = <0x03ab0ebf>;
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};
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sdhc@2e000 {
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model = "eSDHC";
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compatible = "fsl,esdhc";
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reg = <0x2e000 0x1000>;
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interrupts = <0x2a 0x8>;
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interrupt-parent = < &ipic >;
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};
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sata@18000 {
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compatible = "fsl,mpc8379-sata";
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reg = <0x18000 0x1000>;
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interrupts = <0x2c 0x8>;
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interrupt-parent = < &ipic >;
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};
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sata@19000 {
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compatible = "fsl,mpc8379-sata";
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reg = <0x19000 0x1000>;
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interrupts = <0x2d 0x8>;
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interrupt-parent = < &ipic >;
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};
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/* IPIC
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* interrupts cell = <intr #, sense>
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* sense values match linux IORESOURCE_IRQ_* defines:
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* sense == 8: Level, low assertion
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* sense == 2: Edge, high-to-low change
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*/
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ipic: pic@700 {
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compatible = "fsl,ipic";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x700 0x100>;
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};
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};
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pci0: pci@e0008500 {
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cell-index = <0>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x11 */
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0x8800 0x0 0x0 0x1 &ipic 0x14 0x8
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0x8800 0x0 0x0 0x2 &ipic 0x15 0x8
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0x8800 0x0 0x0 0x3 &ipic 0x16 0x8
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0x8800 0x0 0x0 0x4 &ipic 0x17 0x8
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/* IDSEL 0x12 */
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0x9000 0x0 0x0 0x1 &ipic 0x16 0x8
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0x9000 0x0 0x0 0x2 &ipic 0x17 0x8
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0x9000 0x0 0x0 0x3 &ipic 0x14 0x8
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0x9000 0x0 0x0 0x4 &ipic 0x15 0x8
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/* IDSEL 0x13 */
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0x9800 0x0 0x0 0x1 &ipic 0x17 0x8
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0x9800 0x0 0x0 0x2 &ipic 0x14 0x8
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0x9800 0x0 0x0 0x3 &ipic 0x15 0x8
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0x9800 0x0 0x0 0x4 &ipic 0x16 0x8
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/* IDSEL 0x15 */
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0xa800 0x0 0x0 0x1 &ipic 0x14 0x8
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0xa800 0x0 0x0 0x2 &ipic 0x15 0x8
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0xa800 0x0 0x0 0x3 &ipic 0x16 0x8
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0xa800 0x0 0x0 0x4 &ipic 0x17 0x8
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/* IDSEL 0x16 */
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0xb000 0x0 0x0 0x1 &ipic 0x17 0x8
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0xb000 0x0 0x0 0x2 &ipic 0x14 0x8
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0xb000 0x0 0x0 0x3 &ipic 0x15 0x8
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0xb000 0x0 0x0 0x4 &ipic 0x16 0x8
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/* IDSEL 0x17 */
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0xb800 0x0 0x0 0x1 &ipic 0x16 0x8
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0xb800 0x0 0x0 0x2 &ipic 0x17 0x8
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0xb800 0x0 0x0 0x3 &ipic 0x14 0x8
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0xb800 0x0 0x0 0x4 &ipic 0x15 0x8
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/* IDSEL 0x18 */
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0xc000 0x0 0x0 0x1 &ipic 0x15 0x8
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0xc000 0x0 0x0 0x2 &ipic 0x16 0x8
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0xc000 0x0 0x0 0x3 &ipic 0x17 0x8
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0xc000 0x0 0x0 0x4 &ipic 0x14 0x8>;
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interrupt-parent = < &ipic >;
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interrupts = <0x42 0x8>;
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bus-range = <0 0>;
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ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
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0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
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0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
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clock-frequency = <0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0xe0008500 0x100>;
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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};
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