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WSL2-Linux-Kernel/arch/mips/pci/fixup-sb1250.c

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Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 02:20:36 +04:00
/*
[MIPS] BCM1250: TRDY timeout tweaks for Broadcom SiByte systems It was obesrved that at least one older PCI card predating the requirement for the TRDY signal to respond within 16 clock ticks actually does not meet this rule nor even the power-on defaults of the PCI bridges found in development systems built around the Broadcom SiByte SOCs. Here is a patch that bumps up the timeout to the highest finite value supported by these chips, which is 255 clock ticks. The bridges affected are the SiByte SOC itself and the SP1011. This change does not effectively affect systems only having PCI option cards installed that meet the TRDY requirement of the current PCI spec. The rule was introduced with PCI 2.1, so any older card may make the system affected. If this is the case, performance of the system will suffer in return for the card working at all. If this is a concern, then the solution is not to use such cards. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2006-10-02 15:55:09 +04:00
* Copyright (C) 2004, 2006 MIPS Technologies, Inc. All rights reserved.
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 02:20:36 +04:00
* Author: Maciej W. Rozycki <macro@mips.com>
MIPS: SiByte: Set 32-bit bus mask for BCM1250 PCI The Broadcom SiByte BCM1250, BCM1125H and BCM1125 SOCs have an onchip 32-bit PCI host bridge, and the two former SOCs also have an onchip HT host bridge. The HT host bridge, where present, appears in the PCI configuration space as if it was a device on the 32-bit PCI bus behind the PCI host bridge, however at the hardware level its signals are routed separately, so these two devices are actually peer host bridges. As documented[1] and observed in reality the 32-bit PCI host bridge does not support 64-bit addressing as it does not support the Dual Address Cycle (DAC) PCI command, and naturally, being 32-bit only, it has no means to carry the high 32 address bits otherwise. However the DRAM controller also included in the SOC supports memory amounts of up to 16GiB, and due to how the address decoder has been wired in the SOC any memory beyond 1GiB is actually mapped starting from 4GiB physical up, that is beyond the 32-bit addressable limit. Consequently if the maximum amount of memory has been installed, then it will span up to 19GiB. Contrariwise, the HT host bridge does support full 40-bit addressing defined by the HyperTransport (formerly LDT) specification the bridge adheres to, depending on the peripherals revision of the SOC[2] either revision 0.17[3] or revision 1.03[4]. This allows addressing any and all memory installed, and well beyond. Set the bus mask then to limit DMA addressing to 32 bits for all the devices down the 32-bit PCI host bridge, excluding however any devices that are down the HT host bridge. References: [1] "BCM1250/BCM1125/BCM1125H User Manual", Revision 1250_1125-UM100-R, Broadcom Corporation, 21 Oct 2002, Section 8: "PCI Bus and HyperTransport Fabric", "Introduction", p. 190 [2] same, Table 140: "HyperTransport Configuration Header (Type 1)", p. 245 [3] "Lightning Data Transport IO Specification", Revision 0.17, Advanced Micro Devices, 21 Jan 2000, Section 3.2.1.2 "Command Packet", p. 8 [4] "HyperTransport I/O Link Specification", Revision 1.03, HyperTransport Technology Consortium, 10 Oct 2001, Section 3.2.1.2 "Request Packet", pp. 27-28 Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Patchwork: https://patchwork.linux-mips.org/patch/21106/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
2018-11-14 01:42:30 +03:00
* Copyright (C) 2018 Maciej W. Rozycki
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 02:20:36 +04:00
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
MIPS: SiByte: Set 32-bit bus mask for BCM1250 PCI The Broadcom SiByte BCM1250, BCM1125H and BCM1125 SOCs have an onchip 32-bit PCI host bridge, and the two former SOCs also have an onchip HT host bridge. The HT host bridge, where present, appears in the PCI configuration space as if it was a device on the 32-bit PCI bus behind the PCI host bridge, however at the hardware level its signals are routed separately, so these two devices are actually peer host bridges. As documented[1] and observed in reality the 32-bit PCI host bridge does not support 64-bit addressing as it does not support the Dual Address Cycle (DAC) PCI command, and naturally, being 32-bit only, it has no means to carry the high 32 address bits otherwise. However the DRAM controller also included in the SOC supports memory amounts of up to 16GiB, and due to how the address decoder has been wired in the SOC any memory beyond 1GiB is actually mapped starting from 4GiB physical up, that is beyond the 32-bit addressable limit. Consequently if the maximum amount of memory has been installed, then it will span up to 19GiB. Contrariwise, the HT host bridge does support full 40-bit addressing defined by the HyperTransport (formerly LDT) specification the bridge adheres to, depending on the peripherals revision of the SOC[2] either revision 0.17[3] or revision 1.03[4]. This allows addressing any and all memory installed, and well beyond. Set the bus mask then to limit DMA addressing to 32 bits for all the devices down the 32-bit PCI host bridge, excluding however any devices that are down the HT host bridge. References: [1] "BCM1250/BCM1125/BCM1125H User Manual", Revision 1250_1125-UM100-R, Broadcom Corporation, 21 Oct 2002, Section 8: "PCI Bus and HyperTransport Fabric", "Introduction", p. 190 [2] same, Table 140: "HyperTransport Configuration Header (Type 1)", p. 245 [3] "Lightning Data Transport IO Specification", Revision 0.17, Advanced Micro Devices, 21 Jan 2000, Section 3.2.1.2 "Command Packet", p. 8 [4] "HyperTransport I/O Link Specification", Revision 1.03, HyperTransport Technology Consortium, 10 Oct 2001, Section 3.2.1.2 "Request Packet", pp. 27-28 Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Patchwork: https://patchwork.linux-mips.org/patch/21106/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
2018-11-14 01:42:30 +03:00
#include <linux/dma-mapping.h>
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 02:20:36 +04:00
#include <linux/pci.h>
[MIPS] BCM1250: TRDY timeout tweaks for Broadcom SiByte systems It was obesrved that at least one older PCI card predating the requirement for the TRDY signal to respond within 16 clock ticks actually does not meet this rule nor even the power-on defaults of the PCI bridges found in development systems built around the Broadcom SiByte SOCs. Here is a patch that bumps up the timeout to the highest finite value supported by these chips, which is 255 clock ticks. The bridges affected are the SiByte SOC itself and the SP1011. This change does not effectively affect systems only having PCI option cards installed that meet the TRDY requirement of the current PCI spec. The rule was introduced with PCI 2.1, so any older card may make the system affected. If this is the case, performance of the system will suffer in return for the card working at all. If this is a concern, then the solution is not to use such cards. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2006-10-02 15:55:09 +04:00
/*
Fix occurrences of "the the " Signed-off-by: Michael Opdenacker <michael@free-electrons.com> Signed-off-by: Adrian Bunk <bunk@stusta.de>
2007-05-09 10:57:56 +04:00
* Set the BCM1250, etc. PCI host bridge's TRDY timeout
[MIPS] BCM1250: TRDY timeout tweaks for Broadcom SiByte systems It was obesrved that at least one older PCI card predating the requirement for the TRDY signal to respond within 16 clock ticks actually does not meet this rule nor even the power-on defaults of the PCI bridges found in development systems built around the Broadcom SiByte SOCs. Here is a patch that bumps up the timeout to the highest finite value supported by these chips, which is 255 clock ticks. The bridges affected are the SiByte SOC itself and the SP1011. This change does not effectively affect systems only having PCI option cards installed that meet the TRDY requirement of the current PCI spec. The rule was introduced with PCI 2.1, so any older card may make the system affected. If this is the case, performance of the system will suffer in return for the card working at all. If this is a concern, then the solution is not to use such cards. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2006-10-02 15:55:09 +04:00
* to the finite max.
*/
MIPS: drivers: remove __dev* attributes. CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-12-22 02:04:39 +04:00
static void quirk_sb1250_pci(struct pci_dev *dev)
[MIPS] BCM1250: TRDY timeout tweaks for Broadcom SiByte systems It was obesrved that at least one older PCI card predating the requirement for the TRDY signal to respond within 16 clock ticks actually does not meet this rule nor even the power-on defaults of the PCI bridges found in development systems built around the Broadcom SiByte SOCs. Here is a patch that bumps up the timeout to the highest finite value supported by these chips, which is 255 clock ticks. The bridges affected are the SiByte SOC itself and the SP1011. This change does not effectively affect systems only having PCI option cards installed that meet the TRDY requirement of the current PCI spec. The rule was introduced with PCI 2.1, so any older card may make the system affected. If this is the case, performance of the system will suffer in return for the card working at all. If this is a concern, then the solution is not to use such cards. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2006-10-02 15:55:09 +04:00
{
pci_write_config_byte(dev, 0x40, 0xff);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
quirk_sb1250_pci);
MIPS: SiByte: Set 32-bit bus mask for BCM1250 PCI The Broadcom SiByte BCM1250, BCM1125H and BCM1125 SOCs have an onchip 32-bit PCI host bridge, and the two former SOCs also have an onchip HT host bridge. The HT host bridge, where present, appears in the PCI configuration space as if it was a device on the 32-bit PCI bus behind the PCI host bridge, however at the hardware level its signals are routed separately, so these two devices are actually peer host bridges. As documented[1] and observed in reality the 32-bit PCI host bridge does not support 64-bit addressing as it does not support the Dual Address Cycle (DAC) PCI command, and naturally, being 32-bit only, it has no means to carry the high 32 address bits otherwise. However the DRAM controller also included in the SOC supports memory amounts of up to 16GiB, and due to how the address decoder has been wired in the SOC any memory beyond 1GiB is actually mapped starting from 4GiB physical up, that is beyond the 32-bit addressable limit. Consequently if the maximum amount of memory has been installed, then it will span up to 19GiB. Contrariwise, the HT host bridge does support full 40-bit addressing defined by the HyperTransport (formerly LDT) specification the bridge adheres to, depending on the peripherals revision of the SOC[2] either revision 0.17[3] or revision 1.03[4]. This allows addressing any and all memory installed, and well beyond. Set the bus mask then to limit DMA addressing to 32 bits for all the devices down the 32-bit PCI host bridge, excluding however any devices that are down the HT host bridge. References: [1] "BCM1250/BCM1125/BCM1125H User Manual", Revision 1250_1125-UM100-R, Broadcom Corporation, 21 Oct 2002, Section 8: "PCI Bus and HyperTransport Fabric", "Introduction", p. 190 [2] same, Table 140: "HyperTransport Configuration Header (Type 1)", p. 245 [3] "Lightning Data Transport IO Specification", Revision 0.17, Advanced Micro Devices, 21 Jan 2000, Section 3.2.1.2 "Command Packet", p. 8 [4] "HyperTransport I/O Link Specification", Revision 1.03, HyperTransport Technology Consortium, 10 Oct 2001, Section 3.2.1.2 "Request Packet", pp. 27-28 Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Patchwork: https://patchwork.linux-mips.org/patch/21106/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org
2018-11-14 01:42:30 +03:00
/*
* The BCM1250, etc. PCI host bridge does not support DAC on its 32-bit
* bus, so we set the bus's DMA mask accordingly. However the HT link
* down the artificial PCI-HT bridge supports 40-bit addressing and the
* SP1011 HT-PCI bridge downstream supports both DAC and a 64-bit bus
* width, so we record the PCI-HT bridge's secondary and subordinate bus
* numbers and do not set the mask for devices present in the inclusive
* range of those.
*/
struct sb1250_bus_dma_mask_exclude {
bool set;
unsigned char start;
unsigned char end;
};
static int sb1250_bus_dma_mask(struct pci_dev *dev, void *data)
{
struct sb1250_bus_dma_mask_exclude *exclude = data;
bool exclude_this;
bool ht_bridge;
exclude_this = exclude->set && (dev->bus->number >= exclude->start &&
dev->bus->number <= exclude->end);
ht_bridge = !exclude->set && (dev->vendor == PCI_VENDOR_ID_SIBYTE &&
dev->device == PCI_DEVICE_ID_BCM1250_HT);
if (exclude_this) {
dev_dbg(&dev->dev, "not disabling DAC for device");
} else if (ht_bridge) {
exclude->start = dev->subordinate->number;
exclude->end = pci_bus_max_busnr(dev->subordinate);
exclude->set = true;
dev_dbg(&dev->dev, "not disabling DAC for [bus %02x-%02x]",
exclude->start, exclude->end);
} else {
dev_dbg(&dev->dev, "disabling DAC for device");
dev->dev.bus_dma_mask = DMA_BIT_MASK(32);
}
return 0;
}
static void quirk_sb1250_pci_dac(struct pci_dev *dev)
{
struct sb1250_bus_dma_mask_exclude exclude = { .set = false };
pci_walk_bus(dev->bus, sb1250_bus_dma_mask, &exclude);
}
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_PCI,
quirk_sb1250_pci_dac);
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 02:20:36 +04:00
/*
* The BCM1250, etc. PCI/HT bridge reports as a host bridge.
*/
MIPS: drivers: remove __dev* attributes. CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-12-22 02:04:39 +04:00
static void quirk_sb1250_ht(struct pci_dev *dev)
Linux-2.6.12-rc2 Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
2005-04-17 02:20:36 +04:00
{
dev->class = PCI_CLASS_BRIDGE_PCI << 8;
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIBYTE, PCI_DEVICE_ID_BCM1250_HT,
quirk_sb1250_ht);
[MIPS] BCM1250: TRDY timeout tweaks for Broadcom SiByte systems It was obesrved that at least one older PCI card predating the requirement for the TRDY signal to respond within 16 clock ticks actually does not meet this rule nor even the power-on defaults of the PCI bridges found in development systems built around the Broadcom SiByte SOCs. Here is a patch that bumps up the timeout to the highest finite value supported by these chips, which is 255 clock ticks. The bridges affected are the SiByte SOC itself and the SP1011. This change does not effectively affect systems only having PCI option cards installed that meet the TRDY requirement of the current PCI spec. The rule was introduced with PCI 2.1, so any older card may make the system affected. If this is the case, performance of the system will suffer in return for the card working at all. If this is a concern, then the solution is not to use such cards. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2006-10-02 15:55:09 +04:00
/*
Fix occurrences of "the the " Signed-off-by: Michael Opdenacker <michael@free-electrons.com> Signed-off-by: Adrian Bunk <bunk@stusta.de>
2007-05-09 10:57:56 +04:00
* Set the SP1011 HT/PCI bridge's TRDY timeout to the finite max.
[MIPS] BCM1250: TRDY timeout tweaks for Broadcom SiByte systems It was obesrved that at least one older PCI card predating the requirement for the TRDY signal to respond within 16 clock ticks actually does not meet this rule nor even the power-on defaults of the PCI bridges found in development systems built around the Broadcom SiByte SOCs. Here is a patch that bumps up the timeout to the highest finite value supported by these chips, which is 255 clock ticks. The bridges affected are the SiByte SOC itself and the SP1011. This change does not effectively affect systems only having PCI option cards installed that meet the TRDY requirement of the current PCI spec. The rule was introduced with PCI 2.1, so any older card may make the system affected. If this is the case, performance of the system will suffer in return for the card working at all. If this is a concern, then the solution is not to use such cards. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2006-10-02 15:55:09 +04:00
*/
MIPS: drivers: remove __dev* attributes. CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed. This change removes the use of __devinit, __devexit_p, __devinitdata, and __devexit from these drivers. Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand. Cc: Bill Pemberton <wfp5p@virginia.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2012-12-22 02:04:39 +04:00
static void quirk_sp1011(struct pci_dev *dev)
[MIPS] BCM1250: TRDY timeout tweaks for Broadcom SiByte systems It was obesrved that at least one older PCI card predating the requirement for the TRDY signal to respond within 16 clock ticks actually does not meet this rule nor even the power-on defaults of the PCI bridges found in development systems built around the Broadcom SiByte SOCs. Here is a patch that bumps up the timeout to the highest finite value supported by these chips, which is 255 clock ticks. The bridges affected are the SiByte SOC itself and the SP1011. This change does not effectively affect systems only having PCI option cards installed that meet the TRDY requirement of the current PCI spec. The rule was introduced with PCI 2.1, so any older card may make the system affected. If this is the case, performance of the system will suffer in return for the card working at all. If this is a concern, then the solution is not to use such cards. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ---
2006-10-02 15:55:09 +04:00
{
pci_write_config_byte(dev, 0x64, 0xff);
}
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIPACKETS, PCI_DEVICE_ID_SP1011,
quirk_sp1011);