2005-04-17 02:20:36 +04:00
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/*
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* Low-level SLB routines
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*
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* Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
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*
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* Based on earlier C version:
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* Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
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* Copyright (c) 2001 Dave Engebretsen
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* Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/processor.h>
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#include <asm/ppc_asm.h>
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2005-09-09 22:57:26 +04:00
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#include <asm/asm-offsets.h>
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2005-04-17 02:20:36 +04:00
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#include <asm/cputable.h>
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2005-11-07 03:06:55 +03:00
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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2006-09-25 12:19:00 +04:00
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#include <asm/firmware.h>
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2005-04-17 02:20:36 +04:00
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2005-11-07 03:06:55 +03:00
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/* void slb_allocate_realmode(unsigned long ea);
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2005-04-17 02:20:36 +04:00
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*
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* Create an SLB entry for the given EA (user or kernel).
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* r3 = faulting address, r13 = PACA
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* r9, r10, r11 are clobbered by this function
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* No other registers are examined or changed.
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*/
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2005-11-07 03:06:55 +03:00
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_GLOBAL(slb_allocate_realmode)
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/* r3 = faulting address */
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2005-04-17 02:20:36 +04:00
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srdi r9,r3,60 /* get region */
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2005-11-07 03:06:55 +03:00
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srdi r10,r3,28 /* get esid */
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2005-12-05 19:24:33 +03:00
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cmpldi cr7,r9,0xc /* cmp PAGE_OFFSET for later use */
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2005-04-17 02:20:36 +04:00
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2005-12-05 19:24:33 +03:00
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/* r3 = address, r10 = esid, cr7 = <> PAGE_OFFSET */
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2005-04-17 02:20:36 +04:00
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blt cr7,0f /* user or kernel? */
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/* kernel address: proto-VSID = ESID */
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/* WARNING - MAGIC: we don't use the VSID 0xfffffffff, but
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* this code will generate the protoVSID 0xfffffffff for the
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* top segment. That's ok, the scramble below will translate
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* it to VSID 0, which is reserved as a bad VSID - one which
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* will never have any pages in it. */
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[POWERPC] vmemmap fixes to use smaller pages
This changes vmemmap to use a different region (region 0xf) of the
address space, and to configure the page size of that region
dynamically at boot.
The problem with the current approach of always using 16M pages is that
it's not well suited to machines that have small amounts of memory such
as small partitions on pseries, or PS3's.
In fact, on the PS3, failure to allocate the 16M page backing vmmemmap
tends to prevent hotplugging the HV's "additional" memory, thus limiting
the available memory even more, from my experience down to something
like 80M total, which makes it really not very useable.
The logic used by my match to choose the vmemmap page size is:
- If 16M pages are available and there's 1G or more RAM at boot,
use that size.
- Else if 64K pages are available, use that
- Else use 4K pages
I've tested on a POWER6 (16M pages) and on an iSeries POWER3 (4K pages)
and it seems to work fine.
Note that I intend to change the way we organize the kernel regions &
SLBs so the actual region will change from 0xf back to something else at
one point, as I simplify the SLB miss handler, but that will be for a
later patch.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-04-30 09:41:48 +04:00
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/* Check if hitting the linear mapping or some other kernel space
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2005-11-07 03:06:55 +03:00
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*/
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bne cr7,1f
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/* Linear mapping encoding bits, the "li" instruction below will
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* be patched by the kernel at boot
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*/
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_GLOBAL(slb_miss_kernel_load_linear)
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li r11,0
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2007-10-11 14:37:10 +04:00
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BEGIN_FTR_SECTION
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2005-11-07 03:06:55 +03:00
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b slb_finish_load
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2007-10-11 14:37:10 +04:00
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END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
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b slb_finish_load_1T
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2005-11-07 03:06:55 +03:00
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[POWERPC] vmemmap fixes to use smaller pages
This changes vmemmap to use a different region (region 0xf) of the
address space, and to configure the page size of that region
dynamically at boot.
The problem with the current approach of always using 16M pages is that
it's not well suited to machines that have small amounts of memory such
as small partitions on pseries, or PS3's.
In fact, on the PS3, failure to allocate the 16M page backing vmmemmap
tends to prevent hotplugging the HV's "additional" memory, thus limiting
the available memory even more, from my experience down to something
like 80M total, which makes it really not very useable.
The logic used by my match to choose the vmemmap page size is:
- If 16M pages are available and there's 1G or more RAM at boot,
use that size.
- Else if 64K pages are available, use that
- Else use 4K pages
I've tested on a POWER6 (16M pages) and on an iSeries POWER3 (4K pages)
and it seems to work fine.
Note that I intend to change the way we organize the kernel regions &
SLBs so the actual region will change from 0xf back to something else at
one point, as I simplify the SLB miss handler, but that will be for a
later patch.
Signed-off-by: Paul Mackerras <paulus@samba.org>
2008-04-30 09:41:48 +04:00
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1:
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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/* Check virtual memmap region. To be patches at kernel boot */
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cmpldi cr0,r9,0xf
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bne 1f
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_GLOBAL(slb_miss_kernel_load_vmemmap)
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li r11,0
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b 6f
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1:
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#endif /* CONFIG_SPARSEMEM_VMEMMAP */
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/* vmalloc/ioremap mapping encoding bits, the "li" instructions below
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2005-11-07 03:06:55 +03:00
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* will be patched by the kernel at boot
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*/
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2006-06-15 04:45:18 +04:00
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BEGIN_FTR_SECTION
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/* check whether this is in vmalloc or ioremap space */
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clrldi r11,r10,48
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cmpldi r11,(VMALLOC_SIZE >> 28) - 1
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bgt 5f
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lhz r11,PACAVMALLOCSLLP(r13)
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2007-10-11 14:37:10 +04:00
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b 6f
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2006-06-15 04:45:18 +04:00
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5:
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END_FTR_SECTION_IFCLR(CPU_FTR_CI_LARGE_PAGE)
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_GLOBAL(slb_miss_kernel_load_io)
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2005-11-07 03:06:55 +03:00
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li r11,0
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2007-10-11 14:37:10 +04:00
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6:
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BEGIN_FTR_SECTION
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2005-11-07 03:06:55 +03:00
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b slb_finish_load
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2007-10-11 14:37:10 +04:00
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END_FTR_SECTION_IFCLR(CPU_FTR_1T_SEGMENT)
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b slb_finish_load_1T
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2005-11-07 03:06:55 +03:00
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0: /* user address: proto-VSID = context << 15 | ESID. First check
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* if the address is within the boundaries of the user region
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*/
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srdi. r9,r10,USER_ESID_BITS
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2005-04-17 02:20:36 +04:00
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bne- 8f /* invalid ea bits set */
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2007-05-08 10:27:27 +04:00
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/* when using slices, we extract the psize off the slice bitmaps
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* and then we need to get the sllp encoding off the mmu_psize_defs
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* array.
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*
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* XXX This is a bit inefficient especially for the normal case,
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* so we should try to implement a fast path for the standard page
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* size using the old sllp value so we avoid the array. We cannot
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* really do dynamic patching unfortunately as processes might flip
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* between 4k and 64k standard page size
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*/
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#ifdef CONFIG_PPC_MM_SLICES
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[PATCH] ppc64: Fix bug in SLB miss handler for hugepages
This patch, however, should be applied on top of the 64k-page-size patch to
fix some problems with hugepage (some pre-existing, another introduced by
this patch).
The patch fixes a bug in the SLB miss handler for hugepages on ppc64
introduced by the dynamic hugepage patch (commit id
c594adad5653491813959277fb87a2fef54c4e05) due to a misunderstanding of the
srd instruction's behaviour (mea culpa). The problem arises when a 64-bit
process maps some hugepages in the low 4GB of the address space (unusual).
In this case, as well as the 256M segment in question being marked for
hugepages, other segments at 32G intervals will be incorrectly marked for
hugepages.
In the process, this patch tweaks the semantics of the hugepage bitmaps to
be more sensible. Previously, an address below 4G was marked for hugepages
if the appropriate segment bit in the "low areas" bitmask was set *or* if
the low bit in the "high areas" bitmap was set (which would mark all
addresses below 1TB for hugepage). With this patch, any given address is
governed by a single bitmap. Addresses below 4GB are marked for hugepage
if and only if their bit is set in the "low areas" bitmap (256M
granularity). Addresses between 4GB and 1TB are marked for hugepage iff
the low bit in the "high areas" bitmap is set. Higher addresses are marked
for hugepage iff their bit in the "high areas" bitmap is set (1TB
granularity).
To avoid conflicts, this patch must be applied on top of BenH's pending
patch for 64k base page size [0]. As such, this patch also addresses a
hugepage problem introduced by that patch. That patch allows hugepages of
1MB in size on hardware which supports it, however, that won't work when
using 4k pages (4 level pagetable), because in that case hugepage PTEs are
stored at the PMD level, and each PMD entry maps 2MB. This patch simply
disallows hugepages in that case (we can do something cleverer to re-enable
them some other day).
Built, booted, and a handful of hugepage related tests passed on POWER5
LPAR (both ARCH=powerpc and ARCH=ppc64).
[0] http://gate.crashing.org/~benh/ppc64-64k-pages.diff
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-07 11:57:52 +03:00
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cmpldi r10,16
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2007-05-08 10:27:27 +04:00
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/* Get the slice index * 4 in r11 and matching slice size mask in r9 */
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ld r9,PACALOWSLICESPSIZE(r13)
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sldi r11,r10,2
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[PATCH] ppc64: Fix bug in SLB miss handler for hugepages
This patch, however, should be applied on top of the 64k-page-size patch to
fix some problems with hugepage (some pre-existing, another introduced by
this patch).
The patch fixes a bug in the SLB miss handler for hugepages on ppc64
introduced by the dynamic hugepage patch (commit id
c594adad5653491813959277fb87a2fef54c4e05) due to a misunderstanding of the
srd instruction's behaviour (mea culpa). The problem arises when a 64-bit
process maps some hugepages in the low 4GB of the address space (unusual).
In this case, as well as the 256M segment in question being marked for
hugepages, other segments at 32G intervals will be incorrectly marked for
hugepages.
In the process, this patch tweaks the semantics of the hugepage bitmaps to
be more sensible. Previously, an address below 4G was marked for hugepages
if the appropriate segment bit in the "low areas" bitmask was set *or* if
the low bit in the "high areas" bitmap was set (which would mark all
addresses below 1TB for hugepage). With this patch, any given address is
governed by a single bitmap. Addresses below 4GB are marked for hugepage
if and only if their bit is set in the "low areas" bitmap (256M
granularity). Addresses between 4GB and 1TB are marked for hugepage iff
the low bit in the "high areas" bitmap is set. Higher addresses are marked
for hugepage iff their bit in the "high areas" bitmap is set (1TB
granularity).
To avoid conflicts, this patch must be applied on top of BenH's pending
patch for 64k base page size [0]. As such, this patch also addresses a
hugepage problem introduced by that patch. That patch allows hugepages of
1MB in size on hardware which supports it, however, that won't work when
using 4k pages (4 level pagetable), because in that case hugepage PTEs are
stored at the PMD level, and each PMD entry maps 2MB. This patch simply
disallows hugepages in that case (we can do something cleverer to re-enable
them some other day).
Built, booted, and a handful of hugepage related tests passed on POWER5
LPAR (both ARCH=powerpc and ARCH=ppc64).
[0] http://gate.crashing.org/~benh/ppc64-64k-pages.diff
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-07 11:57:52 +03:00
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blt 5f
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2007-05-08 10:27:27 +04:00
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ld r9,PACAHIGHSLICEPSIZE(r13)
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srdi r11,r10,(SLICE_HIGH_SHIFT - SLICE_LOW_SHIFT - 2)
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andi. r11,r11,0x3c
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[PATCH] ppc64: Fix bug in SLB miss handler for hugepages
This patch, however, should be applied on top of the 64k-page-size patch to
fix some problems with hugepage (some pre-existing, another introduced by
this patch).
The patch fixes a bug in the SLB miss handler for hugepages on ppc64
introduced by the dynamic hugepage patch (commit id
c594adad5653491813959277fb87a2fef54c4e05) due to a misunderstanding of the
srd instruction's behaviour (mea culpa). The problem arises when a 64-bit
process maps some hugepages in the low 4GB of the address space (unusual).
In this case, as well as the 256M segment in question being marked for
hugepages, other segments at 32G intervals will be incorrectly marked for
hugepages.
In the process, this patch tweaks the semantics of the hugepage bitmaps to
be more sensible. Previously, an address below 4G was marked for hugepages
if the appropriate segment bit in the "low areas" bitmask was set *or* if
the low bit in the "high areas" bitmap was set (which would mark all
addresses below 1TB for hugepage). With this patch, any given address is
governed by a single bitmap. Addresses below 4GB are marked for hugepage
if and only if their bit is set in the "low areas" bitmap (256M
granularity). Addresses between 4GB and 1TB are marked for hugepage iff
the low bit in the "high areas" bitmap is set. Higher addresses are marked
for hugepage iff their bit in the "high areas" bitmap is set (1TB
granularity).
To avoid conflicts, this patch must be applied on top of BenH's pending
patch for 64k base page size [0]. As such, this patch also addresses a
hugepage problem introduced by that patch. That patch allows hugepages of
1MB in size on hardware which supports it, however, that won't work when
using 4k pages (4 level pagetable), because in that case hugepage PTEs are
stored at the PMD level, and each PMD entry maps 2MB. This patch simply
disallows hugepages in that case (we can do something cleverer to re-enable
them some other day).
Built, booted, and a handful of hugepage related tests passed on POWER5
LPAR (both ARCH=powerpc and ARCH=ppc64).
[0] http://gate.crashing.org/~benh/ppc64-64k-pages.diff
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-11-07 11:57:52 +03:00
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2007-05-08 10:27:27 +04:00
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5: /* Extract the psize and multiply to get an array offset */
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srd r9,r9,r11
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andi. r9,r9,0xf
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mulli r9,r9,MMUPSIZEDEFSIZE
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2005-08-11 10:55:21 +04:00
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2007-05-08 10:27:27 +04:00
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/* Now get to the array and obtain the sllp
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*/
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ld r11,PACATOC(r13)
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ld r11,mmu_psize_defs@got(r11)
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add r11,r11,r9
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ld r11,MMUPSIZESLLP(r11)
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ori r11,r11,SLB_VSID_USER
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#else
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/* paca context sllp already contains the SLB_VSID_USER bits */
|
2006-06-15 04:45:18 +04:00
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lhz r11,PACACONTEXTSLLP(r13)
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2007-05-08 10:27:27 +04:00
|
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#endif /* CONFIG_PPC_MM_SLICES */
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2005-11-07 03:06:55 +03:00
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ld r9,PACACONTEXTID(r13)
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2007-10-11 14:37:10 +04:00
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BEGIN_FTR_SECTION
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cmpldi r10,0x1000
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END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
|
2005-11-07 03:06:55 +03:00
|
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rldimi r10,r9,USER_ESID_BITS,0
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2007-10-11 14:37:10 +04:00
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BEGIN_FTR_SECTION
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bge slb_finish_load_1T
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END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
|
2005-11-07 03:06:55 +03:00
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b slb_finish_load
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8: /* invalid EA */
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li r10,0 /* BAD_VSID */
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li r11,SLB_VSID_USER /* flags don't much matter */
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b slb_finish_load
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#ifdef __DISABLED__
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/* void slb_allocate_user(unsigned long ea);
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*
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* Create an SLB entry for the given EA (user or kernel).
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|
* r3 = faulting address, r13 = PACA
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* r9, r10, r11 are clobbered by this function
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* No other registers are examined or changed.
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*
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* It is called with translation enabled in order to be able to walk the
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* page tables. This is not currently used.
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*/
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_GLOBAL(slb_allocate_user)
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/* r3 = faulting address */
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srdi r10,r3,28 /* get esid */
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crset 4*cr7+lt /* set "user" flag for later */
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/* check if we fit in the range covered by the pagetables*/
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srdi. r9,r3,PGTABLE_EADDR_SIZE
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crnot 4*cr0+eq,4*cr0+eq
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|
|
beqlr
|
2005-04-17 02:20:36 +04:00
|
|
|
|
2005-11-07 03:06:55 +03:00
|
|
|
/* now we need to get to the page tables in order to get the page
|
|
|
|
|
* size encoding from the PMD. In the future, we'll be able to deal
|
|
|
|
|
* with 1T segments too by getting the encoding from the PGD instead
|
|
|
|
|
*/
|
|
|
|
|
ld r9,PACAPGDIR(r13)
|
|
|
|
|
cmpldi cr0,r9,0
|
|
|
|
|
beqlr
|
|
|
|
|
rlwinm r11,r10,8,25,28
|
|
|
|
|
ldx r9,r9,r11 /* get pgd_t */
|
|
|
|
|
cmpldi cr0,r9,0
|
|
|
|
|
beqlr
|
|
|
|
|
rlwinm r11,r10,3,17,28
|
|
|
|
|
ldx r9,r9,r11 /* get pmd_t */
|
|
|
|
|
cmpldi cr0,r9,0
|
|
|
|
|
beqlr
|
|
|
|
|
|
|
|
|
|
/* build vsid flags */
|
|
|
|
|
andi. r11,r9,SLB_VSID_LLP
|
|
|
|
|
ori r11,r11,SLB_VSID_USER
|
|
|
|
|
|
|
|
|
|
/* get context to calculate proto-VSID */
|
2005-08-31 08:34:05 +04:00
|
|
|
ld r9,PACACONTEXTID(r13)
|
2005-11-07 03:06:55 +03:00
|
|
|
rldimi r10,r9,USER_ESID_BITS,0
|
|
|
|
|
|
|
|
|
|
/* fall through slb_finish_load */
|
|
|
|
|
|
|
|
|
|
#endif /* __DISABLED__ */
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
|
|
2005-11-07 03:06:55 +03:00
|
|
|
/*
|
|
|
|
|
* Finish loading of an SLB entry and return
|
|
|
|
|
*
|
2005-12-05 19:24:33 +03:00
|
|
|
* r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9, cr7 = <> PAGE_OFFSET
|
2005-11-07 03:06:55 +03:00
|
|
|
*/
|
|
|
|
|
slb_finish_load:
|
2007-10-11 14:37:10 +04:00
|
|
|
ASM_VSID_SCRAMBLE(r10,r9,256M)
|
2005-11-07 03:06:55 +03:00
|
|
|
rldimi r11,r10,SLB_VSID_SHIFT,16 /* combine VSID and flags */
|
|
|
|
|
|
|
|
|
|
/* r3 = EA, r11 = VSID data */
|
|
|
|
|
/*
|
|
|
|
|
* Find a slot, round robin. Previously we tried to find a
|
|
|
|
|
* free slot first but that took too long. Unfortunately we
|
|
|
|
|
* dont have any LRU information to help us choose a slot.
|
|
|
|
|
*/
|
|
|
|
|
#ifdef CONFIG_PPC_ISERIES
|
2006-09-25 12:19:00 +04:00
|
|
|
BEGIN_FW_FTR_SECTION
|
2005-11-07 03:06:55 +03:00
|
|
|
/*
|
|
|
|
|
* On iSeries, the "bolted" stack segment can be cast out on
|
|
|
|
|
* shared processor switch so we need to check for a miss on
|
|
|
|
|
* it and restore it to the right slot.
|
|
|
|
|
*/
|
|
|
|
|
ld r9,PACAKSAVE(r13)
|
|
|
|
|
clrrdi r9,r9,28
|
|
|
|
|
clrrdi r3,r3,28
|
|
|
|
|
li r10,SLB_NUM_BOLTED-1 /* Stack goes in last bolted slot */
|
|
|
|
|
cmpld r9,r3
|
|
|
|
|
beq 3f
|
2006-09-25 12:19:00 +04:00
|
|
|
END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
|
2005-11-07 03:06:55 +03:00
|
|
|
#endif /* CONFIG_PPC_ISERIES */
|
|
|
|
|
|
2007-10-11 14:37:10 +04:00
|
|
|
7: ld r10,PACASTABRR(r13)
|
2005-11-07 03:06:55 +03:00
|
|
|
addi r10,r10,1
|
2007-12-06 09:24:48 +03:00
|
|
|
/* This gets soft patched on boot. */
|
|
|
|
|
_GLOBAL(slb_compare_rr_to_size)
|
|
|
|
|
cmpldi r10,0
|
2005-11-07 03:06:55 +03:00
|
|
|
|
|
|
|
|
blt+ 4f
|
|
|
|
|
li r10,SLB_NUM_BOLTED
|
|
|
|
|
|
|
|
|
|
4:
|
|
|
|
|
std r10,PACASTABRR(r13)
|
|
|
|
|
|
|
|
|
|
3:
|
|
|
|
|
rldimi r3,r10,0,36 /* r3= EA[0:35] | entry */
|
|
|
|
|
oris r10,r3,SLB_ESID_V@h /* r3 |= SLB_ESID_V */
|
|
|
|
|
|
|
|
|
|
/* r3 = ESID data, r11 = VSID data */
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* No need for an isync before or after this slbmte. The exception
|
|
|
|
|
* we enter with and the rfid we exit with are context synchronizing.
|
|
|
|
|
*/
|
|
|
|
|
slbmte r11,r10
|
|
|
|
|
|
2005-11-07 03:06:55 +03:00
|
|
|
/* we're done for kernel addresses */
|
|
|
|
|
crclr 4*cr0+eq /* set result to "success" */
|
|
|
|
|
bgelr cr7
|
2005-04-17 02:20:36 +04:00
|
|
|
|
|
|
|
|
/* Update the slb cache */
|
|
|
|
|
lhz r3,PACASLBCACHEPTR(r13) /* offset = paca->slb_cache_ptr */
|
|
|
|
|
cmpldi r3,SLB_CACHE_ENTRIES
|
|
|
|
|
bge 1f
|
|
|
|
|
|
|
|
|
|
/* still room in the slb cache */
|
|
|
|
|
sldi r11,r3,1 /* r11 = offset * sizeof(u16) */
|
|
|
|
|
rldicl r10,r10,36,28 /* get low 16 bits of the ESID */
|
|
|
|
|
add r11,r11,r13 /* r11 = (u16 *)paca + offset */
|
|
|
|
|
sth r10,PACASLBCACHE(r11) /* paca->slb_cache[offset] = esid */
|
|
|
|
|
addi r3,r3,1 /* offset++ */
|
|
|
|
|
b 2f
|
|
|
|
|
1: /* offset >= SLB_CACHE_ENTRIES */
|
|
|
|
|
li r3,SLB_CACHE_ENTRIES+1
|
|
|
|
|
2:
|
|
|
|
|
sth r3,PACASLBCACHEPTR(r13) /* paca->slb_cache_ptr = offset */
|
2005-11-07 03:06:55 +03:00
|
|
|
crclr 4*cr0+eq /* set result to "success" */
|
2005-04-17 02:20:36 +04:00
|
|
|
blr
|
|
|
|
|
|
2007-10-11 14:37:10 +04:00
|
|
|
/*
|
|
|
|
|
* Finish loading of a 1T SLB entry (for the kernel linear mapping) and return.
|
|
|
|
|
* We assume legacy iSeries will never have 1T segments.
|
|
|
|
|
*
|
|
|
|
|
* r3 = EA, r10 = proto-VSID, r11 = flags, clobbers r9
|
|
|
|
|
*/
|
|
|
|
|
slb_finish_load_1T:
|
|
|
|
|
srdi r10,r10,40-28 /* get 1T ESID */
|
|
|
|
|
ASM_VSID_SCRAMBLE(r10,r9,1T)
|
|
|
|
|
rldimi r11,r10,SLB_VSID_SHIFT_1T,16 /* combine VSID and flags */
|
|
|
|
|
li r10,MMU_SEGSIZE_1T
|
|
|
|
|
rldimi r11,r10,SLB_VSID_SSIZE_SHIFT,0 /* insert segment size */
|
|
|
|
|
|
|
|
|
|
/* r3 = EA, r11 = VSID data */
|
|
|
|
|
clrrdi r3,r3,SID_SHIFT_1T /* clear out non-ESID bits */
|
|
|
|
|
b 7b
|
|
|
|
|
|
