2005-11-10 17:26:51 +03:00
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/*
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* linux/arch/arm/mach-omap2/io.c
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*
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* OMAP2 I/O mapping code
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*
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* Copyright (C) 2005 Nokia Corporation
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2009-05-29 01:16:04 +04:00
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* Copyright (C) 2007-2009 Texas Instruments
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2008-10-06 16:49:36 +04:00
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*
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* Author:
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* Juha Yrjola <juha.yrjola@nokia.com>
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* Syed Khasim <x0khasim@ti.com>
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2005-11-10 17:26:51 +03:00
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*
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2009-05-29 01:16:04 +04:00
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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2005-11-10 17:26:51 +03:00
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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2008-09-06 15:10:45 +04:00
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#include <linux/io.h>
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2009-06-20 05:08:25 +04:00
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#include <linux/clk.h>
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2005-11-10 17:26:51 +03:00
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2006-04-02 20:46:27 +04:00
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#include <asm/tlb.h>
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#include <asm/mach/map.h>
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2012-11-30 20:41:50 +04:00
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#include <linux/omap-dma.h>
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2012-02-24 22:34:35 +04:00
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2012-10-03 22:23:43 +04:00
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#include "omap_hwmod.h"
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2012-08-31 21:59:07 +04:00
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#include "soc.h"
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2012-02-24 22:34:35 +04:00
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#include "iomap.h"
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2011-03-17 00:25:45 +03:00
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#include "voltage.h"
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2010-12-22 07:05:16 +03:00
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#include "powerdomain.h"
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2010-12-22 07:05:15 +03:00
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#include "clockdomain.h"
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2011-11-11 01:45:17 +04:00
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#include "common.h"
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2012-05-29 13:56:41 +04:00
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#include "clock.h"
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2012-02-24 22:34:35 +04:00
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#include "clock2xxx.h"
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#include "clock3xxx.h"
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#include "clock44xx.h"
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2012-10-04 03:36:40 +04:00
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#include "omap-pm.h"
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2012-10-17 04:46:45 +04:00
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#include "sdrc.h"
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2012-10-30 06:50:21 +04:00
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#include "control.h"
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2012-10-15 23:50:46 +04:00
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#include "serial.h"
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2012-10-30 00:54:06 +04:00
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#include "sram.h"
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2012-10-30 06:56:29 +04:00
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#include "cm2xxx.h"
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#include "cm3xxx.h"
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2012-10-30 06:57:39 +04:00
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#include "prm.h"
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#include "cm.h"
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#include "prcm_mpu44xx.h"
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#include "prminst44xx.h"
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#include "cminst44xx.h"
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2012-11-22 03:15:16 +04:00
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#include "prm2xxx.h"
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#include "prm3xxx.h"
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#include "prm44xx.h"
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2009-09-03 21:14:05 +04:00
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ARM: OMAP: clocks: Delay clk inits atleast until slab is initialized
clk inits on OMAP happen quite early, even before slab is available.
The dependency comes from the fact that the timer init code starts to
use clocks and hwmod and we need clocks to be initialized by then.
There are various problems doing clk inits this early, one is,
not being able to do dynamic clk registrations and hence the
dependency on clk-private.h. The other is, inability to debug
early kernel crashes without enabling DEBUG_LL and earlyprintk.
Doing early clk init also exposed another instance of a kernel
panic due to a BUG() when CONFIG_DEBUG_SLAB is enabled.
[ 0.000000] Kernel BUG at c01174f8 [verbose debug info unavailable]
[ 0.000000] Internal error: Oops - BUG: 0 [#1] SMP ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 Not tainted (3.9.0-rc1-12179-g72d48f9 #6)
[ 0.000000] PC is at __kmalloc+0x1d4/0x248
[ 0.000000] LR is at __clk_init+0x2e0/0x364
[ 0.000000] pc : [<c01174f8>] lr : [<c0441f54>] psr: 600001d3
[ 0.000000] sp : c076ff28 ip : c065cefc fp : c0441f54
[ 0.000000] r10: 0000001c r9 : 000080d0 r8 : c076ffd4
[ 0.000000] r7 : c074b578 r6 : c0794d88 r5 : 00000040 r4 : 00000000
[ 0.000000] r3 : 00000000 r2 : c07cac70 r1 : 000080d0 r0 : 0000001c
[ 0.000000] Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel
[ 0.000000] Control: 10c53c7d Table: 8000404a DAC: 00000017
[ 0.000000] Process swapper (pid: 0, stack limit = 0xc076e240)
[ 0.000000] Stack: (0xc076ff28 to 0xc0770000)
[ 0.000000] ff20: 22222222 c0794ec8 c06546e8 00000000 00000040 c0794d88
[ 0.000000] ff40: c074b578 c076ffd4 c07951c8 c076e000 00000000 c0441f54 c074b578 c076ffd4
[ 0.000000] ff60: c0793828 00000040 c0794d88 c074b578 c076ffd4 c0776900 c076e000 c07272ac
[ 0.000000] ff80: 2f800000 c074c968 c07f93d0 c0719780 c076ffa0 c076ff98 00000000 00000000
[ 0.000000] ffa0: 00000000 00000000 00000000 00000001 c074cd6c c077b1ec 8000406a c0715724
[ 0.000000] ffc0: 00000000 00000000 00000000 00000000 00000000 c074c968 10c53c7d c0776974
[ 0.000000] ffe0: c074cd6c c077b1ec 8000406a 411fc092 00000000 80008074 00000000 00000000
[ 0.000000] [<c01174f8>] (__kmalloc+0x1d4/0x248) from [<c0441f54>] (__clk_init+0x2e0/0x364)
[ 0.000000] [<c0441f54>] (__clk_init+0x2e0/0x364) from [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140)
[ 0.000000] [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140) from [<c0719780>] (setup_arch+0x15c/0x284)
[ 0.000000] [<c0719780>] (setup_arch+0x15c/0x284) from [<c0715724>] (start_kernel+0x7c/0x334)
[ 0.000000] [<c0715724>] (start_kernel+0x7c/0x334) from [<80008074>] (0x80008074)
[ 0.000000] Code: e5883004 e1a00006 e28dd00c e8bd8ff0 (e7f001f2)
[ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
[ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
It was a know issue, that slab allocations would fail when common
clock core tries to cache parent pointers for mux clocks on OMAP,
and hence a patch 'clk: Allow late cache allocation for clk->parents,
commit 7975059d' was added to work this problem around.
A BUG() within kmalloc() with CONFIG_DEBUG_SLAB enabled was completely
overlooked causing this regression.
More details on the issue reported can be found here,
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg85932.html
With all these issues around clk inits happening way too early, it
makes sense to at least move them to a point where dynamic memory
allocations are possible. So move them to a point just before the
timer code starts using clocks and hwmod.
This should at least pave way for clk inits on OMAP moving to dynamic
clock registrations instead of using the static macros defined in
clk-private.h.
The issue with kernel panic while CONFIG_DEBUG_SLAB is enabled
was reported by Piotr Haber and Tony Lindgren and this patch
fixes the reported issue as well.
Reported-by: Piotr Haber <phaber@broadcom.com>
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Paul Walmsley <paul@pwsan.com>
Cc: stable@vger.kernel.org # v3.8
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-03-21 15:04:52 +04:00
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/*
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* omap_clk_init: points to a function that does the SoC-specific
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* clock initializations
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*/
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int (*omap_clk_init)(void);
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2005-11-10 17:26:51 +03:00
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/*
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* The machine specific code may provide the extra mapping besides the
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* default mapping provided here.
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*/
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2008-10-09 18:51:41 +04:00
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2012-03-06 23:49:22 +04:00
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#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
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2008-10-09 18:51:41 +04:00
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static struct map_desc omap24xx_io_desc[] __initdata = {
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2005-11-10 17:26:51 +03:00
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{
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.virtual = L3_24XX_VIRT,
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.pfn = __phys_to_pfn(L3_24XX_PHYS),
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.length = L3_24XX_SIZE,
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.type = MT_DEVICE
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},
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2008-02-21 02:30:06 +03:00
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{
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2008-10-09 18:51:41 +04:00
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.virtual = L4_24XX_VIRT,
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.pfn = __phys_to_pfn(L4_24XX_PHYS),
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.length = L4_24XX_SIZE,
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.type = MT_DEVICE
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2008-02-21 02:30:06 +03:00
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},
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2008-10-09 18:51:41 +04:00
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};
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2011-01-28 03:39:40 +03:00
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#ifdef CONFIG_SOC_OMAP2420
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2008-10-09 18:51:41 +04:00
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static struct map_desc omap242x_io_desc[] __initdata = {
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{
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2010-01-09 01:23:05 +03:00
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.virtual = DSP_MEM_2420_VIRT,
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.pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
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.length = DSP_MEM_2420_SIZE,
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2008-10-09 18:51:41 +04:00
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.type = MT_DEVICE
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},
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{
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2010-01-09 01:23:05 +03:00
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.virtual = DSP_IPI_2420_VIRT,
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.pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
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.length = DSP_IPI_2420_SIZE,
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2008-10-09 18:51:41 +04:00
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.type = MT_DEVICE
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2008-02-21 02:30:06 +03:00
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},
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2008-10-09 18:51:41 +04:00
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{
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2010-01-09 01:23:05 +03:00
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.virtual = DSP_MMU_2420_VIRT,
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.pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
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.length = DSP_MMU_2420_SIZE,
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2008-10-09 18:51:41 +04:00
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.type = MT_DEVICE
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},
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};
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#endif
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2011-01-28 03:39:40 +03:00
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#ifdef CONFIG_SOC_OMAP2430
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2008-10-09 18:51:41 +04:00
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static struct map_desc omap243x_io_desc[] __initdata = {
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2006-12-07 04:14:05 +03:00
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{
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.virtual = L4_WK_243X_VIRT,
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.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
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.length = L4_WK_243X_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP243X_GPMC_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
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.length = OMAP243X_GPMC_SIZE,
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.type = MT_DEVICE
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},
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2008-10-09 18:51:41 +04:00
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{
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.virtual = OMAP243X_SDRC_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
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.length = OMAP243X_SDRC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP243X_SMS_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
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.length = OMAP243X_SMS_SIZE,
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.type = MT_DEVICE
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},
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};
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2006-12-07 04:14:05 +03:00
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#endif
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#endif
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2008-10-09 18:51:41 +04:00
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2010-02-12 23:26:48 +03:00
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#ifdef CONFIG_ARCH_OMAP3
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2008-10-09 18:51:41 +04:00
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static struct map_desc omap34xx_io_desc[] __initdata = {
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2005-11-10 17:26:51 +03:00
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{
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2008-10-09 18:51:41 +04:00
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.virtual = L3_34XX_VIRT,
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.pfn = __phys_to_pfn(L3_34XX_PHYS),
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.length = L3_34XX_SIZE,
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2006-12-08 00:58:10 +03:00
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.type = MT_DEVICE
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},
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{
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2008-10-09 18:51:41 +04:00
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.virtual = L4_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_34XX_PHYS),
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.length = L4_34XX_SIZE,
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2006-12-08 00:58:10 +03:00
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.type = MT_DEVICE
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},
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2008-10-09 18:51:41 +04:00
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{
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.virtual = OMAP34XX_GPMC_VIRT,
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.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
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.length = OMAP34XX_GPMC_SIZE,
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2005-11-10 17:26:51 +03:00
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.type = MT_DEVICE
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2008-10-09 18:51:41 +04:00
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},
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{
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.virtual = OMAP343X_SMS_VIRT,
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.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
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.length = OMAP343X_SMS_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP343X_SDRC_VIRT,
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.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
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.length = OMAP343X_SDRC_SIZE,
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2005-11-10 17:26:51 +03:00
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.type = MT_DEVICE
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2008-10-09 18:51:41 +04:00
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},
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{
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.virtual = L4_PER_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
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.length = L4_PER_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_EMU_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
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.length = L4_EMU_34XX_SIZE,
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.type = MT_DEVICE
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},
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2010-04-30 23:57:14 +04:00
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#if defined(CONFIG_DEBUG_LL) && \
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(defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
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{
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.virtual = ZOOM_UART_VIRT,
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.pfn = __phys_to_pfn(ZOOM_UART_BASE),
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.length = SZ_1M,
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.type = MT_DEVICE
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},
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#endif
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2005-11-10 17:26:51 +03:00
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};
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2008-10-09 18:51:41 +04:00
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#endif
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2011-02-16 19:31:39 +03:00
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2012-05-10 22:10:07 +04:00
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#ifdef CONFIG_SOC_TI81XX
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2011-12-13 22:46:44 +04:00
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static struct map_desc omapti81xx_io_desc[] __initdata = {
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2011-12-13 22:46:43 +04:00
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{
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.virtual = L4_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_34XX_PHYS),
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.length = L4_34XX_SIZE,
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.type = MT_DEVICE
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}
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};
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#endif
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2013-05-27 18:36:13 +04:00
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#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
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2011-12-13 22:46:43 +04:00
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static struct map_desc omapam33xx_io_desc[] __initdata = {
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2011-02-16 19:31:39 +03:00
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{
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.virtual = L4_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_34XX_PHYS),
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.length = L4_34XX_SIZE,
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.type = MT_DEVICE
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},
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2011-12-13 22:46:43 +04:00
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{
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.virtual = L4_WK_AM33XX_VIRT,
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.pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
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.length = L4_WK_AM33XX_SIZE,
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.type = MT_DEVICE
|
|
|
|
|
}
|
2011-02-16 19:31:39 +03:00
|
|
|
};
|
|
|
|
|
#endif
|
|
|
|
|
|
2009-05-29 01:16:04 +04:00
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
|
|
|
static struct map_desc omap44xx_io_desc[] __initdata = {
|
|
|
|
|
{
|
|
|
|
|
.virtual = L3_44XX_VIRT,
|
|
|
|
|
.pfn = __phys_to_pfn(L3_44XX_PHYS),
|
|
|
|
|
.length = L3_44XX_SIZE,
|
|
|
|
|
.type = MT_DEVICE,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.virtual = L4_44XX_VIRT,
|
|
|
|
|
.pfn = __phys_to_pfn(L4_44XX_PHYS),
|
|
|
|
|
.length = L4_44XX_SIZE,
|
|
|
|
|
.type = MT_DEVICE,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.virtual = L4_PER_44XX_VIRT,
|
|
|
|
|
.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
|
|
|
|
|
.length = L4_PER_44XX_SIZE,
|
|
|
|
|
.type = MT_DEVICE,
|
|
|
|
|
},
|
2011-06-26 05:04:31 +04:00
|
|
|
#ifdef CONFIG_OMAP4_ERRATA_I688
|
|
|
|
|
{
|
|
|
|
|
.virtual = OMAP4_SRAM_VA,
|
|
|
|
|
.pfn = __phys_to_pfn(OMAP4_SRAM_PA),
|
|
|
|
|
.length = PAGE_SIZE,
|
|
|
|
|
.type = MT_MEMORY_SO,
|
|
|
|
|
},
|
|
|
|
|
#endif
|
|
|
|
|
|
2009-05-29 01:16:04 +04:00
|
|
|
};
|
|
|
|
|
#endif
|
2005-11-10 17:26:51 +03:00
|
|
|
|
2012-06-05 14:51:32 +04:00
|
|
|
#ifdef CONFIG_SOC_OMAP5
|
|
|
|
|
static struct map_desc omap54xx_io_desc[] __initdata = {
|
|
|
|
|
{
|
|
|
|
|
.virtual = L3_54XX_VIRT,
|
|
|
|
|
.pfn = __phys_to_pfn(L3_54XX_PHYS),
|
|
|
|
|
.length = L3_54XX_SIZE,
|
|
|
|
|
.type = MT_DEVICE,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.virtual = L4_54XX_VIRT,
|
|
|
|
|
.pfn = __phys_to_pfn(L4_54XX_PHYS),
|
|
|
|
|
.length = L4_54XX_SIZE,
|
|
|
|
|
.type = MT_DEVICE,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.virtual = L4_WK_54XX_VIRT,
|
|
|
|
|
.pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
|
|
|
|
|
.length = L4_WK_54XX_SIZE,
|
|
|
|
|
.type = MT_DEVICE,
|
|
|
|
|
},
|
|
|
|
|
{
|
|
|
|
|
.virtual = L4_PER_54XX_VIRT,
|
|
|
|
|
.pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
|
|
|
|
|
.length = L4_PER_54XX_SIZE,
|
|
|
|
|
.type = MT_DEVICE,
|
|
|
|
|
},
|
2013-02-15 16:35:49 +04:00
|
|
|
#ifdef CONFIG_OMAP4_ERRATA_I688
|
|
|
|
|
{
|
|
|
|
|
.virtual = OMAP4_SRAM_VA,
|
|
|
|
|
.pfn = __phys_to_pfn(OMAP4_SRAM_PA),
|
|
|
|
|
.length = PAGE_SIZE,
|
|
|
|
|
.type = MT_MEMORY_SO,
|
|
|
|
|
},
|
|
|
|
|
#endif
|
2012-06-05 14:51:32 +04:00
|
|
|
};
|
|
|
|
|
#endif
|
|
|
|
|
|
2011-01-28 03:39:40 +03:00
|
|
|
#ifdef CONFIG_SOC_OMAP2420
|
2012-10-30 06:50:21 +04:00
|
|
|
void __init omap242x_map_io(void)
|
2005-11-10 17:26:51 +03:00
|
|
|
{
|
2008-10-09 18:51:41 +04:00
|
|
|
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
|
|
|
|
|
iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
|
2010-02-12 23:26:47 +03:00
|
|
|
}
|
2008-10-09 18:51:41 +04:00
|
|
|
#endif
|
|
|
|
|
|
2011-01-28 03:39:40 +03:00
|
|
|
#ifdef CONFIG_SOC_OMAP2430
|
2012-10-30 06:50:21 +04:00
|
|
|
void __init omap243x_map_io(void)
|
2010-02-12 23:26:47 +03:00
|
|
|
{
|
2008-10-09 18:51:41 +04:00
|
|
|
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
|
|
|
|
|
iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
|
2010-02-12 23:26:47 +03:00
|
|
|
}
|
2008-10-09 18:51:41 +04:00
|
|
|
#endif
|
|
|
|
|
|
2010-02-12 23:26:48 +03:00
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
2012-10-30 06:50:21 +04:00
|
|
|
void __init omap3_map_io(void)
|
2010-02-12 23:26:47 +03:00
|
|
|
{
|
2008-10-09 18:51:41 +04:00
|
|
|
iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
|
2010-02-12 23:26:47 +03:00
|
|
|
}
|
2008-10-09 18:51:41 +04:00
|
|
|
#endif
|
2006-04-02 20:46:27 +04:00
|
|
|
|
2012-05-10 22:10:07 +04:00
|
|
|
#ifdef CONFIG_SOC_TI81XX
|
2012-10-30 06:50:21 +04:00
|
|
|
void __init ti81xx_map_io(void)
|
2011-02-16 19:31:39 +03:00
|
|
|
{
|
2011-12-13 22:46:44 +04:00
|
|
|
iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
|
2011-02-16 19:31:39 +03:00
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2013-05-27 18:36:13 +04:00
|
|
|
#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
|
2012-10-30 06:50:21 +04:00
|
|
|
void __init am33xx_map_io(void)
|
2011-02-16 19:31:39 +03:00
|
|
|
{
|
2011-12-13 22:46:43 +04:00
|
|
|
iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
|
2011-02-16 19:31:39 +03:00
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2010-02-12 23:26:47 +03:00
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
2012-10-30 06:50:21 +04:00
|
|
|
void __init omap4_map_io(void)
|
2010-02-12 23:26:47 +03:00
|
|
|
{
|
2009-05-29 01:16:04 +04:00
|
|
|
iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
|
2012-02-02 18:03:55 +04:00
|
|
|
omap_barriers_init();
|
2006-04-02 20:46:27 +04:00
|
|
|
}
|
2010-02-12 23:26:47 +03:00
|
|
|
#endif
|
2006-04-02 20:46:27 +04:00
|
|
|
|
2012-06-05 14:51:32 +04:00
|
|
|
#ifdef CONFIG_SOC_OMAP5
|
2012-10-30 06:50:21 +04:00
|
|
|
void __init omap5_map_io(void)
|
2012-06-05 14:51:32 +04:00
|
|
|
{
|
|
|
|
|
iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
|
2013-02-15 16:35:49 +04:00
|
|
|
omap_barriers_init();
|
2012-06-05 14:51:32 +04:00
|
|
|
}
|
|
|
|
|
#endif
|
2009-06-20 05:08:25 +04:00
|
|
|
/*
|
|
|
|
|
* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
|
|
|
|
|
*
|
|
|
|
|
* Sets the CORE DPLL3 M2 divider to the same value that it's at
|
|
|
|
|
* currently. This has the effect of setting the SDRC SDRAM AC timing
|
|
|
|
|
* registers to the values currently defined by the kernel. Currently
|
|
|
|
|
* only defined for OMAP3; will return 0 if called on OMAP2. Returns
|
|
|
|
|
* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
|
|
|
|
|
* or passes along the return value of clk_set_rate().
|
|
|
|
|
*/
|
|
|
|
|
static int __init _omap2_init_reprogram_sdrc(void)
|
|
|
|
|
{
|
|
|
|
|
struct clk *dpll3_m2_ck;
|
|
|
|
|
int v = -EINVAL;
|
|
|
|
|
long rate;
|
|
|
|
|
|
|
|
|
|
if (!cpu_is_omap34xx())
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
|
|
dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
|
2010-11-30 17:17:58 +03:00
|
|
|
if (IS_ERR(dpll3_m2_ck))
|
2009-06-20 05:08:25 +04:00
|
|
|
return -EINVAL;
|
|
|
|
|
|
|
|
|
|
rate = clk_get_rate(dpll3_m2_ck);
|
|
|
|
|
pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
|
|
|
|
|
v = clk_set_rate(dpll3_m2_ck, rate);
|
|
|
|
|
if (v)
|
|
|
|
|
pr_err("dpll3_m2_clk rate change failed: %d\n", v);
|
|
|
|
|
|
|
|
|
|
clk_put(dpll3_m2_ck);
|
|
|
|
|
|
|
|
|
|
return v;
|
|
|
|
|
}
|
|
|
|
|
|
2010-12-14 22:42:35 +03:00
|
|
|
static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
|
|
|
|
|
{
|
|
|
|
|
return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
|
|
|
|
|
}
|
|
|
|
|
|
2011-10-05 05:26:28 +04:00
|
|
|
static void __init omap_hwmod_init_postsetup(void)
|
|
|
|
|
{
|
|
|
|
|
u8 postsetup_state;
|
2010-12-14 22:42:35 +03:00
|
|
|
|
|
|
|
|
/* Set the default postsetup state for all hwmods */
|
|
|
|
|
#ifdef CONFIG_PM_RUNTIME
|
|
|
|
|
postsetup_state = _HWMOD_STATE_IDLE;
|
|
|
|
|
#else
|
|
|
|
|
postsetup_state = _HWMOD_STATE_ENABLED;
|
|
|
|
|
#endif
|
|
|
|
|
omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
|
2010-05-12 19:54:36 +04:00
|
|
|
|
2010-12-09 18:13:48 +03:00
|
|
|
omap_pm_if_early_init();
|
OMAP2+: io: split omap2_init_common_hw()
Split omap2_init_common_hw() into two functions. The first,
omap2_init_common_infrastructure(), initializes the hwmod code and
data, the OMAP PM code, and the clock code and data. The second,
omap2_init_common_devices(), handles any other early device
initialization that, for whatever reason, has not been or cannot be
moved to initcalls or early platform devices.
This patch is required for the hwmod postsetup patch, which allows
board files to change the state that hwmods should be placed into at
the conclusion of the hwmod _setup() function. For example, for a
board whose creators wish to ensure watchdog coverage across the
entire kernel boot process, code to change the watchdog's postsetup
state will be added in the board-*.c file between the
omap2_init_common_infrastructure() and omap2_init_common_devices() function
calls.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
2010-12-22 01:25:10 +03:00
|
|
|
}
|
|
|
|
|
|
2013-07-05 18:20:17 +04:00
|
|
|
static void __init __maybe_unused omap_common_late_init(void)
|
2013-02-14 15:55:22 +04:00
|
|
|
{
|
|
|
|
|
omap_mux_late_init();
|
|
|
|
|
omap2_common_pm_late_init();
|
2013-02-14 15:55:24 +04:00
|
|
|
omap_soc_device_init();
|
2013-02-14 15:55:22 +04:00
|
|
|
}
|
|
|
|
|
|
2012-01-25 23:57:46 +04:00
|
|
|
#ifdef CONFIG_SOC_OMAP2420
|
2011-08-23 10:57:24 +04:00
|
|
|
void __init omap2420_init_early(void)
|
|
|
|
|
{
|
2012-10-30 06:50:21 +04:00
|
|
|
omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
|
|
|
|
|
omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
|
|
|
|
|
OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
|
|
|
|
|
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
|
|
|
|
|
NULL);
|
2012-10-30 06:57:39 +04:00
|
|
|
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
|
|
|
|
|
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
|
2011-12-19 14:20:15 +04:00
|
|
|
omap2xxx_check_revision();
|
2012-11-22 03:15:16 +04:00
|
|
|
omap2xxx_prm_init();
|
2012-10-30 06:56:29 +04:00
|
|
|
omap2xxx_cm_init();
|
2011-10-05 05:26:28 +04:00
|
|
|
omap2xxx_voltagedomains_init();
|
|
|
|
|
omap242x_powerdomains_init();
|
|
|
|
|
omap242x_clockdomains_init();
|
|
|
|
|
omap2420_hwmod_init();
|
|
|
|
|
omap_hwmod_init_postsetup();
|
ARM: OMAP: clocks: Delay clk inits atleast until slab is initialized
clk inits on OMAP happen quite early, even before slab is available.
The dependency comes from the fact that the timer init code starts to
use clocks and hwmod and we need clocks to be initialized by then.
There are various problems doing clk inits this early, one is,
not being able to do dynamic clk registrations and hence the
dependency on clk-private.h. The other is, inability to debug
early kernel crashes without enabling DEBUG_LL and earlyprintk.
Doing early clk init also exposed another instance of a kernel
panic due to a BUG() when CONFIG_DEBUG_SLAB is enabled.
[ 0.000000] Kernel BUG at c01174f8 [verbose debug info unavailable]
[ 0.000000] Internal error: Oops - BUG: 0 [#1] SMP ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 Not tainted (3.9.0-rc1-12179-g72d48f9 #6)
[ 0.000000] PC is at __kmalloc+0x1d4/0x248
[ 0.000000] LR is at __clk_init+0x2e0/0x364
[ 0.000000] pc : [<c01174f8>] lr : [<c0441f54>] psr: 600001d3
[ 0.000000] sp : c076ff28 ip : c065cefc fp : c0441f54
[ 0.000000] r10: 0000001c r9 : 000080d0 r8 : c076ffd4
[ 0.000000] r7 : c074b578 r6 : c0794d88 r5 : 00000040 r4 : 00000000
[ 0.000000] r3 : 00000000 r2 : c07cac70 r1 : 000080d0 r0 : 0000001c
[ 0.000000] Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel
[ 0.000000] Control: 10c53c7d Table: 8000404a DAC: 00000017
[ 0.000000] Process swapper (pid: 0, stack limit = 0xc076e240)
[ 0.000000] Stack: (0xc076ff28 to 0xc0770000)
[ 0.000000] ff20: 22222222 c0794ec8 c06546e8 00000000 00000040 c0794d88
[ 0.000000] ff40: c074b578 c076ffd4 c07951c8 c076e000 00000000 c0441f54 c074b578 c076ffd4
[ 0.000000] ff60: c0793828 00000040 c0794d88 c074b578 c076ffd4 c0776900 c076e000 c07272ac
[ 0.000000] ff80: 2f800000 c074c968 c07f93d0 c0719780 c076ffa0 c076ff98 00000000 00000000
[ 0.000000] ffa0: 00000000 00000000 00000000 00000001 c074cd6c c077b1ec 8000406a c0715724
[ 0.000000] ffc0: 00000000 00000000 00000000 00000000 00000000 c074c968 10c53c7d c0776974
[ 0.000000] ffe0: c074cd6c c077b1ec 8000406a 411fc092 00000000 80008074 00000000 00000000
[ 0.000000] [<c01174f8>] (__kmalloc+0x1d4/0x248) from [<c0441f54>] (__clk_init+0x2e0/0x364)
[ 0.000000] [<c0441f54>] (__clk_init+0x2e0/0x364) from [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140)
[ 0.000000] [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140) from [<c0719780>] (setup_arch+0x15c/0x284)
[ 0.000000] [<c0719780>] (setup_arch+0x15c/0x284) from [<c0715724>] (start_kernel+0x7c/0x334)
[ 0.000000] [<c0715724>] (start_kernel+0x7c/0x334) from [<80008074>] (0x80008074)
[ 0.000000] Code: e5883004 e1a00006 e28dd00c e8bd8ff0 (e7f001f2)
[ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
[ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
It was a know issue, that slab allocations would fail when common
clock core tries to cache parent pointers for mux clocks on OMAP,
and hence a patch 'clk: Allow late cache allocation for clk->parents,
commit 7975059d' was added to work this problem around.
A BUG() within kmalloc() with CONFIG_DEBUG_SLAB enabled was completely
overlooked causing this regression.
More details on the issue reported can be found here,
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg85932.html
With all these issues around clk inits happening way too early, it
makes sense to at least move them to a point where dynamic memory
allocations are possible. So move them to a point just before the
timer code starts using clocks and hwmod.
This should at least pave way for clk inits on OMAP moving to dynamic
clock registrations instead of using the static macros defined in
clk-private.h.
The issue with kernel panic while CONFIG_DEBUG_SLAB is enabled
was reported by Piotr Haber and Tony Lindgren and this patch
fixes the reported issue as well.
Reported-by: Piotr Haber <phaber@broadcom.com>
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Paul Walmsley <paul@pwsan.com>
Cc: stable@vger.kernel.org # v3.8
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-03-21 15:04:52 +04:00
|
|
|
omap_clk_init = omap2420_clk_init;
|
2011-08-23 10:57:24 +04:00
|
|
|
}
|
2012-04-26 12:06:50 +04:00
|
|
|
|
|
|
|
|
void __init omap2420_init_late(void)
|
|
|
|
|
{
|
2013-02-14 15:55:22 +04:00
|
|
|
omap_common_late_init();
|
2012-04-26 12:06:50 +04:00
|
|
|
omap2_pm_init();
|
2012-06-01 12:32:49 +04:00
|
|
|
omap2_clk_enable_autoidle_all();
|
2012-04-26 12:06:50 +04:00
|
|
|
}
|
2012-01-25 23:57:46 +04:00
|
|
|
#endif
|
2011-08-23 10:57:24 +04:00
|
|
|
|
2012-01-25 23:57:46 +04:00
|
|
|
#ifdef CONFIG_SOC_OMAP2430
|
2011-08-23 10:57:24 +04:00
|
|
|
void __init omap2430_init_early(void)
|
|
|
|
|
{
|
2012-10-30 06:50:21 +04:00
|
|
|
omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
|
|
|
|
|
omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
|
|
|
|
|
OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
|
|
|
|
|
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
|
|
|
|
|
NULL);
|
2012-10-30 06:57:39 +04:00
|
|
|
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
|
|
|
|
|
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
|
2011-12-19 14:20:15 +04:00
|
|
|
omap2xxx_check_revision();
|
2012-11-22 03:15:16 +04:00
|
|
|
omap2xxx_prm_init();
|
2012-10-30 06:56:29 +04:00
|
|
|
omap2xxx_cm_init();
|
2011-10-05 05:26:28 +04:00
|
|
|
omap2xxx_voltagedomains_init();
|
|
|
|
|
omap243x_powerdomains_init();
|
|
|
|
|
omap243x_clockdomains_init();
|
|
|
|
|
omap2430_hwmod_init();
|
|
|
|
|
omap_hwmod_init_postsetup();
|
ARM: OMAP: clocks: Delay clk inits atleast until slab is initialized
clk inits on OMAP happen quite early, even before slab is available.
The dependency comes from the fact that the timer init code starts to
use clocks and hwmod and we need clocks to be initialized by then.
There are various problems doing clk inits this early, one is,
not being able to do dynamic clk registrations and hence the
dependency on clk-private.h. The other is, inability to debug
early kernel crashes without enabling DEBUG_LL and earlyprintk.
Doing early clk init also exposed another instance of a kernel
panic due to a BUG() when CONFIG_DEBUG_SLAB is enabled.
[ 0.000000] Kernel BUG at c01174f8 [verbose debug info unavailable]
[ 0.000000] Internal error: Oops - BUG: 0 [#1] SMP ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 Not tainted (3.9.0-rc1-12179-g72d48f9 #6)
[ 0.000000] PC is at __kmalloc+0x1d4/0x248
[ 0.000000] LR is at __clk_init+0x2e0/0x364
[ 0.000000] pc : [<c01174f8>] lr : [<c0441f54>] psr: 600001d3
[ 0.000000] sp : c076ff28 ip : c065cefc fp : c0441f54
[ 0.000000] r10: 0000001c r9 : 000080d0 r8 : c076ffd4
[ 0.000000] r7 : c074b578 r6 : c0794d88 r5 : 00000040 r4 : 00000000
[ 0.000000] r3 : 00000000 r2 : c07cac70 r1 : 000080d0 r0 : 0000001c
[ 0.000000] Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel
[ 0.000000] Control: 10c53c7d Table: 8000404a DAC: 00000017
[ 0.000000] Process swapper (pid: 0, stack limit = 0xc076e240)
[ 0.000000] Stack: (0xc076ff28 to 0xc0770000)
[ 0.000000] ff20: 22222222 c0794ec8 c06546e8 00000000 00000040 c0794d88
[ 0.000000] ff40: c074b578 c076ffd4 c07951c8 c076e000 00000000 c0441f54 c074b578 c076ffd4
[ 0.000000] ff60: c0793828 00000040 c0794d88 c074b578 c076ffd4 c0776900 c076e000 c07272ac
[ 0.000000] ff80: 2f800000 c074c968 c07f93d0 c0719780 c076ffa0 c076ff98 00000000 00000000
[ 0.000000] ffa0: 00000000 00000000 00000000 00000001 c074cd6c c077b1ec 8000406a c0715724
[ 0.000000] ffc0: 00000000 00000000 00000000 00000000 00000000 c074c968 10c53c7d c0776974
[ 0.000000] ffe0: c074cd6c c077b1ec 8000406a 411fc092 00000000 80008074 00000000 00000000
[ 0.000000] [<c01174f8>] (__kmalloc+0x1d4/0x248) from [<c0441f54>] (__clk_init+0x2e0/0x364)
[ 0.000000] [<c0441f54>] (__clk_init+0x2e0/0x364) from [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140)
[ 0.000000] [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140) from [<c0719780>] (setup_arch+0x15c/0x284)
[ 0.000000] [<c0719780>] (setup_arch+0x15c/0x284) from [<c0715724>] (start_kernel+0x7c/0x334)
[ 0.000000] [<c0715724>] (start_kernel+0x7c/0x334) from [<80008074>] (0x80008074)
[ 0.000000] Code: e5883004 e1a00006 e28dd00c e8bd8ff0 (e7f001f2)
[ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
[ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
It was a know issue, that slab allocations would fail when common
clock core tries to cache parent pointers for mux clocks on OMAP,
and hence a patch 'clk: Allow late cache allocation for clk->parents,
commit 7975059d' was added to work this problem around.
A BUG() within kmalloc() with CONFIG_DEBUG_SLAB enabled was completely
overlooked causing this regression.
More details on the issue reported can be found here,
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg85932.html
With all these issues around clk inits happening way too early, it
makes sense to at least move them to a point where dynamic memory
allocations are possible. So move them to a point just before the
timer code starts using clocks and hwmod.
This should at least pave way for clk inits on OMAP moving to dynamic
clock registrations instead of using the static macros defined in
clk-private.h.
The issue with kernel panic while CONFIG_DEBUG_SLAB is enabled
was reported by Piotr Haber and Tony Lindgren and this patch
fixes the reported issue as well.
Reported-by: Piotr Haber <phaber@broadcom.com>
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Paul Walmsley <paul@pwsan.com>
Cc: stable@vger.kernel.org # v3.8
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-03-21 15:04:52 +04:00
|
|
|
omap_clk_init = omap2430_clk_init;
|
2011-10-05 05:26:28 +04:00
|
|
|
}
|
2012-04-26 12:06:50 +04:00
|
|
|
|
|
|
|
|
void __init omap2430_init_late(void)
|
|
|
|
|
{
|
2013-02-14 15:55:22 +04:00
|
|
|
omap_common_late_init();
|
2012-04-26 12:06:50 +04:00
|
|
|
omap2_pm_init();
|
2012-06-01 12:32:49 +04:00
|
|
|
omap2_clk_enable_autoidle_all();
|
2012-04-26 12:06:50 +04:00
|
|
|
}
|
2011-10-13 20:14:10 +04:00
|
|
|
#endif
|
2011-10-05 05:26:28 +04:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Currently only board-omap3beagle.c should call this because of the
|
|
|
|
|
* same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
|
|
|
|
|
*/
|
2011-10-13 20:14:10 +04:00
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
2011-10-05 05:26:28 +04:00
|
|
|
void __init omap3_init_early(void)
|
|
|
|
|
{
|
2012-10-30 06:50:21 +04:00
|
|
|
omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
|
|
|
|
|
omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
|
|
|
|
|
OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
|
|
|
|
|
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
|
|
|
|
|
NULL);
|
2012-10-30 06:57:39 +04:00
|
|
|
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
|
|
|
|
|
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
|
2011-12-19 14:20:15 +04:00
|
|
|
omap3xxx_check_revision();
|
|
|
|
|
omap3xxx_check_features();
|
2012-11-22 03:15:16 +04:00
|
|
|
omap3xxx_prm_init();
|
2012-10-30 06:56:29 +04:00
|
|
|
omap3xxx_cm_init();
|
2011-10-05 05:26:28 +04:00
|
|
|
omap3xxx_voltagedomains_init();
|
|
|
|
|
omap3xxx_powerdomains_init();
|
|
|
|
|
omap3xxx_clockdomains_init();
|
|
|
|
|
omap3xxx_hwmod_init();
|
|
|
|
|
omap_hwmod_init_postsetup();
|
ARM: OMAP: clocks: Delay clk inits atleast until slab is initialized
clk inits on OMAP happen quite early, even before slab is available.
The dependency comes from the fact that the timer init code starts to
use clocks and hwmod and we need clocks to be initialized by then.
There are various problems doing clk inits this early, one is,
not being able to do dynamic clk registrations and hence the
dependency on clk-private.h. The other is, inability to debug
early kernel crashes without enabling DEBUG_LL and earlyprintk.
Doing early clk init also exposed another instance of a kernel
panic due to a BUG() when CONFIG_DEBUG_SLAB is enabled.
[ 0.000000] Kernel BUG at c01174f8 [verbose debug info unavailable]
[ 0.000000] Internal error: Oops - BUG: 0 [#1] SMP ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 Not tainted (3.9.0-rc1-12179-g72d48f9 #6)
[ 0.000000] PC is at __kmalloc+0x1d4/0x248
[ 0.000000] LR is at __clk_init+0x2e0/0x364
[ 0.000000] pc : [<c01174f8>] lr : [<c0441f54>] psr: 600001d3
[ 0.000000] sp : c076ff28 ip : c065cefc fp : c0441f54
[ 0.000000] r10: 0000001c r9 : 000080d0 r8 : c076ffd4
[ 0.000000] r7 : c074b578 r6 : c0794d88 r5 : 00000040 r4 : 00000000
[ 0.000000] r3 : 00000000 r2 : c07cac70 r1 : 000080d0 r0 : 0000001c
[ 0.000000] Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel
[ 0.000000] Control: 10c53c7d Table: 8000404a DAC: 00000017
[ 0.000000] Process swapper (pid: 0, stack limit = 0xc076e240)
[ 0.000000] Stack: (0xc076ff28 to 0xc0770000)
[ 0.000000] ff20: 22222222 c0794ec8 c06546e8 00000000 00000040 c0794d88
[ 0.000000] ff40: c074b578 c076ffd4 c07951c8 c076e000 00000000 c0441f54 c074b578 c076ffd4
[ 0.000000] ff60: c0793828 00000040 c0794d88 c074b578 c076ffd4 c0776900 c076e000 c07272ac
[ 0.000000] ff80: 2f800000 c074c968 c07f93d0 c0719780 c076ffa0 c076ff98 00000000 00000000
[ 0.000000] ffa0: 00000000 00000000 00000000 00000001 c074cd6c c077b1ec 8000406a c0715724
[ 0.000000] ffc0: 00000000 00000000 00000000 00000000 00000000 c074c968 10c53c7d c0776974
[ 0.000000] ffe0: c074cd6c c077b1ec 8000406a 411fc092 00000000 80008074 00000000 00000000
[ 0.000000] [<c01174f8>] (__kmalloc+0x1d4/0x248) from [<c0441f54>] (__clk_init+0x2e0/0x364)
[ 0.000000] [<c0441f54>] (__clk_init+0x2e0/0x364) from [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140)
[ 0.000000] [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140) from [<c0719780>] (setup_arch+0x15c/0x284)
[ 0.000000] [<c0719780>] (setup_arch+0x15c/0x284) from [<c0715724>] (start_kernel+0x7c/0x334)
[ 0.000000] [<c0715724>] (start_kernel+0x7c/0x334) from [<80008074>] (0x80008074)
[ 0.000000] Code: e5883004 e1a00006 e28dd00c e8bd8ff0 (e7f001f2)
[ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
[ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
It was a know issue, that slab allocations would fail when common
clock core tries to cache parent pointers for mux clocks on OMAP,
and hence a patch 'clk: Allow late cache allocation for clk->parents,
commit 7975059d' was added to work this problem around.
A BUG() within kmalloc() with CONFIG_DEBUG_SLAB enabled was completely
overlooked causing this regression.
More details on the issue reported can be found here,
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg85932.html
With all these issues around clk inits happening way too early, it
makes sense to at least move them to a point where dynamic memory
allocations are possible. So move them to a point just before the
timer code starts using clocks and hwmod.
This should at least pave way for clk inits on OMAP moving to dynamic
clock registrations instead of using the static macros defined in
clk-private.h.
The issue with kernel panic while CONFIG_DEBUG_SLAB is enabled
was reported by Piotr Haber and Tony Lindgren and this patch
fixes the reported issue as well.
Reported-by: Piotr Haber <phaber@broadcom.com>
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Paul Walmsley <paul@pwsan.com>
Cc: stable@vger.kernel.org # v3.8
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-03-21 15:04:52 +04:00
|
|
|
omap_clk_init = omap3xxx_clk_init;
|
2011-08-23 10:57:24 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void __init omap3430_init_early(void)
|
|
|
|
|
{
|
2011-10-05 05:26:28 +04:00
|
|
|
omap3_init_early();
|
2011-08-23 10:57:24 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void __init omap35xx_init_early(void)
|
|
|
|
|
{
|
2011-10-05 05:26:28 +04:00
|
|
|
omap3_init_early();
|
2011-08-23 10:57:24 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void __init omap3630_init_early(void)
|
|
|
|
|
{
|
2011-10-05 05:26:28 +04:00
|
|
|
omap3_init_early();
|
2011-08-23 10:57:24 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void __init am35xx_init_early(void)
|
|
|
|
|
{
|
2011-10-05 05:26:28 +04:00
|
|
|
omap3_init_early();
|
2011-08-23 10:57:24 +04:00
|
|
|
}
|
|
|
|
|
|
2011-12-13 22:46:44 +04:00
|
|
|
void __init ti81xx_init_early(void)
|
2011-08-23 10:57:24 +04:00
|
|
|
{
|
2012-10-30 06:50:21 +04:00
|
|
|
omap2_set_globals_tap(OMAP343X_CLASS,
|
|
|
|
|
OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
|
|
|
|
|
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
|
|
|
|
|
NULL);
|
2012-10-30 06:57:39 +04:00
|
|
|
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
|
|
|
|
|
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
|
2011-12-19 14:20:15 +04:00
|
|
|
omap3xxx_check_revision();
|
|
|
|
|
ti81xx_check_features();
|
2011-10-05 05:17:41 +04:00
|
|
|
omap3xxx_voltagedomains_init();
|
|
|
|
|
omap3xxx_powerdomains_init();
|
|
|
|
|
omap3xxx_clockdomains_init();
|
|
|
|
|
omap3xxx_hwmod_init();
|
|
|
|
|
omap_hwmod_init_postsetup();
|
ARM: OMAP: clocks: Delay clk inits atleast until slab is initialized
clk inits on OMAP happen quite early, even before slab is available.
The dependency comes from the fact that the timer init code starts to
use clocks and hwmod and we need clocks to be initialized by then.
There are various problems doing clk inits this early, one is,
not being able to do dynamic clk registrations and hence the
dependency on clk-private.h. The other is, inability to debug
early kernel crashes without enabling DEBUG_LL and earlyprintk.
Doing early clk init also exposed another instance of a kernel
panic due to a BUG() when CONFIG_DEBUG_SLAB is enabled.
[ 0.000000] Kernel BUG at c01174f8 [verbose debug info unavailable]
[ 0.000000] Internal error: Oops - BUG: 0 [#1] SMP ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 Not tainted (3.9.0-rc1-12179-g72d48f9 #6)
[ 0.000000] PC is at __kmalloc+0x1d4/0x248
[ 0.000000] LR is at __clk_init+0x2e0/0x364
[ 0.000000] pc : [<c01174f8>] lr : [<c0441f54>] psr: 600001d3
[ 0.000000] sp : c076ff28 ip : c065cefc fp : c0441f54
[ 0.000000] r10: 0000001c r9 : 000080d0 r8 : c076ffd4
[ 0.000000] r7 : c074b578 r6 : c0794d88 r5 : 00000040 r4 : 00000000
[ 0.000000] r3 : 00000000 r2 : c07cac70 r1 : 000080d0 r0 : 0000001c
[ 0.000000] Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel
[ 0.000000] Control: 10c53c7d Table: 8000404a DAC: 00000017
[ 0.000000] Process swapper (pid: 0, stack limit = 0xc076e240)
[ 0.000000] Stack: (0xc076ff28 to 0xc0770000)
[ 0.000000] ff20: 22222222 c0794ec8 c06546e8 00000000 00000040 c0794d88
[ 0.000000] ff40: c074b578 c076ffd4 c07951c8 c076e000 00000000 c0441f54 c074b578 c076ffd4
[ 0.000000] ff60: c0793828 00000040 c0794d88 c074b578 c076ffd4 c0776900 c076e000 c07272ac
[ 0.000000] ff80: 2f800000 c074c968 c07f93d0 c0719780 c076ffa0 c076ff98 00000000 00000000
[ 0.000000] ffa0: 00000000 00000000 00000000 00000001 c074cd6c c077b1ec 8000406a c0715724
[ 0.000000] ffc0: 00000000 00000000 00000000 00000000 00000000 c074c968 10c53c7d c0776974
[ 0.000000] ffe0: c074cd6c c077b1ec 8000406a 411fc092 00000000 80008074 00000000 00000000
[ 0.000000] [<c01174f8>] (__kmalloc+0x1d4/0x248) from [<c0441f54>] (__clk_init+0x2e0/0x364)
[ 0.000000] [<c0441f54>] (__clk_init+0x2e0/0x364) from [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140)
[ 0.000000] [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140) from [<c0719780>] (setup_arch+0x15c/0x284)
[ 0.000000] [<c0719780>] (setup_arch+0x15c/0x284) from [<c0715724>] (start_kernel+0x7c/0x334)
[ 0.000000] [<c0715724>] (start_kernel+0x7c/0x334) from [<80008074>] (0x80008074)
[ 0.000000] Code: e5883004 e1a00006 e28dd00c e8bd8ff0 (e7f001f2)
[ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
[ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
It was a know issue, that slab allocations would fail when common
clock core tries to cache parent pointers for mux clocks on OMAP,
and hence a patch 'clk: Allow late cache allocation for clk->parents,
commit 7975059d' was added to work this problem around.
A BUG() within kmalloc() with CONFIG_DEBUG_SLAB enabled was completely
overlooked causing this regression.
More details on the issue reported can be found here,
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg85932.html
With all these issues around clk inits happening way too early, it
makes sense to at least move them to a point where dynamic memory
allocations are possible. So move them to a point just before the
timer code starts using clocks and hwmod.
This should at least pave way for clk inits on OMAP moving to dynamic
clock registrations instead of using the static macros defined in
clk-private.h.
The issue with kernel panic while CONFIG_DEBUG_SLAB is enabled
was reported by Piotr Haber and Tony Lindgren and this patch
fixes the reported issue as well.
Reported-by: Piotr Haber <phaber@broadcom.com>
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Paul Walmsley <paul@pwsan.com>
Cc: stable@vger.kernel.org # v3.8
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-03-21 15:04:52 +04:00
|
|
|
omap_clk_init = omap3xxx_clk_init;
|
2011-08-23 10:57:24 +04:00
|
|
|
}
|
2012-04-26 12:06:50 +04:00
|
|
|
|
|
|
|
|
void __init omap3_init_late(void)
|
|
|
|
|
{
|
2013-02-14 15:55:22 +04:00
|
|
|
omap_common_late_init();
|
2012-04-26 12:06:50 +04:00
|
|
|
omap3_pm_init();
|
2012-06-01 12:32:49 +04:00
|
|
|
omap2_clk_enable_autoidle_all();
|
2012-04-26 12:06:50 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void __init omap3430_init_late(void)
|
|
|
|
|
{
|
2013-02-14 15:55:22 +04:00
|
|
|
omap_common_late_init();
|
2012-04-26 12:06:50 +04:00
|
|
|
omap3_pm_init();
|
2012-06-01 12:32:49 +04:00
|
|
|
omap2_clk_enable_autoidle_all();
|
2012-04-26 12:06:50 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void __init omap35xx_init_late(void)
|
|
|
|
|
{
|
2013-02-14 15:55:22 +04:00
|
|
|
omap_common_late_init();
|
2012-04-26 12:06:50 +04:00
|
|
|
omap3_pm_init();
|
2012-06-01 12:32:49 +04:00
|
|
|
omap2_clk_enable_autoidle_all();
|
2012-04-26 12:06:50 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void __init omap3630_init_late(void)
|
|
|
|
|
{
|
2013-02-14 15:55:22 +04:00
|
|
|
omap_common_late_init();
|
2012-04-26 12:06:50 +04:00
|
|
|
omap3_pm_init();
|
2012-06-01 12:32:49 +04:00
|
|
|
omap2_clk_enable_autoidle_all();
|
2012-04-26 12:06:50 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void __init am35xx_init_late(void)
|
|
|
|
|
{
|
2013-02-14 15:55:22 +04:00
|
|
|
omap_common_late_init();
|
2012-04-26 12:06:50 +04:00
|
|
|
omap3_pm_init();
|
2012-06-01 12:32:49 +04:00
|
|
|
omap2_clk_enable_autoidle_all();
|
2012-04-26 12:06:50 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void __init ti81xx_init_late(void)
|
|
|
|
|
{
|
2013-02-14 15:55:22 +04:00
|
|
|
omap_common_late_init();
|
2012-04-26 12:06:50 +04:00
|
|
|
omap3_pm_init();
|
2012-06-01 12:32:49 +04:00
|
|
|
omap2_clk_enable_autoidle_all();
|
2012-04-26 12:06:50 +04:00
|
|
|
}
|
2011-10-13 20:14:10 +04:00
|
|
|
#endif
|
2011-08-23 10:57:24 +04:00
|
|
|
|
2012-05-10 23:08:49 +04:00
|
|
|
#ifdef CONFIG_SOC_AM33XX
|
|
|
|
|
void __init am33xx_init_early(void)
|
|
|
|
|
{
|
2012-10-30 06:50:21 +04:00
|
|
|
omap2_set_globals_tap(AM335X_CLASS,
|
|
|
|
|
AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
|
|
|
|
|
omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
|
|
|
|
|
NULL);
|
2012-10-30 06:57:39 +04:00
|
|
|
omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
|
|
|
|
|
omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
|
2012-05-10 23:08:49 +04:00
|
|
|
omap3xxx_check_revision();
|
2013-05-17 14:13:41 +04:00
|
|
|
am33xx_check_features();
|
ARM: OMAP AM33xx: powerdomains: add AM335x support
Add offset & mask fields to struct powerdomain
In case of AM33xx family of devices, there is no consistency between
PWRSTCTRL & PWRSTST register offsers in PRM space, for example -
PRM_XXX PWRSTCTRL PWRSTST
=======================================
PRM_PER_MOD: 0x0C, 0x08
PRM_WKUP_MOD: 0x04, 0x08
PRM_MPU_MOD: 0x00, 0x04
PRM_DEVICE_MOD: NA, NA
And also, there is no consistency between bit-offsets inside
PWRSTCTRL & PWRSTST register, for example -
PRM_XXX LOGICRET MEMON MEMRET
=======================================
GFX_PWRCTRL: 2, 17, 6
PER_PWRCTRL: 3, 25, 29
MPU_PWRCTRL: 2, 18, 22
WKUP_PWRCTRL: 3, NA, NA
This means, we need to maintain and pass on all this information
in powerdomain handle; so adding fields for,
- PWRSTCTRL/ST register offset
- Logic retention state mask
- mem_on/ret/pwrst/retst mask
Currently, this fields is only applicable and used for AM33XX devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: this patch is a combination of "Add offset & mask fields to
struct powerdomain" and the powerdomain portions of "ARM: OMAP3+: am33xx:
Add powerdomain & PRM support"; updated for 3.5]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2012-06-18 10:47:27 +04:00
|
|
|
am33xx_powerdomains_init();
|
2012-06-18 10:47:27 +04:00
|
|
|
am33xx_clockdomains_init();
|
2012-07-25 23:51:13 +04:00
|
|
|
am33xx_hwmod_init();
|
|
|
|
|
omap_hwmod_init_postsetup();
|
ARM: OMAP: clocks: Delay clk inits atleast until slab is initialized
clk inits on OMAP happen quite early, even before slab is available.
The dependency comes from the fact that the timer init code starts to
use clocks and hwmod and we need clocks to be initialized by then.
There are various problems doing clk inits this early, one is,
not being able to do dynamic clk registrations and hence the
dependency on clk-private.h. The other is, inability to debug
early kernel crashes without enabling DEBUG_LL and earlyprintk.
Doing early clk init also exposed another instance of a kernel
panic due to a BUG() when CONFIG_DEBUG_SLAB is enabled.
[ 0.000000] Kernel BUG at c01174f8 [verbose debug info unavailable]
[ 0.000000] Internal error: Oops - BUG: 0 [#1] SMP ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 Not tainted (3.9.0-rc1-12179-g72d48f9 #6)
[ 0.000000] PC is at __kmalloc+0x1d4/0x248
[ 0.000000] LR is at __clk_init+0x2e0/0x364
[ 0.000000] pc : [<c01174f8>] lr : [<c0441f54>] psr: 600001d3
[ 0.000000] sp : c076ff28 ip : c065cefc fp : c0441f54
[ 0.000000] r10: 0000001c r9 : 000080d0 r8 : c076ffd4
[ 0.000000] r7 : c074b578 r6 : c0794d88 r5 : 00000040 r4 : 00000000
[ 0.000000] r3 : 00000000 r2 : c07cac70 r1 : 000080d0 r0 : 0000001c
[ 0.000000] Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel
[ 0.000000] Control: 10c53c7d Table: 8000404a DAC: 00000017
[ 0.000000] Process swapper (pid: 0, stack limit = 0xc076e240)
[ 0.000000] Stack: (0xc076ff28 to 0xc0770000)
[ 0.000000] ff20: 22222222 c0794ec8 c06546e8 00000000 00000040 c0794d88
[ 0.000000] ff40: c074b578 c076ffd4 c07951c8 c076e000 00000000 c0441f54 c074b578 c076ffd4
[ 0.000000] ff60: c0793828 00000040 c0794d88 c074b578 c076ffd4 c0776900 c076e000 c07272ac
[ 0.000000] ff80: 2f800000 c074c968 c07f93d0 c0719780 c076ffa0 c076ff98 00000000 00000000
[ 0.000000] ffa0: 00000000 00000000 00000000 00000001 c074cd6c c077b1ec 8000406a c0715724
[ 0.000000] ffc0: 00000000 00000000 00000000 00000000 00000000 c074c968 10c53c7d c0776974
[ 0.000000] ffe0: c074cd6c c077b1ec 8000406a 411fc092 00000000 80008074 00000000 00000000
[ 0.000000] [<c01174f8>] (__kmalloc+0x1d4/0x248) from [<c0441f54>] (__clk_init+0x2e0/0x364)
[ 0.000000] [<c0441f54>] (__clk_init+0x2e0/0x364) from [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140)
[ 0.000000] [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140) from [<c0719780>] (setup_arch+0x15c/0x284)
[ 0.000000] [<c0719780>] (setup_arch+0x15c/0x284) from [<c0715724>] (start_kernel+0x7c/0x334)
[ 0.000000] [<c0715724>] (start_kernel+0x7c/0x334) from [<80008074>] (0x80008074)
[ 0.000000] Code: e5883004 e1a00006 e28dd00c e8bd8ff0 (e7f001f2)
[ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
[ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
It was a know issue, that slab allocations would fail when common
clock core tries to cache parent pointers for mux clocks on OMAP,
and hence a patch 'clk: Allow late cache allocation for clk->parents,
commit 7975059d' was added to work this problem around.
A BUG() within kmalloc() with CONFIG_DEBUG_SLAB enabled was completely
overlooked causing this regression.
More details on the issue reported can be found here,
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg85932.html
With all these issues around clk inits happening way too early, it
makes sense to at least move them to a point where dynamic memory
allocations are possible. So move them to a point just before the
timer code starts using clocks and hwmod.
This should at least pave way for clk inits on OMAP moving to dynamic
clock registrations instead of using the static macros defined in
clk-private.h.
The issue with kernel panic while CONFIG_DEBUG_SLAB is enabled
was reported by Piotr Haber and Tony Lindgren and this patch
fixes the reported issue as well.
Reported-by: Piotr Haber <phaber@broadcom.com>
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Paul Walmsley <paul@pwsan.com>
Cc: stable@vger.kernel.org # v3.8
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-03-21 15:04:52 +04:00
|
|
|
omap_clk_init = am33xx_clk_init;
|
2012-05-10 23:08:49 +04:00
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2013-05-27 18:36:23 +04:00
|
|
|
#ifdef CONFIG_SOC_AM43XX
|
|
|
|
|
void __init am43xx_init_early(void)
|
|
|
|
|
{
|
|
|
|
|
omap2_set_globals_tap(AM335X_CLASS,
|
|
|
|
|
AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
|
|
|
|
|
omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
|
|
|
|
|
NULL);
|
|
|
|
|
omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
|
|
|
|
|
omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
|
|
|
|
|
omap3xxx_check_revision();
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2011-10-13 20:14:10 +04:00
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
2011-08-23 10:57:24 +04:00
|
|
|
void __init omap4430_init_early(void)
|
|
|
|
|
{
|
2012-10-30 06:50:21 +04:00
|
|
|
omap2_set_globals_tap(OMAP443X_CLASS,
|
|
|
|
|
OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
|
|
|
|
|
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
|
|
|
|
|
OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
|
2012-10-30 06:57:39 +04:00
|
|
|
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
|
|
|
|
|
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
|
|
|
|
|
OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
|
|
|
|
|
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
|
|
|
|
|
omap_prm_base_init();
|
|
|
|
|
omap_cm_base_init();
|
2011-12-19 14:20:15 +04:00
|
|
|
omap4xxx_check_revision();
|
|
|
|
|
omap4xxx_check_features();
|
2012-11-22 03:15:16 +04:00
|
|
|
omap44xx_prm_init();
|
2011-10-05 05:26:28 +04:00
|
|
|
omap44xx_voltagedomains_init();
|
|
|
|
|
omap44xx_powerdomains_init();
|
|
|
|
|
omap44xx_clockdomains_init();
|
|
|
|
|
omap44xx_hwmod_init();
|
|
|
|
|
omap_hwmod_init_postsetup();
|
ARM: OMAP: clocks: Delay clk inits atleast until slab is initialized
clk inits on OMAP happen quite early, even before slab is available.
The dependency comes from the fact that the timer init code starts to
use clocks and hwmod and we need clocks to be initialized by then.
There are various problems doing clk inits this early, one is,
not being able to do dynamic clk registrations and hence the
dependency on clk-private.h. The other is, inability to debug
early kernel crashes without enabling DEBUG_LL and earlyprintk.
Doing early clk init also exposed another instance of a kernel
panic due to a BUG() when CONFIG_DEBUG_SLAB is enabled.
[ 0.000000] Kernel BUG at c01174f8 [verbose debug info unavailable]
[ 0.000000] Internal error: Oops - BUG: 0 [#1] SMP ARM
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 Not tainted (3.9.0-rc1-12179-g72d48f9 #6)
[ 0.000000] PC is at __kmalloc+0x1d4/0x248
[ 0.000000] LR is at __clk_init+0x2e0/0x364
[ 0.000000] pc : [<c01174f8>] lr : [<c0441f54>] psr: 600001d3
[ 0.000000] sp : c076ff28 ip : c065cefc fp : c0441f54
[ 0.000000] r10: 0000001c r9 : 000080d0 r8 : c076ffd4
[ 0.000000] r7 : c074b578 r6 : c0794d88 r5 : 00000040 r4 : 00000000
[ 0.000000] r3 : 00000000 r2 : c07cac70 r1 : 000080d0 r0 : 0000001c
[ 0.000000] Flags: nZCv IRQs off FIQs off Mode SVC_32 ISA ARM Segment kernel
[ 0.000000] Control: 10c53c7d Table: 8000404a DAC: 00000017
[ 0.000000] Process swapper (pid: 0, stack limit = 0xc076e240)
[ 0.000000] Stack: (0xc076ff28 to 0xc0770000)
[ 0.000000] ff20: 22222222 c0794ec8 c06546e8 00000000 00000040 c0794d88
[ 0.000000] ff40: c074b578 c076ffd4 c07951c8 c076e000 00000000 c0441f54 c074b578 c076ffd4
[ 0.000000] ff60: c0793828 00000040 c0794d88 c074b578 c076ffd4 c0776900 c076e000 c07272ac
[ 0.000000] ff80: 2f800000 c074c968 c07f93d0 c0719780 c076ffa0 c076ff98 00000000 00000000
[ 0.000000] ffa0: 00000000 00000000 00000000 00000001 c074cd6c c077b1ec 8000406a c0715724
[ 0.000000] ffc0: 00000000 00000000 00000000 00000000 00000000 c074c968 10c53c7d c0776974
[ 0.000000] ffe0: c074cd6c c077b1ec 8000406a 411fc092 00000000 80008074 00000000 00000000
[ 0.000000] [<c01174f8>] (__kmalloc+0x1d4/0x248) from [<c0441f54>] (__clk_init+0x2e0/0x364)
[ 0.000000] [<c0441f54>] (__clk_init+0x2e0/0x364) from [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140)
[ 0.000000] [<c07272ac>] (omap4xxx_clk_init+0xbc/0x140) from [<c0719780>] (setup_arch+0x15c/0x284)
[ 0.000000] [<c0719780>] (setup_arch+0x15c/0x284) from [<c0715724>] (start_kernel+0x7c/0x334)
[ 0.000000] [<c0715724>] (start_kernel+0x7c/0x334) from [<80008074>] (0x80008074)
[ 0.000000] Code: e5883004 e1a00006 e28dd00c e8bd8ff0 (e7f001f2)
[ 0.000000] ---[ end trace 1b75b31a2719ed1c ]---
[ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
It was a know issue, that slab allocations would fail when common
clock core tries to cache parent pointers for mux clocks on OMAP,
and hence a patch 'clk: Allow late cache allocation for clk->parents,
commit 7975059d' was added to work this problem around.
A BUG() within kmalloc() with CONFIG_DEBUG_SLAB enabled was completely
overlooked causing this regression.
More details on the issue reported can be found here,
http://www.mail-archive.com/linux-omap@vger.kernel.org/msg85932.html
With all these issues around clk inits happening way too early, it
makes sense to at least move them to a point where dynamic memory
allocations are possible. So move them to a point just before the
timer code starts using clocks and hwmod.
This should at least pave way for clk inits on OMAP moving to dynamic
clock registrations instead of using the static macros defined in
clk-private.h.
The issue with kernel panic while CONFIG_DEBUG_SLAB is enabled
was reported by Piotr Haber and Tony Lindgren and this patch
fixes the reported issue as well.
Reported-by: Piotr Haber <phaber@broadcom.com>
Reported-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Paul Walmsley <paul@pwsan.com>
Cc: stable@vger.kernel.org # v3.8
Signed-off-by: Tony Lindgren <tony@atomide.com>
2013-03-21 15:04:52 +04:00
|
|
|
omap_clk_init = omap4xxx_clk_init;
|
2011-08-23 10:57:24 +04:00
|
|
|
}
|
2012-04-26 12:06:50 +04:00
|
|
|
|
|
|
|
|
void __init omap4430_init_late(void)
|
|
|
|
|
{
|
2013-02-14 15:55:22 +04:00
|
|
|
omap_common_late_init();
|
2012-04-26 12:06:50 +04:00
|
|
|
omap4_pm_init();
|
2012-06-01 12:32:49 +04:00
|
|
|
omap2_clk_enable_autoidle_all();
|
2012-04-26 12:06:50 +04:00
|
|
|
}
|
2011-10-13 20:14:10 +04:00
|
|
|
#endif
|
2011-08-23 10:57:24 +04:00
|
|
|
|
2012-06-05 14:51:32 +04:00
|
|
|
#ifdef CONFIG_SOC_OMAP5
|
|
|
|
|
void __init omap5_init_early(void)
|
|
|
|
|
{
|
2012-10-30 06:50:21 +04:00
|
|
|
omap2_set_globals_tap(OMAP54XX_CLASS,
|
|
|
|
|
OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
|
|
|
|
|
omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
|
|
|
|
|
OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
|
2012-10-30 06:57:39 +04:00
|
|
|
omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
|
|
|
|
|
omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
|
|
|
|
|
OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
|
|
|
|
|
omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
|
|
|
|
|
omap_prm_base_init();
|
|
|
|
|
omap_cm_base_init();
|
2013-05-29 20:38:12 +04:00
|
|
|
omap44xx_prm_init();
|
2012-06-05 14:51:32 +04:00
|
|
|
omap5xxx_check_revision();
|
2013-05-29 20:38:12 +04:00
|
|
|
omap54xx_voltagedomains_init();
|
|
|
|
|
omap54xx_powerdomains_init();
|
|
|
|
|
omap54xx_clockdomains_init();
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|
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omap54xx_hwmod_init();
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|
|
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omap_hwmod_init_postsetup();
|
2012-06-05 14:51:32 +04:00
|
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}
|
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#endif
|
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2011-08-23 10:57:23 +04:00
|
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void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
|
OMAP2+: io: split omap2_init_common_hw()
Split omap2_init_common_hw() into two functions. The first,
omap2_init_common_infrastructure(), initializes the hwmod code and
data, the OMAP PM code, and the clock code and data. The second,
omap2_init_common_devices(), handles any other early device
initialization that, for whatever reason, has not been or cannot be
moved to initcalls or early platform devices.
This patch is required for the hwmod postsetup patch, which allows
board files to change the state that hwmods should be placed into at
the conclusion of the hwmod _setup() function. For example, for a
board whose creators wish to ensure watchdog coverage across the
entire kernel boot process, code to change the watchdog's postsetup
state will be added in the board-*.c file between the
omap2_init_common_infrastructure() and omap2_init_common_devices() function
calls.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
2010-12-22 01:25:10 +03:00
|
|
|
struct omap_sdrc_params *sdrc_cs1)
|
|
|
|
|
{
|
2011-10-05 00:52:57 +04:00
|
|
|
omap_sram_init();
|
|
|
|
|
|
2011-02-16 19:31:39 +03:00
|
|
|
if (cpu_is_omap24xx() || omap3_has_sdrc()) {
|
2010-03-10 20:16:31 +03:00
|
|
|
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
|
|
|
|
|
_omap2_init_reprogram_sdrc();
|
|
|
|
|
}
|
2005-11-10 17:26:51 +03:00
|
|
|
}
|
