2018-03-28 18:46:15 +03:00
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// SPDX-License-Identifier: GPL-2.0
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2015-09-22 15:47:15 +03:00
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/*
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* Intel(R) Trace Hub pci driver
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*
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* Copyright (C) 2014-2015 Intel Corporation.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/sysfs.h>
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#include <linux/pci.h>
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#include "intel_th.h"
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#define DRIVER_NAME "intel_th_pci"
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2019-05-03 11:44:36 +03:00
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enum {
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TH_PCI_CONFIG_BAR = 0,
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TH_PCI_STH_SW_BAR = 2,
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2019-05-03 11:44:38 +03:00
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TH_PCI_RTIT_BAR = 4,
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2019-05-03 11:44:36 +03:00
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};
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#define BAR_MASK (BIT(TH_PCI_CONFIG_BAR) | BIT(TH_PCI_STH_SW_BAR))
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2015-09-22 15:47:15 +03:00
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2017-02-24 17:09:40 +03:00
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#define PCI_REG_NPKDSC 0x80
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#define NPKDSC_TSACT BIT(5)
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static int intel_th_pci_activate(struct intel_th *th)
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{
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struct pci_dev *pdev = to_pci_dev(th->dev);
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u32 npkdsc;
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int err;
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if (!INTEL_TH_CAP(th, tscu_enable))
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return 0;
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err = pci_read_config_dword(pdev, PCI_REG_NPKDSC, &npkdsc);
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if (!err) {
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npkdsc |= NPKDSC_TSACT;
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err = pci_write_config_dword(pdev, PCI_REG_NPKDSC, npkdsc);
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}
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if (err)
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dev_err(&pdev->dev, "failed to read NPKDSC register\n");
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return err;
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}
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static void intel_th_pci_deactivate(struct intel_th *th)
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{
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struct pci_dev *pdev = to_pci_dev(th->dev);
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u32 npkdsc;
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int err;
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if (!INTEL_TH_CAP(th, tscu_enable))
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return;
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err = pci_read_config_dword(pdev, PCI_REG_NPKDSC, &npkdsc);
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if (!err) {
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npkdsc |= NPKDSC_TSACT;
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err = pci_write_config_dword(pdev, PCI_REG_NPKDSC, npkdsc);
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}
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if (err)
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dev_err(&pdev->dev, "failed to read NPKDSC register\n");
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}
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2015-09-22 15:47:15 +03:00
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static int intel_th_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *id)
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{
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2017-08-18 17:57:35 +03:00
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struct intel_th_drvdata *drvdata = (void *)id->driver_data;
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2019-05-03 11:44:40 +03:00
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struct resource resource[TH_MMIO_END + TH_NVEC_MAX] = {
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2019-05-03 11:44:36 +03:00
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[TH_MMIO_CONFIG] = pdev->resource[TH_PCI_CONFIG_BAR],
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[TH_MMIO_SW] = pdev->resource[TH_PCI_STH_SW_BAR],
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};
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2019-05-03 11:44:40 +03:00
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int err, r = TH_MMIO_SW + 1, i;
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2015-09-22 15:47:15 +03:00
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struct intel_th *th;
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err = pcim_enable_device(pdev);
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if (err)
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return err;
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err = pcim_iomap_regions_request_all(pdev, BAR_MASK, DRIVER_NAME);
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if (err)
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return err;
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2019-05-03 11:44:38 +03:00
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if (pdev->resource[TH_PCI_RTIT_BAR].start) {
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resource[TH_MMIO_RTIT] = pdev->resource[TH_PCI_RTIT_BAR];
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r++;
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}
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2019-05-03 11:44:40 +03:00
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err = pci_alloc_irq_vectors(pdev, 1, 8, PCI_IRQ_ALL_TYPES);
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if (err > 0)
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for (i = 0; i < err; i++, r++) {
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resource[r].flags = IORESOURCE_IRQ;
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resource[r].start = pci_irq_vector(pdev, i);
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}
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2019-05-03 11:44:39 +03:00
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th = intel_th_alloc(&pdev->dev, drvdata, resource, r);
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2015-09-22 15:47:15 +03:00
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if (IS_ERR(th))
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return PTR_ERR(th);
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2017-02-24 17:09:40 +03:00
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th->activate = intel_th_pci_activate;
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th->deactivate = intel_th_pci_deactivate;
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2017-08-10 11:10:58 +03:00
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pci_set_master(pdev);
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2015-09-22 15:47:15 +03:00
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return 0;
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}
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static void intel_th_pci_remove(struct pci_dev *pdev)
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{
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struct intel_th *th = pci_get_drvdata(pdev);
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intel_th_free(th);
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2019-05-03 11:44:40 +03:00
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pci_free_irq_vectors(pdev);
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2015-09-22 15:47:15 +03:00
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}
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2020-03-17 09:22:10 +03:00
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static const struct intel_th_drvdata intel_th_1x_multi_is_broken = {
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.multi_is_broken = 1,
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};
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2017-02-24 17:09:40 +03:00
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static const struct intel_th_drvdata intel_th_2x = {
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.tscu_enable = 1,
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2019-05-03 11:44:42 +03:00
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.has_mintctl = 1,
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2017-02-24 17:09:40 +03:00
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};
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2015-09-22 15:47:15 +03:00
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static const struct pci_device_id intel_th_pci_id_table[] = {
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{
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9d26),
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.driver_data = (kernel_ulong_t)0,
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},
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{
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa126),
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.driver_data = (kernel_ulong_t)0,
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},
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2015-12-22 18:25:22 +03:00
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{
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/* Apollo Lake */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x5a8e),
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.driver_data = (kernel_ulong_t)0,
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},
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2015-12-22 18:25:23 +03:00
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{
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/* Broxton */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0a80),
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.driver_data = (kernel_ulong_t)0,
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},
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2016-04-08 18:26:52 +03:00
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{
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/* Broxton B-step */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1a8e),
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.driver_data = (kernel_ulong_t)0,
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},
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2016-06-28 18:55:23 +03:00
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{
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/* Kaby Lake PCH-H */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa2a6),
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2020-03-17 09:22:10 +03:00
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.driver_data = (kernel_ulong_t)&intel_th_1x_multi_is_broken,
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2016-06-28 18:55:23 +03:00
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},
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2015-09-08 14:03:55 +03:00
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{
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/* Denverton */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x19e1),
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.driver_data = (kernel_ulong_t)0,
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},
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2017-09-19 18:47:42 +03:00
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{
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/* Lewisburg PCH */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa1a6),
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.driver_data = (kernel_ulong_t)0,
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},
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2019-08-21 10:49:54 +03:00
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{
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/* Lewisburg PCH */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa226),
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.driver_data = (kernel_ulong_t)0,
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},
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2016-06-30 16:10:51 +03:00
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{
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/* Gemini Lake */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x318e),
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2017-02-24 17:09:40 +03:00
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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2016-06-30 16:10:51 +03:00
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},
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2016-06-30 16:11:13 +03:00
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{
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/* Cannon Lake H */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa326),
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2017-02-24 17:09:40 +03:00
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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2016-06-30 16:11:13 +03:00
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},
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2016-06-30 16:11:31 +03:00
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{
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/* Cannon Lake LP */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9da6),
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2017-02-24 17:09:40 +03:00
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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2016-06-30 16:11:31 +03:00
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},
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2017-09-19 18:47:41 +03:00
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{
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/* Cedar Fork PCH */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x18e1),
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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},
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2018-09-18 16:10:49 +03:00
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{
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/* Ice Lake PCH */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x34a6),
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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},
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2019-04-17 10:35:36 +03:00
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{
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/* Comet Lake */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x02a6),
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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},
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2019-10-28 10:06:50 +03:00
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{
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/* Comet Lake PCH */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x06a6),
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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},
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2019-12-17 14:55:24 +03:00
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{
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/* Comet Lake PCH-V */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa3a6),
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2020-03-17 09:22:10 +03:00
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.driver_data = (kernel_ulong_t)&intel_th_1x_multi_is_broken,
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2019-12-17 14:55:24 +03:00
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},
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2019-06-21 19:19:30 +03:00
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{
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/* Ice Lake NNPI */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x45c5),
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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},
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2019-11-20 16:08:05 +03:00
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{
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/* Ice Lake CPU */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8a29),
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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},
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2019-11-20 16:08:06 +03:00
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{
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/* Tiger Lake CPU */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x9a33),
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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},
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2019-08-21 10:49:55 +03:00
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{
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/* Tiger Lake PCH */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0xa0a6),
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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},
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2020-07-06 19:13:37 +03:00
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{
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/* Tiger Lake PCH-H */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x43a6),
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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},
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2019-10-28 10:06:51 +03:00
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{
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/* Jasper Lake PCH */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4da6),
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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},
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2020-07-06 19:13:36 +03:00
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{
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/* Jasper Lake CPU */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4e29),
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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},
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2020-03-17 09:22:15 +03:00
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{
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/* Elkhart Lake CPU */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4529),
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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},
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2019-12-17 14:55:25 +03:00
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{
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/* Elkhart Lake */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4b26),
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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},
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2020-07-06 19:13:38 +03:00
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{
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/* Emmitsburg PCH */
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PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1bcc),
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.driver_data = (kernel_ulong_t)&intel_th_2x,
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},
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2015-09-22 15:47:15 +03:00
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{ 0 },
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};
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MODULE_DEVICE_TABLE(pci, intel_th_pci_id_table);
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static struct pci_driver intel_th_pci_driver = {
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.name = DRIVER_NAME,
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.id_table = intel_th_pci_id_table,
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.probe = intel_th_pci_probe,
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.remove = intel_th_pci_remove,
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};
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module_pci_driver(intel_th_pci_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("Intel(R) Trace Hub PCI controller driver");
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MODULE_AUTHOR("Alexander Shishkin <alexander.shishkin@intel.com>");
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