2007-01-03 11:32:45 +03:00
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/*
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* sata_inic162x.c - Driver for Initio 162x SATA controllers
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*
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* Copyright 2006 SUSE Linux Products GmbH
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* Copyright 2006 Tejun Heo <teheo@novell.com>
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*
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* This file is released under GPL v2.
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*
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* This controller is eccentric and easily locks up if something isn't
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* right. Documentation is available at initio's website but it only
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* documents registers (not programming model).
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*
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* - ATA disks work.
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* - Hotplug works.
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* - ATAPI read works but burning doesn't. This thing is really
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* peculiar about ATAPI and I couldn't figure out how ATAPI PIO and
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* ATAPI DMA WRITE should be programmed. If you've got a clue, be
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* my guest.
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* - Both STR and STD work.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/blkdev.h>
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#include <scsi/scsi_device.h>
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#define DRV_NAME "sata_inic162x"
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2007-08-31 12:54:06 +04:00
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#define DRV_VERSION "0.3"
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2007-01-03 11:32:45 +03:00
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enum {
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2008-04-30 11:35:16 +04:00
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MMIO_BAR_PCI = 5,
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MMIO_BAR_CARDBUS = 1,
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2007-01-03 11:32:45 +03:00
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NR_PORTS = 2,
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2008-04-30 11:35:11 +04:00
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IDMA_CPB_TBL_SIZE = 4 * 32,
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INIC_DMA_BOUNDARY = 0xffffff,
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2008-04-30 11:35:09 +04:00
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HOST_ACTRL = 0x08,
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2007-01-03 11:32:45 +03:00
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HOST_CTL = 0x7c,
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HOST_STAT = 0x7e,
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HOST_IRQ_STAT = 0xbc,
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HOST_IRQ_MASK = 0xbe,
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PORT_SIZE = 0x40,
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/* registers for ATA TF operation */
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2008-04-30 11:35:09 +04:00
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PORT_TF_DATA = 0x00,
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PORT_TF_FEATURE = 0x01,
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PORT_TF_NSECT = 0x02,
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PORT_TF_LBAL = 0x03,
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PORT_TF_LBAM = 0x04,
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PORT_TF_LBAH = 0x05,
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PORT_TF_DEVICE = 0x06,
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PORT_TF_COMMAND = 0x07,
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PORT_TF_ALT_STAT = 0x08,
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2007-01-03 11:32:45 +03:00
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PORT_IRQ_STAT = 0x09,
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PORT_IRQ_MASK = 0x0a,
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PORT_PRD_CTL = 0x0b,
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PORT_PRD_ADDR = 0x0c,
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PORT_PRD_XFERLEN = 0x10,
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2008-04-30 11:35:09 +04:00
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PORT_CPB_CPBLAR = 0x18,
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PORT_CPB_PTQFIFO = 0x1c,
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2007-01-03 11:32:45 +03:00
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/* IDMA register */
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PORT_IDMA_CTL = 0x14,
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2008-04-30 11:35:09 +04:00
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PORT_IDMA_STAT = 0x16,
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PORT_RPQ_FIFO = 0x1e,
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PORT_RPQ_CNT = 0x1f,
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2007-01-03 11:32:45 +03:00
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PORT_SCR = 0x20,
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/* HOST_CTL bits */
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HCTL_IRQOFF = (1 << 8), /* global IRQ off */
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2008-04-30 11:35:09 +04:00
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HCTL_FTHD0 = (1 << 10), /* fifo threshold 0 */
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HCTL_FTHD1 = (1 << 11), /* fifo threshold 1*/
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HCTL_PWRDWN = (1 << 12), /* power down PHYs */
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2007-01-03 11:32:45 +03:00
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HCTL_SOFTRST = (1 << 13), /* global reset (no phy reset) */
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HCTL_RPGSEL = (1 << 15), /* register page select */
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HCTL_KNOWN_BITS = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
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HCTL_RPGSEL,
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/* HOST_IRQ_(STAT|MASK) bits */
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HIRQ_PORT0 = (1 << 0),
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HIRQ_PORT1 = (1 << 1),
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HIRQ_SOFT = (1 << 14),
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HIRQ_GLOBAL = (1 << 15), /* STAT only */
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/* PORT_IRQ_(STAT|MASK) bits */
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PIRQ_OFFLINE = (1 << 0), /* device unplugged */
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PIRQ_ONLINE = (1 << 1), /* device plugged */
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PIRQ_COMPLETE = (1 << 2), /* completion interrupt */
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PIRQ_FATAL = (1 << 3), /* fatal error */
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PIRQ_ATA = (1 << 4), /* ATA interrupt */
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PIRQ_REPLY = (1 << 5), /* reply FIFO not empty */
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PIRQ_PENDING = (1 << 7), /* port IRQ pending (STAT only) */
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PIRQ_ERR = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
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2008-04-30 11:35:15 +04:00
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PIRQ_MASK_DEFAULT = PIRQ_REPLY | PIRQ_ATA,
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2007-01-03 11:32:45 +03:00
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PIRQ_MASK_FREEZE = 0xff,
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/* PORT_PRD_CTL bits */
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PRD_CTL_START = (1 << 0),
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PRD_CTL_WR = (1 << 3),
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PRD_CTL_DMAEN = (1 << 7), /* DMA enable */
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/* PORT_IDMA_CTL bits */
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IDMA_CTL_RST_ATA = (1 << 2), /* hardreset ATA bus */
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IDMA_CTL_RST_IDMA = (1 << 5), /* reset IDMA machinary */
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IDMA_CTL_GO = (1 << 7), /* IDMA mode go */
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IDMA_CTL_ATA_NIEN = (1 << 8), /* ATA IRQ disable */
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2008-04-30 11:35:09 +04:00
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/* PORT_IDMA_STAT bits */
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IDMA_STAT_PERR = (1 << 0), /* PCI ERROR MODE */
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IDMA_STAT_CPBERR = (1 << 1), /* ADMA CPB error */
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IDMA_STAT_LGCY = (1 << 3), /* ADMA legacy */
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IDMA_STAT_UIRQ = (1 << 4), /* ADMA unsolicited irq */
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IDMA_STAT_STPD = (1 << 5), /* ADMA stopped */
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IDMA_STAT_PSD = (1 << 6), /* ADMA pause */
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IDMA_STAT_DONE = (1 << 7), /* ADMA done */
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IDMA_STAT_ERR = IDMA_STAT_PERR | IDMA_STAT_CPBERR,
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/* CPB Control Flags*/
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CPB_CTL_VALID = (1 << 0), /* CPB valid */
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CPB_CTL_QUEUED = (1 << 1), /* queued command */
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CPB_CTL_DATA = (1 << 2), /* data, rsvd in datasheet */
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CPB_CTL_IEN = (1 << 3), /* PCI interrupt enable */
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CPB_CTL_DEVDIR = (1 << 4), /* device direction control */
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/* CPB Response Flags */
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CPB_RESP_DONE = (1 << 0), /* ATA command complete */
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CPB_RESP_REL = (1 << 1), /* ATA release */
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CPB_RESP_IGNORED = (1 << 2), /* CPB ignored */
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CPB_RESP_ATA_ERR = (1 << 3), /* ATA command error */
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CPB_RESP_SPURIOUS = (1 << 4), /* ATA spurious interrupt error */
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CPB_RESP_UNDERFLOW = (1 << 5), /* APRD deficiency length error */
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CPB_RESP_OVERFLOW = (1 << 6), /* APRD exccess length error */
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CPB_RESP_CPB_ERR = (1 << 7), /* CPB error flag */
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/* PRD Control Flags */
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PRD_DRAIN = (1 << 1), /* ignore data excess */
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PRD_CDB = (1 << 2), /* atapi packet command pointer */
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PRD_DIRECT_INTR = (1 << 3), /* direct interrupt */
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PRD_DMA = (1 << 4), /* data transfer method */
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PRD_WRITE = (1 << 5), /* data dir, rsvd in datasheet */
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PRD_IOM = (1 << 6), /* io/memory transfer */
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PRD_END = (1 << 7), /* APRD chain end */
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2007-01-03 11:32:45 +03:00
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};
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2008-04-30 11:35:11 +04:00
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/* Comman Parameter Block */
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struct inic_cpb {
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u8 resp_flags; /* Response Flags */
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u8 error; /* ATA Error */
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u8 status; /* ATA Status */
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u8 ctl_flags; /* Control Flags */
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__le32 len; /* Total Transfer Length */
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__le32 prd; /* First PRD pointer */
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u8 rsvd[4];
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/* 16 bytes */
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u8 feature; /* ATA Feature */
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u8 hob_feature; /* ATA Ex. Feature */
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u8 device; /* ATA Device/Head */
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u8 mirctl; /* Mirror Control */
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u8 nsect; /* ATA Sector Count */
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u8 hob_nsect; /* ATA Ex. Sector Count */
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u8 lbal; /* ATA Sector Number */
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u8 hob_lbal; /* ATA Ex. Sector Number */
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u8 lbam; /* ATA Cylinder Low */
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u8 hob_lbam; /* ATA Ex. Cylinder Low */
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u8 lbah; /* ATA Cylinder High */
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u8 hob_lbah; /* ATA Ex. Cylinder High */
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u8 command; /* ATA Command */
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u8 ctl; /* ATA Control */
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u8 slave_error; /* Slave ATA Error */
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u8 slave_status; /* Slave ATA Status */
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/* 32 bytes */
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} __packed;
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/* Physical Region Descriptor */
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struct inic_prd {
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__le32 mad; /* Physical Memory Address */
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__le16 len; /* Transfer Length */
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u8 rsvd;
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u8 flags; /* Control Flags */
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} __packed;
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struct inic_pkt {
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struct inic_cpb cpb;
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2008-04-30 11:35:14 +04:00
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struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */
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u8 cdb[ATAPI_CDB_LEN];
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2008-04-30 11:35:11 +04:00
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} __packed;
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2007-01-03 11:32:45 +03:00
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struct inic_host_priv {
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2008-04-30 11:35:16 +04:00
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void __iomem *mmio_base;
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2008-04-30 11:35:08 +04:00
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u16 cached_hctl;
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2007-01-03 11:32:45 +03:00
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};
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struct inic_port_priv {
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2008-04-30 11:35:11 +04:00
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struct inic_pkt *pkt;
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dma_addr_t pkt_dma;
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u32 *cpb_tbl;
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dma_addr_t cpb_tbl_dma;
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2007-01-03 11:32:45 +03:00
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};
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static struct scsi_host_template inic_sht = {
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2008-04-30 11:35:12 +04:00
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ATA_BASE_SHT(DRV_NAME),
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.sg_tablesize = LIBATA_MAX_PRD, /* maybe it can be larger? */
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2008-04-30 11:35:11 +04:00
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.dma_boundary = INIC_DMA_BOUNDARY,
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2007-01-03 11:32:45 +03:00
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};
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static const int scr_map[] = {
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[SCR_STATUS] = 0,
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[SCR_ERROR] = 1,
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[SCR_CONTROL] = 2,
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};
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2007-10-26 08:03:37 +04:00
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static void __iomem *inic_port_base(struct ata_port *ap)
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2007-01-03 11:32:45 +03:00
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{
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2008-04-30 11:35:16 +04:00
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struct inic_host_priv *hpriv = ap->host->private_data;
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return hpriv->mmio_base + ap->port_no * PORT_SIZE;
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2007-01-03 11:32:45 +03:00
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}
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static void inic_reset_port(void __iomem *port_base)
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{
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void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
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2008-04-30 11:35:15 +04:00
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/* stop IDMA engine */
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readw(idma_ctl); /* flush */
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msleep(1);
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2007-01-03 11:32:45 +03:00
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/* mask IRQ and assert reset */
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2008-04-30 11:35:15 +04:00
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writew(IDMA_CTL_RST_IDMA, idma_ctl);
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2007-01-03 11:32:45 +03:00
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readw(idma_ctl); /* flush */
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msleep(1);
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/* release reset */
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2008-04-30 11:35:15 +04:00
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writew(0, idma_ctl);
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2007-01-03 11:32:45 +03:00
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/* clear irq */
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writeb(0xff, port_base + PORT_IRQ_STAT);
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}
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2007-07-16 09:29:40 +04:00
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static int inic_scr_read(struct ata_port *ap, unsigned sc_reg, u32 *val)
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2007-01-03 11:32:45 +03:00
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{
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2008-04-30 11:35:15 +04:00
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void __iomem *scr_addr = inic_port_base(ap) + PORT_SCR;
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2007-01-03 11:32:45 +03:00
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void __iomem *addr;
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if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
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2007-07-16 09:29:40 +04:00
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return -EINVAL;
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2007-01-03 11:32:45 +03:00
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addr = scr_addr + scr_map[sc_reg] * 4;
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2007-07-16 09:29:40 +04:00
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*val = readl(scr_addr + scr_map[sc_reg] * 4);
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2007-01-03 11:32:45 +03:00
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/* this controller has stuck DIAG.N, ignore it */
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if (sc_reg == SCR_ERROR)
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2007-07-16 09:29:40 +04:00
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*val &= ~SERR_PHYRDY_CHG;
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return 0;
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2007-01-03 11:32:45 +03:00
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}
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2007-07-16 09:29:40 +04:00
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static int inic_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
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2007-01-03 11:32:45 +03:00
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{
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2008-04-30 11:35:15 +04:00
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void __iomem *scr_addr = inic_port_base(ap) + PORT_SCR;
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2007-01-03 11:32:45 +03:00
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if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
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2007-07-16 09:29:40 +04:00
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return -EINVAL;
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2007-01-03 11:32:45 +03:00
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writel(val, scr_addr + scr_map[sc_reg] * 4);
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2007-07-16 09:29:40 +04:00
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return 0;
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2007-01-03 11:32:45 +03:00
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}
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2008-04-30 11:35:11 +04:00
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static void inic_stop_idma(struct ata_port *ap)
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2007-01-03 11:32:45 +03:00
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{
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void __iomem *port_base = inic_port_base(ap);
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2008-04-30 11:35:11 +04:00
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readb(port_base + PORT_RPQ_FIFO);
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readb(port_base + PORT_RPQ_CNT);
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writew(0, port_base + PORT_IDMA_CTL);
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}
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static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat)
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{
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2007-08-06 13:36:22 +04:00
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struct ata_eh_info *ehi = &ap->link.eh_info;
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2008-04-30 11:35:11 +04:00
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struct inic_port_priv *pp = ap->private_data;
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struct inic_cpb *cpb = &pp->pkt->cpb;
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bool freeze = false;
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ata_ehi_clear_desc(ehi);
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ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x",
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irq_stat, idma_stat);
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inic_stop_idma(ap);
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|
if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
|
|
|
|
ata_ehi_push_desc(ehi, "hotplug");
|
|
|
|
ata_ehi_hotplugged(ehi);
|
|
|
|
freeze = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (idma_stat & IDMA_STAT_PERR) {
|
|
|
|
ata_ehi_push_desc(ehi, "PCI error");
|
|
|
|
freeze = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (idma_stat & IDMA_STAT_CPBERR) {
|
|
|
|
ata_ehi_push_desc(ehi, "CPB error");
|
|
|
|
|
|
|
|
if (cpb->resp_flags & CPB_RESP_IGNORED) {
|
|
|
|
__ata_ehi_push_desc(ehi, " ignored");
|
|
|
|
ehi->err_mask |= AC_ERR_INVALID;
|
|
|
|
freeze = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpb->resp_flags & CPB_RESP_ATA_ERR)
|
|
|
|
ehi->err_mask |= AC_ERR_DEV;
|
|
|
|
|
|
|
|
if (cpb->resp_flags & CPB_RESP_SPURIOUS) {
|
|
|
|
__ata_ehi_push_desc(ehi, " spurious-intr");
|
|
|
|
ehi->err_mask |= AC_ERR_HSM;
|
|
|
|
freeze = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cpb->resp_flags &
|
|
|
|
(CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) {
|
|
|
|
__ata_ehi_push_desc(ehi, " data-over/underflow");
|
|
|
|
ehi->err_mask |= AC_ERR_HSM;
|
|
|
|
freeze = true;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (freeze)
|
|
|
|
ata_port_freeze(ap);
|
|
|
|
else
|
|
|
|
ata_port_abort(ap);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void inic_host_intr(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
void __iomem *port_base = inic_port_base(ap);
|
|
|
|
struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
|
2007-01-03 11:32:45 +03:00
|
|
|
u8 irq_stat;
|
2008-04-30 11:35:11 +04:00
|
|
|
u16 idma_stat;
|
2007-01-03 11:32:45 +03:00
|
|
|
|
2008-04-30 11:35:11 +04:00
|
|
|
/* read and clear IRQ status */
|
2007-01-03 11:32:45 +03:00
|
|
|
irq_stat = readb(port_base + PORT_IRQ_STAT);
|
|
|
|
writeb(irq_stat, port_base + PORT_IRQ_STAT);
|
2008-04-30 11:35:11 +04:00
|
|
|
idma_stat = readw(port_base + PORT_IDMA_STAT);
|
|
|
|
|
|
|
|
if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR)))
|
|
|
|
inic_host_err_intr(ap, irq_stat, idma_stat);
|
|
|
|
|
2008-04-30 11:35:15 +04:00
|
|
|
if (unlikely(!qc))
|
2008-04-30 11:35:11 +04:00
|
|
|
goto spurious;
|
|
|
|
|
2008-04-30 11:35:14 +04:00
|
|
|
if (likely(idma_stat & IDMA_STAT_DONE)) {
|
|
|
|
inic_stop_idma(ap);
|
2007-01-03 11:32:45 +03:00
|
|
|
|
2008-04-30 11:35:14 +04:00
|
|
|
/* Depending on circumstances, device error
|
|
|
|
* isn't reported by IDMA, check it explicitly.
|
|
|
|
*/
|
|
|
|
if (unlikely(readb(port_base + PORT_TF_COMMAND) &
|
|
|
|
(ATA_DF | ATA_ERR)))
|
|
|
|
qc->err_mask |= AC_ERR_DEV;
|
2007-01-03 11:32:45 +03:00
|
|
|
|
2008-04-30 11:35:14 +04:00
|
|
|
ata_qc_complete(qc);
|
|
|
|
return;
|
2007-01-03 11:32:45 +03:00
|
|
|
}
|
|
|
|
|
2008-04-30 11:35:11 +04:00
|
|
|
spurious:
|
2008-04-30 11:35:15 +04:00
|
|
|
ata_port_printk(ap, KERN_WARNING, "unhandled interrupt: "
|
|
|
|
"cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n",
|
|
|
|
qc ? qc->tf.command : 0xff, irq_stat, idma_stat);
|
2007-01-03 11:32:45 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t inic_interrupt(int irq, void *dev_instance)
|
|
|
|
{
|
|
|
|
struct ata_host *host = dev_instance;
|
2008-04-30 11:35:16 +04:00
|
|
|
struct inic_host_priv *hpriv = host->private_data;
|
2007-01-03 11:32:45 +03:00
|
|
|
u16 host_irq_stat;
|
|
|
|
int i, handled = 0;;
|
|
|
|
|
2008-04-30 11:35:16 +04:00
|
|
|
host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT);
|
2007-01-03 11:32:45 +03:00
|
|
|
|
|
|
|
if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
spin_lock(&host->lock);
|
|
|
|
|
|
|
|
for (i = 0; i < NR_PORTS; i++) {
|
|
|
|
struct ata_port *ap = host->ports[i];
|
|
|
|
|
|
|
|
if (!(host_irq_stat & (HIRQ_PORT0 << i)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (likely(ap && !(ap->flags & ATA_FLAG_DISABLED))) {
|
|
|
|
inic_host_intr(ap);
|
|
|
|
handled++;
|
|
|
|
} else {
|
|
|
|
if (ata_ratelimit())
|
|
|
|
dev_printk(KERN_ERR, host->dev, "interrupt "
|
|
|
|
"from disabled port %d (0x%x)\n",
|
|
|
|
i, host_irq_stat);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
spin_unlock(&host->lock);
|
|
|
|
|
|
|
|
out:
|
|
|
|
return IRQ_RETVAL(handled);
|
|
|
|
}
|
|
|
|
|
2008-04-30 11:35:14 +04:00
|
|
|
static int inic_check_atapi_dma(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
/* For some reason ATAPI_PROT_DMA doesn't work for some
|
|
|
|
* commands including writes and other misc ops. Use PIO
|
|
|
|
* protocol instead, which BTW is driven by the DMA engine
|
|
|
|
* anyway, so it shouldn't make much difference for native
|
|
|
|
* SATA devices.
|
|
|
|
*/
|
|
|
|
if (atapi_cmd_type(qc->cdb[0]) == READ)
|
|
|
|
return 0;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
2008-04-30 11:35:11 +04:00
|
|
|
static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct scatterlist *sg;
|
|
|
|
unsigned int si;
|
2008-04-30 11:35:13 +04:00
|
|
|
u8 flags = 0;
|
2008-04-30 11:35:11 +04:00
|
|
|
|
|
|
|
if (qc->tf.flags & ATA_TFLAG_WRITE)
|
|
|
|
flags |= PRD_WRITE;
|
|
|
|
|
2008-04-30 11:35:13 +04:00
|
|
|
if (ata_is_dma(qc->tf.protocol))
|
|
|
|
flags |= PRD_DMA;
|
|
|
|
|
2008-04-30 11:35:11 +04:00
|
|
|
for_each_sg(qc->sg, sg, qc->n_elem, si) {
|
|
|
|
prd->mad = cpu_to_le32(sg_dma_address(sg));
|
|
|
|
prd->len = cpu_to_le16(sg_dma_len(sg));
|
|
|
|
prd->flags = flags;
|
|
|
|
prd++;
|
|
|
|
}
|
|
|
|
|
|
|
|
WARN_ON(!si);
|
|
|
|
prd[-1].flags |= PRD_END;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void inic_qc_prep(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct inic_port_priv *pp = qc->ap->private_data;
|
|
|
|
struct inic_pkt *pkt = pp->pkt;
|
|
|
|
struct inic_cpb *cpb = &pkt->cpb;
|
|
|
|
struct inic_prd *prd = pkt->prd;
|
2008-04-30 11:35:13 +04:00
|
|
|
bool is_atapi = ata_is_atapi(qc->tf.protocol);
|
|
|
|
bool is_data = ata_is_data(qc->tf.protocol);
|
2008-04-30 11:35:14 +04:00
|
|
|
unsigned int cdb_len = 0;
|
2008-04-30 11:35:11 +04:00
|
|
|
|
|
|
|
VPRINTK("ENTER\n");
|
|
|
|
|
2008-04-30 11:35:13 +04:00
|
|
|
if (is_atapi)
|
2008-04-30 11:35:14 +04:00
|
|
|
cdb_len = qc->dev->cdb_len;
|
2008-04-30 11:35:11 +04:00
|
|
|
|
|
|
|
/* prepare packet, based on initio driver */
|
|
|
|
memset(pkt, 0, sizeof(struct inic_pkt));
|
|
|
|
|
2008-04-30 11:35:13 +04:00
|
|
|
cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN;
|
2008-04-30 11:35:14 +04:00
|
|
|
if (is_atapi || is_data)
|
2008-04-30 11:35:13 +04:00
|
|
|
cpb->ctl_flags |= CPB_CTL_DATA;
|
2008-04-30 11:35:11 +04:00
|
|
|
|
2008-04-30 11:35:14 +04:00
|
|
|
cpb->len = cpu_to_le32(qc->nbytes + cdb_len);
|
2008-04-30 11:35:11 +04:00
|
|
|
cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd));
|
|
|
|
|
|
|
|
cpb->device = qc->tf.device;
|
|
|
|
cpb->feature = qc->tf.feature;
|
|
|
|
cpb->nsect = qc->tf.nsect;
|
|
|
|
cpb->lbal = qc->tf.lbal;
|
|
|
|
cpb->lbam = qc->tf.lbam;
|
|
|
|
cpb->lbah = qc->tf.lbah;
|
|
|
|
|
|
|
|
if (qc->tf.flags & ATA_TFLAG_LBA48) {
|
|
|
|
cpb->hob_feature = qc->tf.hob_feature;
|
|
|
|
cpb->hob_nsect = qc->tf.hob_nsect;
|
|
|
|
cpb->hob_lbal = qc->tf.hob_lbal;
|
|
|
|
cpb->hob_lbam = qc->tf.hob_lbam;
|
|
|
|
cpb->hob_lbah = qc->tf.hob_lbah;
|
|
|
|
}
|
|
|
|
|
|
|
|
cpb->command = qc->tf.command;
|
|
|
|
/* don't load ctl - dunno why. it's like that in the initio driver */
|
|
|
|
|
2008-04-30 11:35:14 +04:00
|
|
|
/* setup PRD for CDB */
|
|
|
|
if (is_atapi) {
|
|
|
|
memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN);
|
|
|
|
prd->mad = cpu_to_le32(pp->pkt_dma +
|
|
|
|
offsetof(struct inic_pkt, cdb));
|
|
|
|
prd->len = cpu_to_le16(cdb_len);
|
|
|
|
prd->flags = PRD_CDB | PRD_WRITE;
|
|
|
|
if (!is_data)
|
|
|
|
prd->flags |= PRD_END;
|
|
|
|
prd++;
|
|
|
|
}
|
|
|
|
|
2008-04-30 11:35:11 +04:00
|
|
|
/* setup sg table */
|
2008-04-30 11:35:13 +04:00
|
|
|
if (is_data)
|
|
|
|
inic_fill_sg(prd, qc);
|
2008-04-30 11:35:11 +04:00
|
|
|
|
|
|
|
pp->cpb_tbl[0] = pp->pkt_dma;
|
|
|
|
}
|
|
|
|
|
2007-01-03 11:32:45 +03:00
|
|
|
static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct ata_port *ap = qc->ap;
|
2008-04-30 11:35:11 +04:00
|
|
|
void __iomem *port_base = inic_port_base(ap);
|
2007-01-03 11:32:45 +03:00
|
|
|
|
2008-04-30 11:35:14 +04:00
|
|
|
/* fire up the ADMA engine */
|
|
|
|
writew(HCTL_FTHD0, port_base + HOST_CTL);
|
|
|
|
writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL);
|
|
|
|
writeb(0, port_base + PORT_CPB_PTQFIFO);
|
2007-01-03 11:32:45 +03:00
|
|
|
|
2008-04-30 11:35:14 +04:00
|
|
|
return 0;
|
2007-01-03 11:32:45 +03:00
|
|
|
}
|
|
|
|
|
2008-05-01 18:55:58 +04:00
|
|
|
static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
|
|
|
|
{
|
|
|
|
void __iomem *port_base = inic_port_base(ap);
|
|
|
|
|
|
|
|
tf->feature = readb(port_base + PORT_TF_FEATURE);
|
|
|
|
tf->nsect = readb(port_base + PORT_TF_NSECT);
|
|
|
|
tf->lbal = readb(port_base + PORT_TF_LBAL);
|
|
|
|
tf->lbam = readb(port_base + PORT_TF_LBAM);
|
|
|
|
tf->lbah = readb(port_base + PORT_TF_LBAH);
|
|
|
|
tf->device = readb(port_base + PORT_TF_DEVICE);
|
|
|
|
tf->command = readb(port_base + PORT_TF_COMMAND);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
struct ata_taskfile *rtf = &qc->result_tf;
|
|
|
|
struct ata_taskfile tf;
|
|
|
|
|
|
|
|
/* FIXME: Except for status and error, result TF access
|
|
|
|
* doesn't work. I tried reading from BAR0/2, CPB and BAR5.
|
|
|
|
* None works regardless of which command interface is used.
|
|
|
|
* For now return true iff status indicates device error.
|
|
|
|
* This means that we're reporting bogus sector for RW
|
|
|
|
* failures. Eeekk....
|
|
|
|
*/
|
|
|
|
inic_tf_read(qc->ap, &tf);
|
|
|
|
|
|
|
|
if (!(tf.command & ATA_ERR))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
rtf->command = tf.command;
|
|
|
|
rtf->feature = tf.feature;
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2007-01-03 11:32:45 +03:00
|
|
|
static void inic_freeze(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
void __iomem *port_base = inic_port_base(ap);
|
|
|
|
|
2008-04-30 11:35:12 +04:00
|
|
|
writeb(PIRQ_MASK_FREEZE, port_base + PORT_IRQ_MASK);
|
2007-01-03 11:32:45 +03:00
|
|
|
writeb(0xff, port_base + PORT_IRQ_STAT);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void inic_thaw(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
void __iomem *port_base = inic_port_base(ap);
|
|
|
|
|
|
|
|
writeb(0xff, port_base + PORT_IRQ_STAT);
|
2008-04-30 11:35:12 +04:00
|
|
|
writeb(PIRQ_MASK_DEFAULT, port_base + PORT_IRQ_MASK);
|
2007-01-03 11:32:45 +03:00
|
|
|
}
|
|
|
|
|
2008-05-01 18:55:58 +04:00
|
|
|
static int inic_check_ready(struct ata_link *link)
|
|
|
|
{
|
|
|
|
void __iomem *port_base = inic_port_base(link->ap);
|
|
|
|
|
|
|
|
return ata_check_ready(readb(port_base + PORT_TF_COMMAND));
|
|
|
|
}
|
|
|
|
|
2007-01-03 11:32:45 +03:00
|
|
|
/*
|
|
|
|
* SRST and SControl hardreset don't give valid signature on this
|
|
|
|
* controller. Only controller specific hardreset mechanism works.
|
|
|
|
*/
|
2007-08-06 13:36:23 +04:00
|
|
|
static int inic_hardreset(struct ata_link *link, unsigned int *class,
|
libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 10:50:52 +03:00
|
|
|
unsigned long deadline)
|
2007-01-03 11:32:45 +03:00
|
|
|
{
|
2007-08-06 13:36:23 +04:00
|
|
|
struct ata_port *ap = link->ap;
|
2007-01-03 11:32:45 +03:00
|
|
|
void __iomem *port_base = inic_port_base(ap);
|
|
|
|
void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
|
2007-08-06 13:36:23 +04:00
|
|
|
const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
|
2007-01-03 11:32:45 +03:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
/* hammer it into sane state */
|
|
|
|
inic_reset_port(port_base);
|
|
|
|
|
2008-04-30 11:35:15 +04:00
|
|
|
writew(IDMA_CTL_RST_ATA, idma_ctl);
|
2007-01-03 11:32:45 +03:00
|
|
|
readw(idma_ctl); /* flush */
|
|
|
|
msleep(1);
|
2008-04-30 11:35:15 +04:00
|
|
|
writew(0, idma_ctl);
|
2007-01-03 11:32:45 +03:00
|
|
|
|
2007-08-06 13:36:23 +04:00
|
|
|
rc = sata_link_resume(link, timing, deadline);
|
2007-01-03 11:32:45 +03:00
|
|
|
if (rc) {
|
2007-08-06 13:36:23 +04:00
|
|
|
ata_link_printk(link, KERN_WARNING, "failed to resume "
|
2007-02-02 09:29:52 +03:00
|
|
|
"link after reset (errno=%d)\n", rc);
|
2007-01-03 11:32:45 +03:00
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
*class = ATA_DEV_NONE;
|
2007-08-06 13:36:23 +04:00
|
|
|
if (ata_link_online(link)) {
|
2007-01-03 11:32:45 +03:00
|
|
|
struct ata_taskfile tf;
|
|
|
|
|
2008-04-07 17:47:19 +04:00
|
|
|
/* wait for link to become ready */
|
2008-05-01 18:55:58 +04:00
|
|
|
rc = ata_wait_after_reset(link, deadline, inic_check_ready);
|
2007-02-02 10:50:52 +03:00
|
|
|
/* link occupied, -ENODEV too is an error */
|
|
|
|
if (rc) {
|
2007-08-06 13:36:23 +04:00
|
|
|
ata_link_printk(link, KERN_WARNING, "device not ready "
|
libata: add deadline support to prereset and reset methods
Add @deadline to prereset and reset methods and make them honor it.
ata_wait_ready() which directly takes @deadline is implemented to be
used as the wait function. This patch is in preparation for EH timing
improvements.
* ata_wait_ready() never does busy sleep. It's only used from EH and
no wait in EH is that urgent. This function also prints 'be
patient' message automatically after 5 secs of waiting if more than
3 secs is remaining till deadline.
* ata_bus_post_reset() now fails with error code if any of its wait
fails. This is important because earlier reset tries will have
shorter timeout than the spec requires. If a device fails to
respond before the short timeout, reset should be retried with
longer timeout rather than silently ignoring the device.
There are three behavior differences.
1. Timeout is applied to both devices at once, not separately. This
is more consistent with what the spec says.
2. When a device passes devchk but fails to become ready before
deadline. Previouly, post_reset would just succeed and let
device classification remove the device. New code fails the
reset thus causing reset retry. After a few times, EH will give
up disabling the port.
3. When slave device passes devchk but fails to become accessible
(TF-wise) after reset. Original code disables dev1 after 30s
timeout and continues as if the device doesn't exist, while the
patched code fails reset. When this happens, new code fails
reset on whole port rather than proceeding with only the primary
device.
If the failing device is suffering transient problems, new code
retries reset which is a better behavior. If the failing device is
actually broken, the net effect is identical to it, but not to the
other device sharing the channel. In the previous code, reset would
have succeeded after 30s thus detecting the working one. In the new
code, reset fails and whole port gets disabled. IMO, it's a
pathological case anyway (broken device sharing bus with working
one) and doesn't really matter.
* ata_bus_softreset() is changed to return error code from
ata_bus_post_reset(). It used to return 0 unconditionally.
* Spin up waiting is to be removed and not converted to honor
deadline.
* To be on the safe side, deadline is set to 40s for the time being.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-02-02 10:50:52 +03:00
|
|
|
"after hardreset (errno=%d)\n", rc);
|
|
|
|
return rc;
|
2007-01-03 11:32:45 +03:00
|
|
|
}
|
|
|
|
|
2008-05-01 18:55:58 +04:00
|
|
|
inic_tf_read(ap, &tf);
|
2007-01-03 11:32:45 +03:00
|
|
|
*class = ata_dev_classify(&tf);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void inic_error_handler(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
void __iomem *port_base = inic_port_base(ap);
|
|
|
|
|
|
|
|
inic_reset_port(port_base);
|
libata: make reset related methods proper port operations
Currently reset methods are not specified directly in the
ata_port_operations table. If a LLD wants to use custom reset
methods, it should construct and use a error_handler which uses those
reset methods. It's done this way for two reasons.
First, the ops table already contained too many methods and adding
four more of them would noticeably increase the amount of necessary
boilerplate code all over low level drivers.
Second, as ->error_handler uses those reset methods, it can get
confusing. ie. By overriding ->error_handler, those reset ops can be
made useless making layering a bit hazy.
Now that ops table uses inheritance, the first problem doesn't exist
anymore. The second isn't completely solved but is relieved by
providing default values - most drivers can just override what it has
implemented and don't have to concern itself about higher level
callbacks. In fact, there currently is no driver which actually
modifies error handling behavior. Drivers which override
->error_handler just wraps the standard error handler only to prepare
the controller for EH. I don't think making ops layering strict has
any noticeable benefit.
This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and
their PMP counterparts propoer ops. Default ops are provided in the
base ops tables and drivers are converted to override individual reset
methods instead of creating custom error_handler.
* ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs
aren't accessible. sata_promise doesn't need to use separate
error_handlers for PATA and SATA anymore.
* softreset is broken for sata_inic162x and sata_sx4. As libata now
always prefers hardreset, this doesn't really matter but the ops are
forced to NULL using ATA_OP_NULL for documentation purpose.
* pata_hpt374 needs to use different prereset for the first and second
PCI functions. This used to be done by branching from
hpt374_error_handler(). The proper way to do this is to use
separate ops and port_info tables for each function. Converted.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 06:22:50 +03:00
|
|
|
ata_std_error_handler(ap);
|
2007-01-03 11:32:45 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
|
|
|
|
{
|
|
|
|
/* make DMA engine forget about the failed command */
|
2007-03-20 09:24:11 +03:00
|
|
|
if (qc->flags & ATA_QCFLAG_FAILED)
|
2007-01-03 11:32:45 +03:00
|
|
|
inic_reset_port(inic_port_base(qc->ap));
|
|
|
|
}
|
|
|
|
|
|
|
|
static void init_port(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
void __iomem *port_base = inic_port_base(ap);
|
2008-04-30 11:35:11 +04:00
|
|
|
struct inic_port_priv *pp = ap->private_data;
|
2007-01-03 11:32:45 +03:00
|
|
|
|
2008-04-30 11:35:11 +04:00
|
|
|
/* clear packet and CPB table */
|
|
|
|
memset(pp->pkt, 0, sizeof(struct inic_pkt));
|
|
|
|
memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE);
|
|
|
|
|
|
|
|
/* setup PRD and CPB lookup table addresses */
|
2007-01-03 11:32:45 +03:00
|
|
|
writel(ap->prd_dma, port_base + PORT_PRD_ADDR);
|
2008-04-30 11:35:11 +04:00
|
|
|
writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR);
|
2007-01-03 11:32:45 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static int inic_port_resume(struct ata_port *ap)
|
|
|
|
{
|
|
|
|
init_port(ap);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int inic_port_start(struct ata_port *ap)
|
|
|
|
{
|
2008-04-30 11:35:11 +04:00
|
|
|
struct device *dev = ap->host->dev;
|
2007-01-03 11:32:45 +03:00
|
|
|
struct inic_port_priv *pp;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
/* alloc and initialize private data */
|
2008-04-30 11:35:11 +04:00
|
|
|
pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
|
2007-01-03 11:32:45 +03:00
|
|
|
if (!pp)
|
|
|
|
return -ENOMEM;
|
|
|
|
ap->private_data = pp;
|
|
|
|
|
|
|
|
/* Alloc resources */
|
|
|
|
rc = ata_port_start(ap);
|
2008-04-30 11:35:08 +04:00
|
|
|
if (rc)
|
2007-01-03 11:32:45 +03:00
|
|
|
return rc;
|
|
|
|
|
2008-04-30 11:35:11 +04:00
|
|
|
pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt),
|
|
|
|
&pp->pkt_dma, GFP_KERNEL);
|
|
|
|
if (!pp->pkt)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE,
|
|
|
|
&pp->cpb_tbl_dma, GFP_KERNEL);
|
|
|
|
if (!pp->cpb_tbl)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2007-01-03 11:32:45 +03:00
|
|
|
init_port(ap);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct ata_port_operations inic_port_ops = {
|
2008-04-30 11:35:15 +04:00
|
|
|
.inherits = &sata_port_ops,
|
2007-01-03 11:32:45 +03:00
|
|
|
|
2008-04-30 11:35:14 +04:00
|
|
|
.check_atapi_dma = inic_check_atapi_dma,
|
2008-04-30 11:35:11 +04:00
|
|
|
.qc_prep = inic_qc_prep,
|
2007-01-03 11:32:45 +03:00
|
|
|
.qc_issue = inic_qc_issue,
|
2008-05-01 18:55:58 +04:00
|
|
|
.qc_fill_rtf = inic_qc_fill_rtf,
|
2007-01-03 11:32:45 +03:00
|
|
|
|
|
|
|
.freeze = inic_freeze,
|
|
|
|
.thaw = inic_thaw,
|
libata: make reset related methods proper port operations
Currently reset methods are not specified directly in the
ata_port_operations table. If a LLD wants to use custom reset
methods, it should construct and use a error_handler which uses those
reset methods. It's done this way for two reasons.
First, the ops table already contained too many methods and adding
four more of them would noticeably increase the amount of necessary
boilerplate code all over low level drivers.
Second, as ->error_handler uses those reset methods, it can get
confusing. ie. By overriding ->error_handler, those reset ops can be
made useless making layering a bit hazy.
Now that ops table uses inheritance, the first problem doesn't exist
anymore. The second isn't completely solved but is relieved by
providing default values - most drivers can just override what it has
implemented and don't have to concern itself about higher level
callbacks. In fact, there currently is no driver which actually
modifies error handling behavior. Drivers which override
->error_handler just wraps the standard error handler only to prepare
the controller for EH. I don't think making ops layering strict has
any noticeable benefit.
This patch makes ->prereset, ->softreset, ->hardreset, ->postreset and
their PMP counterparts propoer ops. Default ops are provided in the
base ops tables and drivers are converted to override individual reset
methods instead of creating custom error_handler.
* ata_std_error_handler() doesn't use sata_std_hardreset() if SCRs
aren't accessible. sata_promise doesn't need to use separate
error_handlers for PATA and SATA anymore.
* softreset is broken for sata_inic162x and sata_sx4. As libata now
always prefers hardreset, this doesn't really matter but the ops are
forced to NULL using ATA_OP_NULL for documentation purpose.
* pata_hpt374 needs to use different prereset for the first and second
PCI functions. This used to be done by branching from
hpt374_error_handler(). The proper way to do this is to use
separate ops and port_info tables for each function. Converted.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 06:22:50 +03:00
|
|
|
.hardreset = inic_hardreset,
|
2007-01-03 11:32:45 +03:00
|
|
|
.error_handler = inic_error_handler,
|
|
|
|
.post_internal_cmd = inic_post_internal_cmd,
|
|
|
|
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 06:22:49 +03:00
|
|
|
.scr_read = inic_scr_read,
|
|
|
|
.scr_write = inic_scr_write,
|
2007-01-03 11:32:45 +03:00
|
|
|
|
libata: implement and use ops inheritance
libata lets low level drivers build ata_port_operations table and
register it with libata core layer. This allows low level drivers
high level of flexibility but also burdens them with lots of
boilerplate entries.
This becomes worse for drivers which support related similar
controllers which differ slightly. They share most of the operations
except for a few. However, the driver still needs to list all
operations for each variant. This results in large number of
duplicate entries, which is not only inefficient but also error-prone
as it becomes very difficult to tell what the actual differences are.
This duplicate boilerplates all over the low level drivers also make
updating the core layer exteremely difficult and error-prone. When
compounded with multi-branched development model, it ends up
accumulating inconsistencies over time. Some of those inconsistencies
cause immediate problems and fixed. Others just remain there dormant
making maintenance increasingly difficult.
To rectify the problem, this patch implements ata_port_operations
inheritance. To allow LLDs to easily re-use their own ops tables
overriding only specific methods, this patch implements poor man's
class inheritance. An ops table has ->inherits field which can be set
to any ops table as long as it doesn't create a loop. When the host
is started, the inheritance chain is followed and any operation which
isn't specified is taken from the nearest ancestor which has it
specified. This operation is called finalization and done only once
per an ops table and the LLD doesn't have to do anything special about
it other than making the ops table non-const such that libata can
update it.
libata provides four base ops tables lower drivers can inherit from -
base, sata, pmp, sff and bmdma. To avoid overriding these ops
accidentaly, these ops are declared const and LLDs should always
inherit these instead of using them directly.
After finalization, all the ops table are identical before and after
the patch except for setting .irq_handler to ata_interrupt in drivers
which didn't use to. The .irq_handler doesn't have any actual effect
and the field will soon be removed by later patch.
* sata_sx4 is still using old style EH and currently doesn't take
advantage of ops inheritance.
Signed-off-by: Tejun Heo <htejun@gmail.com>
2008-03-25 06:22:49 +03:00
|
|
|
.port_resume = inic_port_resume,
|
2007-01-03 11:32:45 +03:00
|
|
|
.port_start = inic_port_start,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct ata_port_info inic_port_info = {
|
|
|
|
.flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
|
|
|
|
.pio_mask = 0x1f, /* pio0-4 */
|
|
|
|
.mwdma_mask = 0x07, /* mwdma0-2 */
|
2007-07-09 20:16:50 +04:00
|
|
|
.udma_mask = ATA_UDMA6,
|
2007-01-03 11:32:45 +03:00
|
|
|
.port_ops = &inic_port_ops
|
|
|
|
};
|
|
|
|
|
|
|
|
static int init_controller(void __iomem *mmio_base, u16 hctl)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
u16 val;
|
|
|
|
|
|
|
|
hctl &= ~HCTL_KNOWN_BITS;
|
|
|
|
|
|
|
|
/* Soft reset whole controller. Spec says reset duration is 3
|
|
|
|
* PCI clocks, be generous and give it 10ms.
|
|
|
|
*/
|
|
|
|
writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
|
|
|
|
readw(mmio_base + HOST_CTL); /* flush */
|
|
|
|
|
|
|
|
for (i = 0; i < 10; i++) {
|
|
|
|
msleep(1);
|
|
|
|
val = readw(mmio_base + HOST_CTL);
|
|
|
|
if (!(val & HCTL_SOFTRST))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (val & HCTL_SOFTRST)
|
|
|
|
return -EIO;
|
|
|
|
|
|
|
|
/* mask all interrupts and reset ports */
|
|
|
|
for (i = 0; i < NR_PORTS; i++) {
|
|
|
|
void __iomem *port_base = mmio_base + i * PORT_SIZE;
|
|
|
|
|
|
|
|
writeb(0xff, port_base + PORT_IRQ_MASK);
|
|
|
|
inic_reset_port(port_base);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* port IRQ is masked now, unmask global IRQ */
|
|
|
|
writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
|
|
|
|
val = readw(mmio_base + HOST_IRQ_MASK);
|
|
|
|
val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
|
|
|
|
writew(val, mmio_base + HOST_IRQ_MASK);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2007-03-02 11:31:26 +03:00
|
|
|
#ifdef CONFIG_PM
|
2007-01-03 11:32:45 +03:00
|
|
|
static int inic_pci_device_resume(struct pci_dev *pdev)
|
|
|
|
{
|
|
|
|
struct ata_host *host = dev_get_drvdata(&pdev->dev);
|
|
|
|
struct inic_host_priv *hpriv = host->private_data;
|
|
|
|
int rc;
|
|
|
|
|
2007-03-06 13:37:54 +03:00
|
|
|
rc = ata_pci_device_do_resume(pdev);
|
|
|
|
if (rc)
|
|
|
|
return rc;
|
2007-01-03 11:32:45 +03:00
|
|
|
|
|
|
|
if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
|
2008-04-30 11:35:16 +04:00
|
|
|
rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
|
2007-01-03 11:32:45 +03:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
ata_host_resume(host);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
2007-03-02 11:31:26 +03:00
|
|
|
#endif
|
2007-01-03 11:32:45 +03:00
|
|
|
|
|
|
|
static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|
|
|
{
|
|
|
|
static int printed_version;
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 18:44:08 +04:00
|
|
|
const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
|
|
|
|
struct ata_host *host;
|
2007-01-03 11:32:45 +03:00
|
|
|
struct inic_host_priv *hpriv;
|
2007-02-01 09:06:36 +03:00
|
|
|
void __iomem * const *iomap;
|
2008-04-30 11:35:16 +04:00
|
|
|
int mmio_bar;
|
2007-01-03 11:32:45 +03:00
|
|
|
int i, rc;
|
|
|
|
|
|
|
|
if (!printed_version++)
|
|
|
|
dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
|
|
|
|
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 18:44:08 +04:00
|
|
|
/* alloc host */
|
|
|
|
host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
|
|
|
|
hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
|
|
|
|
if (!host || !hpriv)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
host->private_data = hpriv;
|
|
|
|
|
2008-04-30 11:35:16 +04:00
|
|
|
/* Acquire resources and fill host. Note that PCI and cardbus
|
|
|
|
* use different BARs.
|
|
|
|
*/
|
2007-01-20 10:00:28 +03:00
|
|
|
rc = pcim_enable_device(pdev);
|
2007-01-03 11:32:45 +03:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
|
|
|
|
2008-04-30 11:35:16 +04:00
|
|
|
if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM)
|
|
|
|
mmio_bar = MMIO_BAR_PCI;
|
|
|
|
else
|
|
|
|
mmio_bar = MMIO_BAR_CARDBUS;
|
|
|
|
|
|
|
|
rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME);
|
2007-02-01 09:06:36 +03:00
|
|
|
if (rc)
|
|
|
|
return rc;
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 18:44:08 +04:00
|
|
|
host->iomap = iomap = pcim_iomap_table(pdev);
|
2008-04-30 11:35:16 +04:00
|
|
|
hpriv->mmio_base = iomap[mmio_bar];
|
|
|
|
hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL);
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 18:44:08 +04:00
|
|
|
|
|
|
|
for (i = 0; i < NR_PORTS; i++) {
|
2007-08-18 08:14:55 +04:00
|
|
|
struct ata_port *ap = host->ports[i];
|
|
|
|
|
2008-04-30 11:35:16 +04:00
|
|
|
ata_port_pbar_desc(ap, mmio_bar, -1, "mmio");
|
|
|
|
ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port");
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 18:44:08 +04:00
|
|
|
}
|
|
|
|
|
2007-01-03 11:32:45 +03:00
|
|
|
/* Set dma_mask. This devices doesn't support 64bit addressing. */
|
|
|
|
rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
|
|
|
|
if (rc) {
|
|
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
|
|
|
"32-bit DMA enable failed\n");
|
2007-01-20 10:00:28 +03:00
|
|
|
return rc;
|
2007-01-03 11:32:45 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
|
|
|
|
if (rc) {
|
|
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
|
|
|
"32-bit consistent DMA enable failed\n");
|
2007-01-20 10:00:28 +03:00
|
|
|
return rc;
|
2007-01-03 11:32:45 +03:00
|
|
|
}
|
|
|
|
|
2008-02-05 09:28:05 +03:00
|
|
|
/*
|
|
|
|
* This controller is braindamaged. dma_boundary is 0xffff
|
|
|
|
* like others but it will lock up the whole machine HARD if
|
|
|
|
* 65536 byte PRD entry is fed. Reduce maximum segment size.
|
|
|
|
*/
|
|
|
|
rc = pci_set_dma_max_seg_size(pdev, 65536 - 512);
|
|
|
|
if (rc) {
|
|
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
|
|
|
"failed to set the maximum segment size.\n");
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2008-04-30 11:35:16 +04:00
|
|
|
rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
|
2007-01-03 11:32:45 +03:00
|
|
|
if (rc) {
|
|
|
|
dev_printk(KERN_ERR, &pdev->dev,
|
|
|
|
"failed to initialize controller\n");
|
2007-01-20 10:00:28 +03:00
|
|
|
return rc;
|
2007-01-03 11:32:45 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
pci_set_master(pdev);
|
libata: convert the remaining SATA drivers to new init model
Convert ahci, sata_sil, sata_sil24, sata_svw, sata_qstor, sata_mv,
sata_sx4, sata_vsc and sata_inic162x to new init model.
Now that host and ap are available during intialization, functions are
converted to take either host or ap instead of low level parameters
which were inevitable for functions shared between init and other
paths. This simplifies code quite a bit.
* init_one()'s now follow more consistent init order
* ahci_setup_port() and ahci_host_init() collapsed into
ahci_init_one() for init order consistency
* sata_vsc uses port_info instead of setting fields manually
* in sata_svw, k2_board_info converted to port_info (info is now in
port flags). port number is honored now.
Tested on ICH7/8 AHCI, jmb360, sil3112, 3114, 3124 and 3132.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
2007-04-17 18:44:08 +04:00
|
|
|
return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
|
|
|
|
&inic_sht);
|
2007-01-03 11:32:45 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const struct pci_device_id inic_pci_tbl[] = {
|
|
|
|
{ PCI_VDEVICE(INIT, 0x1622), },
|
|
|
|
{ },
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct pci_driver inic_pci_driver = {
|
|
|
|
.name = DRV_NAME,
|
|
|
|
.id_table = inic_pci_tbl,
|
2007-03-02 11:31:26 +03:00
|
|
|
#ifdef CONFIG_PM
|
2007-01-03 11:32:45 +03:00
|
|
|
.suspend = ata_pci_device_suspend,
|
|
|
|
.resume = inic_pci_device_resume,
|
2007-03-02 11:31:26 +03:00
|
|
|
#endif
|
2007-01-03 11:32:45 +03:00
|
|
|
.probe = inic_init_one,
|
|
|
|
.remove = ata_pci_remove_one,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init inic_init(void)
|
|
|
|
{
|
|
|
|
return pci_register_driver(&inic_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void __exit inic_exit(void)
|
|
|
|
{
|
|
|
|
pci_unregister_driver(&inic_pci_driver);
|
|
|
|
}
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Tejun Heo");
|
|
|
|
MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
|
|
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
|
|
|
|
module_init(inic_init);
|
|
|
|
module_exit(inic_exit);
|