2010-04-29 12:03:17 +04:00
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/*
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* Watchdog driver for IMX2 and later processors
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*
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* Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
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2014-01-13 15:58:34 +04:00
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* Copyright (C) 2014 Freescale Semiconductor, Inc.
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2010-04-29 12:03:17 +04:00
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*
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* some parts adapted by similar drivers from Darius Augulis and Vladimir
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* Zapolskiy, additional improvements by Wim Van Sebroeck.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* NOTE: MX1 has a slightly different Watchdog than MX2 and later:
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*
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* MX1: MX2+:
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* ---- -----
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* Registers: 32-bit 16-bit
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* Stopable timer: Yes No
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* Need to enable clk: No Yes
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* Halt on suspend: Manual Can be automatic
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*/
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2014-04-04 05:33:24 +04:00
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#include <linux/clk.h>
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2014-09-12 11:24:36 +04:00
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#include <linux/delay.h>
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2010-04-29 12:03:17 +04:00
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#include <linux/init.h>
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2016-10-07 15:41:39 +03:00
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#include <linux/interrupt.h>
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2014-04-04 05:33:24 +04:00
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#include <linux/io.h>
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2010-04-29 12:03:17 +04:00
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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2014-06-03 06:45:14 +04:00
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#include <linux/of_address.h>
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2010-04-29 12:03:17 +04:00
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#include <linux/platform_device.h>
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2014-04-04 05:33:25 +04:00
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#include <linux/regmap.h>
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2014-04-04 05:33:24 +04:00
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#include <linux/watchdog.h>
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2010-04-29 12:03:17 +04:00
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#define DRIVER_NAME "imx2-wdt"
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#define IMX2_WDT_WCR 0x00 /* Control Register */
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#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
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2016-08-31 14:52:49 +03:00
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#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
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#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
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#define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
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#define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
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#define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
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2010-04-29 12:03:17 +04:00
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#define IMX2_WDT_WSR 0x02 /* Service Register */
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#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
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#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
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2012-02-16 16:17:45 +04:00
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#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
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2016-08-31 14:52:49 +03:00
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#define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */
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2012-02-16 16:17:45 +04:00
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2016-10-07 15:41:39 +03:00
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#define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */
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#define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */
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#define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */
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#define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */
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2014-09-08 11:14:07 +04:00
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#define IMX2_WDT_WMCR 0x08 /* Misc Register */
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2010-04-29 12:03:17 +04:00
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#define IMX2_WDT_MAX_TIME 128
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#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
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#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
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2014-04-11 10:57:14 +04:00
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struct imx2_wdt_device {
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2010-04-29 12:03:17 +04:00
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struct clk *clk;
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2014-04-04 05:33:25 +04:00
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struct regmap *regmap;
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2014-04-11 10:57:14 +04:00
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struct watchdog_device wdog;
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2016-04-01 18:16:43 +03:00
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bool ext_reset;
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2014-04-11 10:57:14 +04:00
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};
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2010-04-29 12:03:17 +04:00
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2012-03-05 19:51:11 +04:00
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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2010-04-29 12:03:17 +04:00
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MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
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module_param(timeout, uint, 0);
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MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
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__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
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static const struct watchdog_info imx2_wdt_info = {
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.identity = "imx2+ watchdog",
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.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
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};
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2016-10-07 15:41:39 +03:00
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static const struct watchdog_info imx2_wdt_pretimeout_info = {
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.identity = "imx2+ watchdog",
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.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
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WDIOF_PRETIMEOUT,
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};
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2016-02-27 04:32:49 +03:00
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static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
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void *data)
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2014-09-12 11:24:36 +04:00
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{
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2015-11-16 20:28:04 +03:00
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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2014-09-12 11:24:36 +04:00
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unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
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2015-11-16 20:28:04 +03:00
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2016-04-01 18:16:43 +03:00
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/* Use internal reset or external - not both */
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if (wdev->ext_reset)
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wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
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else
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wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
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2014-09-12 11:24:36 +04:00
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/* Assert SRS signal */
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2015-10-02 06:25:28 +03:00
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regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
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2014-09-12 11:24:36 +04:00
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/*
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* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
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* written twice), we add another two writes to ensure there must be at
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* least two writes happen in the same one 32kHz clock period. We save
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* the target check here, since the writes shouldn't be a huge burden
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* for other platforms.
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*/
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2015-10-02 06:25:28 +03:00
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regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
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regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
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2014-09-12 11:24:36 +04:00
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/* wait for reset to assert... */
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mdelay(500);
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2015-11-16 20:28:04 +03:00
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return 0;
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2014-09-12 11:24:36 +04:00
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}
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2014-04-11 10:57:14 +04:00
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static inline void imx2_wdt_setup(struct watchdog_device *wdog)
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2010-04-29 12:03:17 +04:00
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{
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2014-04-11 10:57:14 +04:00
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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2014-04-04 05:33:25 +04:00
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u32 val;
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2014-04-11 10:57:14 +04:00
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regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
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2010-04-29 12:03:17 +04:00
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2014-01-13 15:58:34 +04:00
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/* Suspend timer in low power mode, write once-only */
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val |= IMX2_WDT_WCR_WDZST;
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2010-04-29 12:03:17 +04:00
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/* Strip the old watchdog Time-Out value */
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val &= ~IMX2_WDT_WCR_WT;
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2016-04-01 18:16:43 +03:00
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/* Generate internal chip-level reset if WDOG times out */
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if (!wdev->ext_reset)
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val &= ~IMX2_WDT_WCR_WRE;
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/* Or if external-reset assert WDOG_B reset only on time-out */
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else
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val |= IMX2_WDT_WCR_WRE;
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2010-04-29 12:03:17 +04:00
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/* Keep Watchdog Disabled */
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val &= ~IMX2_WDT_WCR_WDE;
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/* Set the watchdog's Time-Out value */
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2014-04-11 10:57:14 +04:00
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val |= WDOG_SEC_TO_COUNT(wdog->timeout);
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2010-04-29 12:03:17 +04:00
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2014-04-11 10:57:14 +04:00
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regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
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2010-04-29 12:03:17 +04:00
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/* enable the watchdog */
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val |= IMX2_WDT_WCR_WDE;
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2014-04-11 10:57:14 +04:00
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regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
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2010-04-29 12:03:17 +04:00
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}
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2014-04-11 10:57:14 +04:00
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static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
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2010-04-29 12:03:17 +04:00
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{
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2014-04-11 10:57:14 +04:00
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u32 val;
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2010-04-29 12:03:17 +04:00
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2014-04-11 10:57:14 +04:00
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regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
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return val & IMX2_WDT_WCR_WDE;
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2010-04-29 12:03:17 +04:00
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}
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2014-04-11 10:57:14 +04:00
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static int imx2_wdt_ping(struct watchdog_device *wdog)
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2010-04-29 12:03:17 +04:00
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{
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2014-04-11 10:57:14 +04:00
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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2010-04-29 12:03:17 +04:00
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2014-04-11 10:57:14 +04:00
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regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
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regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
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return 0;
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2010-04-29 12:03:17 +04:00
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}
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2014-04-11 10:57:14 +04:00
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static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
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unsigned int new_timeout)
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2010-04-29 12:03:17 +04:00
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{
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2014-04-11 10:57:14 +04:00
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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2015-05-06 14:17:59 +03:00
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wdog->timeout = new_timeout;
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2014-04-11 10:57:14 +04:00
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regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
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2014-04-04 05:33:25 +04:00
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WDOG_SEC_TO_COUNT(new_timeout));
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2014-04-11 10:57:14 +04:00
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return 0;
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2010-04-29 12:03:17 +04:00
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}
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2016-10-07 15:41:39 +03:00
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static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
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unsigned int new_pretimeout)
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{
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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if (new_pretimeout >= IMX2_WDT_MAX_TIME)
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return -EINVAL;
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wdog->pretimeout = new_pretimeout;
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regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
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IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
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IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
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return 0;
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}
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static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
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{
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struct watchdog_device *wdog = wdog_arg;
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
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IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
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watchdog_notify_pretimeout(wdog);
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return IRQ_HANDLED;
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}
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2014-04-11 10:57:14 +04:00
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static int imx2_wdt_start(struct watchdog_device *wdog)
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2010-04-29 12:03:17 +04:00
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{
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2014-04-11 10:57:14 +04:00
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struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
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2010-04-29 12:03:17 +04:00
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2016-02-29 00:12:20 +03:00
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if (imx2_wdt_is_running(wdev))
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2014-04-11 10:57:14 +04:00
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imx2_wdt_set_timeout(wdog, wdog->timeout);
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2016-02-29 00:12:20 +03:00
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else
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2014-04-11 10:57:14 +04:00
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imx2_wdt_setup(wdog);
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2016-02-29 00:12:20 +03:00
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set_bit(WDOG_HW_RUNNING, &wdog->status);
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2010-04-29 12:03:17 +04:00
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2016-02-29 00:12:20 +03:00
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return imx2_wdt_ping(wdog);
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2010-04-29 12:03:17 +04:00
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}
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2015-01-05 12:09:17 +03:00
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static const struct watchdog_ops imx2_wdt_ops = {
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2010-04-29 12:03:17 +04:00
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.owner = THIS_MODULE,
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2014-04-11 10:57:14 +04:00
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.start = imx2_wdt_start,
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.ping = imx2_wdt_ping,
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.set_timeout = imx2_wdt_set_timeout,
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2016-10-07 15:41:39 +03:00
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.set_pretimeout = imx2_wdt_set_pretimeout,
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2015-11-16 20:28:04 +03:00
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.restart = imx2_wdt_restart,
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2010-04-29 12:03:17 +04:00
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};
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2015-01-05 12:09:17 +03:00
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static const struct regmap_config imx2_wdt_regmap_config = {
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2014-04-04 05:33:25 +04:00
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.reg_bits = 16,
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.reg_stride = 2,
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.val_bits = 16,
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.max_register = 0x8,
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};
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2010-04-29 12:03:17 +04:00
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static int __init imx2_wdt_probe(struct platform_device *pdev)
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{
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2014-04-11 10:57:14 +04:00
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struct imx2_wdt_device *wdev;
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struct watchdog_device *wdog;
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2010-04-29 12:03:17 +04:00
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struct resource *res;
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2014-04-04 05:33:25 +04:00
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void __iomem *base;
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int ret;
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2014-04-11 10:57:14 +04:00
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u32 val;
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wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
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if (!wdev)
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return -ENOMEM;
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2010-04-29 12:03:17 +04:00
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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2014-04-04 05:33:25 +04:00
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base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(base))
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return PTR_ERR(base);
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2014-04-11 10:57:14 +04:00
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wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
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&imx2_wdt_regmap_config);
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if (IS_ERR(wdev->regmap)) {
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2014-04-04 05:33:25 +04:00
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dev_err(&pdev->dev, "regmap init failed\n");
|
2014-04-11 10:57:14 +04:00
|
|
|
return PTR_ERR(wdev->regmap);
|
2014-04-04 05:33:25 +04:00
|
|
|
}
|
2010-04-29 12:03:17 +04:00
|
|
|
|
2014-04-11 10:57:14 +04:00
|
|
|
wdev->clk = devm_clk_get(&pdev->dev, NULL);
|
|
|
|
if (IS_ERR(wdev->clk)) {
|
2010-04-29 12:03:17 +04:00
|
|
|
dev_err(&pdev->dev, "can't get Watchdog clock\n");
|
2014-04-11 10:57:14 +04:00
|
|
|
return PTR_ERR(wdev->clk);
|
2010-04-29 12:03:17 +04:00
|
|
|
}
|
|
|
|
|
2014-04-11 10:57:14 +04:00
|
|
|
wdog = &wdev->wdog;
|
|
|
|
wdog->info = &imx2_wdt_info;
|
|
|
|
wdog->ops = &imx2_wdt_ops;
|
|
|
|
wdog->min_timeout = 1;
|
2016-02-29 00:12:20 +03:00
|
|
|
wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
|
2015-06-02 15:46:18 +03:00
|
|
|
wdog->parent = &pdev->dev;
|
2010-04-29 12:03:17 +04:00
|
|
|
|
2016-10-07 15:41:39 +03:00
|
|
|
ret = platform_get_irq(pdev, 0);
|
|
|
|
if (ret > 0)
|
|
|
|
if (!devm_request_irq(&pdev->dev, ret, imx2_wdt_isr, 0,
|
|
|
|
dev_name(&pdev->dev), wdog))
|
|
|
|
wdog->info = &imx2_wdt_pretimeout_info;
|
|
|
|
|
2015-06-22 07:16:18 +03:00
|
|
|
ret = clk_prepare_enable(wdev->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2010-04-29 12:03:17 +04:00
|
|
|
|
2014-04-11 10:57:14 +04:00
|
|
|
regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
|
|
|
|
wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
|
2010-04-29 12:03:17 +04:00
|
|
|
|
2016-04-01 18:16:43 +03:00
|
|
|
wdev->ext_reset = of_property_read_bool(pdev->dev.of_node,
|
|
|
|
"fsl,ext-reset-output");
|
2014-04-11 10:57:14 +04:00
|
|
|
wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
|
|
|
|
if (wdog->timeout != timeout)
|
|
|
|
dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
|
|
|
|
timeout, wdog->timeout);
|
|
|
|
|
|
|
|
platform_set_drvdata(pdev, wdog);
|
|
|
|
watchdog_set_drvdata(wdog, wdev);
|
|
|
|
watchdog_set_nowayout(wdog, nowayout);
|
2015-11-16 20:28:04 +03:00
|
|
|
watchdog_set_restart_priority(wdog, 128);
|
2014-04-11 10:57:14 +04:00
|
|
|
watchdog_init_timeout(wdog, timeout, &pdev->dev);
|
|
|
|
|
2016-02-29 00:12:20 +03:00
|
|
|
if (imx2_wdt_is_running(wdev)) {
|
|
|
|
imx2_wdt_set_timeout(wdog, wdog->timeout);
|
|
|
|
set_bit(WDOG_HW_RUNNING, &wdog->status);
|
|
|
|
}
|
2014-04-11 10:57:14 +04:00
|
|
|
|
2014-09-08 11:14:07 +04:00
|
|
|
/*
|
|
|
|
* Disable the watchdog power down counter at boot. Otherwise the power
|
|
|
|
* down counter will pull down the #WDOG interrupt line for one clock
|
|
|
|
* cycle.
|
|
|
|
*/
|
|
|
|
regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
|
|
|
|
|
2014-04-11 10:57:14 +04:00
|
|
|
ret = watchdog_register_device(wdog);
|
|
|
|
if (ret) {
|
|
|
|
dev_err(&pdev->dev, "cannot register watchdog device\n");
|
2015-06-22 07:16:19 +03:00
|
|
|
goto disable_clk;
|
2014-04-11 10:57:14 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
|
|
|
|
wdog->timeout, nowayout);
|
|
|
|
|
|
|
|
return 0;
|
2015-06-22 07:16:19 +03:00
|
|
|
|
|
|
|
disable_clk:
|
|
|
|
clk_disable_unprepare(wdev->clk);
|
|
|
|
return ret;
|
2010-04-29 12:03:17 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static int __exit imx2_wdt_remove(struct platform_device *pdev)
|
|
|
|
{
|
2014-04-11 10:57:14 +04:00
|
|
|
struct watchdog_device *wdog = platform_get_drvdata(pdev);
|
|
|
|
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
|
2010-04-29 12:03:17 +04:00
|
|
|
|
2014-04-11 10:57:14 +04:00
|
|
|
watchdog_unregister_device(wdog);
|
2010-04-29 12:03:17 +04:00
|
|
|
|
2014-04-11 10:57:14 +04:00
|
|
|
if (imx2_wdt_is_running(wdev)) {
|
|
|
|
imx2_wdt_ping(wdog);
|
|
|
|
dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
|
2013-04-29 13:15:53 +04:00
|
|
|
}
|
2010-04-29 12:03:17 +04:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void imx2_wdt_shutdown(struct platform_device *pdev)
|
|
|
|
{
|
2014-04-11 10:57:14 +04:00
|
|
|
struct watchdog_device *wdog = platform_get_drvdata(pdev);
|
|
|
|
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
|
|
|
|
|
|
|
|
if (imx2_wdt_is_running(wdev)) {
|
|
|
|
/*
|
2016-02-29 00:12:20 +03:00
|
|
|
* We are running, configure max timeout before reboot
|
|
|
|
* will take place.
|
2014-04-11 10:57:14 +04:00
|
|
|
*/
|
|
|
|
imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
|
|
|
|
imx2_wdt_ping(wdog);
|
|
|
|
dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
|
2010-04-29 12:03:17 +04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-09-22 14:00:52 +04:00
|
|
|
#ifdef CONFIG_PM_SLEEP
|
2014-10-16 07:44:15 +04:00
|
|
|
/* Disable watchdog if it is active or non-active but still running */
|
2014-09-22 14:00:52 +04:00
|
|
|
static int imx2_wdt_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct watchdog_device *wdog = dev_get_drvdata(dev);
|
|
|
|
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
|
|
|
|
|
2014-10-16 07:44:15 +04:00
|
|
|
/* The watchdog IP block is running */
|
|
|
|
if (imx2_wdt_is_running(wdev)) {
|
|
|
|
imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
|
|
|
|
imx2_wdt_ping(wdog);
|
|
|
|
}
|
2014-09-22 14:00:52 +04:00
|
|
|
|
|
|
|
clk_disable_unprepare(wdev->clk);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Enable watchdog and configure it if necessary */
|
|
|
|
static int imx2_wdt_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct watchdog_device *wdog = dev_get_drvdata(dev);
|
|
|
|
struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
|
2015-06-22 07:16:18 +03:00
|
|
|
int ret;
|
2014-09-22 14:00:52 +04:00
|
|
|
|
2015-06-22 07:16:18 +03:00
|
|
|
ret = clk_prepare_enable(wdev->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2014-09-22 14:00:52 +04:00
|
|
|
|
|
|
|
if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
|
2014-10-16 07:44:15 +04:00
|
|
|
/*
|
|
|
|
* If the watchdog is still active and resumes
|
|
|
|
* from deep sleep state, need to restart the
|
|
|
|
* watchdog again.
|
2014-09-22 14:00:52 +04:00
|
|
|
*/
|
|
|
|
imx2_wdt_setup(wdog);
|
2016-02-29 00:12:20 +03:00
|
|
|
}
|
|
|
|
if (imx2_wdt_is_running(wdev)) {
|
2014-09-22 14:00:52 +04:00
|
|
|
imx2_wdt_set_timeout(wdog, wdog->timeout);
|
|
|
|
imx2_wdt_ping(wdog);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
|
|
|
|
imx2_wdt_resume);
|
|
|
|
|
2011-07-18 07:15:21 +04:00
|
|
|
static const struct of_device_id imx2_wdt_dt_ids[] = {
|
|
|
|
{ .compatible = "fsl,imx21-wdt", },
|
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
2013-07-29 11:38:18 +04:00
|
|
|
MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
|
2011-07-18 07:15:21 +04:00
|
|
|
|
2010-04-29 12:03:17 +04:00
|
|
|
static struct platform_driver imx2_wdt_driver = {
|
|
|
|
.remove = __exit_p(imx2_wdt_remove),
|
|
|
|
.shutdown = imx2_wdt_shutdown,
|
|
|
|
.driver = {
|
|
|
|
.name = DRIVER_NAME,
|
2014-09-22 14:00:52 +04:00
|
|
|
.pm = &imx2_wdt_pm_ops,
|
2011-07-18 07:15:21 +04:00
|
|
|
.of_match_table = imx2_wdt_dt_ids,
|
2010-04-29 12:03:17 +04:00
|
|
|
},
|
|
|
|
};
|
|
|
|
|
2013-01-09 15:15:27 +04:00
|
|
|
module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
|
2010-04-29 12:03:17 +04:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Wolfram Sang");
|
|
|
|
MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|