2016-02-05 07:34:34 +03:00
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/*
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* Qualcomm Technologies HIDMA DMA engine Management interface
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*
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2016-05-01 07:25:28 +03:00
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* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
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2016-02-05 07:34:34 +03:00
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/dmaengine.h>
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#include <linux/acpi.h>
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#include <linux/of.h>
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#include <linux/property.h>
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2016-05-01 07:25:28 +03:00
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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2016-02-05 07:34:34 +03:00
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#include <linux/module.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/bitops.h>
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2016-05-01 07:25:28 +03:00
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#include <linux/dma-mapping.h>
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2016-02-05 07:34:34 +03:00
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#include "hidma_mgmt.h"
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#define HIDMA_QOS_N_OFFSET 0x300
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#define HIDMA_CFG_OFFSET 0x400
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#define HIDMA_MAX_BUS_REQ_LEN_OFFSET 0x41C
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#define HIDMA_MAX_XACTIONS_OFFSET 0x420
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#define HIDMA_HW_VERSION_OFFSET 0x424
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#define HIDMA_CHRESET_TIMEOUT_OFFSET 0x418
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#define HIDMA_MAX_WR_XACTIONS_MASK GENMASK(4, 0)
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#define HIDMA_MAX_RD_XACTIONS_MASK GENMASK(4, 0)
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#define HIDMA_WEIGHT_MASK GENMASK(6, 0)
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#define HIDMA_MAX_BUS_REQ_LEN_MASK GENMASK(15, 0)
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#define HIDMA_CHRESET_TIMEOUT_MASK GENMASK(19, 0)
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#define HIDMA_MAX_WR_XACTIONS_BIT_POS 16
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#define HIDMA_MAX_BUS_WR_REQ_BIT_POS 16
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#define HIDMA_WRR_BIT_POS 8
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#define HIDMA_PRIORITY_BIT_POS 15
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#define HIDMA_AUTOSUSPEND_TIMEOUT 2000
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#define HIDMA_MAX_CHANNEL_WEIGHT 15
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int hidma_mgmt_setup(struct hidma_mgmt_dev *mgmtdev)
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{
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unsigned int i;
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u32 val;
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if (!is_power_of_2(mgmtdev->max_write_request) ||
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(mgmtdev->max_write_request < 128) ||
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(mgmtdev->max_write_request > 1024)) {
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dev_err(&mgmtdev->pdev->dev, "invalid write request %d\n",
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mgmtdev->max_write_request);
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return -EINVAL;
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}
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if (!is_power_of_2(mgmtdev->max_read_request) ||
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(mgmtdev->max_read_request < 128) ||
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(mgmtdev->max_read_request > 1024)) {
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dev_err(&mgmtdev->pdev->dev, "invalid read request %d\n",
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mgmtdev->max_read_request);
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return -EINVAL;
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}
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if (mgmtdev->max_wr_xactions > HIDMA_MAX_WR_XACTIONS_MASK) {
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dev_err(&mgmtdev->pdev->dev,
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"max_wr_xactions cannot be bigger than %ld\n",
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HIDMA_MAX_WR_XACTIONS_MASK);
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return -EINVAL;
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}
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if (mgmtdev->max_rd_xactions > HIDMA_MAX_RD_XACTIONS_MASK) {
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dev_err(&mgmtdev->pdev->dev,
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"max_rd_xactions cannot be bigger than %ld\n",
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HIDMA_MAX_RD_XACTIONS_MASK);
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return -EINVAL;
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}
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for (i = 0; i < mgmtdev->dma_channels; i++) {
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if (mgmtdev->priority[i] > 1) {
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dev_err(&mgmtdev->pdev->dev,
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"priority can be 0 or 1\n");
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return -EINVAL;
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}
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if (mgmtdev->weight[i] > HIDMA_MAX_CHANNEL_WEIGHT) {
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dev_err(&mgmtdev->pdev->dev,
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"max value of weight can be %d.\n",
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HIDMA_MAX_CHANNEL_WEIGHT);
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return -EINVAL;
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}
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/* weight needs to be at least one */
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if (mgmtdev->weight[i] == 0)
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mgmtdev->weight[i] = 1;
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}
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pm_runtime_get_sync(&mgmtdev->pdev->dev);
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val = readl(mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
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val &= ~(HIDMA_MAX_BUS_REQ_LEN_MASK << HIDMA_MAX_BUS_WR_REQ_BIT_POS);
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val |= mgmtdev->max_write_request << HIDMA_MAX_BUS_WR_REQ_BIT_POS;
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val &= ~HIDMA_MAX_BUS_REQ_LEN_MASK;
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val |= mgmtdev->max_read_request;
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writel(val, mgmtdev->virtaddr + HIDMA_MAX_BUS_REQ_LEN_OFFSET);
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val = readl(mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
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val &= ~(HIDMA_MAX_WR_XACTIONS_MASK << HIDMA_MAX_WR_XACTIONS_BIT_POS);
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val |= mgmtdev->max_wr_xactions << HIDMA_MAX_WR_XACTIONS_BIT_POS;
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val &= ~HIDMA_MAX_RD_XACTIONS_MASK;
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val |= mgmtdev->max_rd_xactions;
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writel(val, mgmtdev->virtaddr + HIDMA_MAX_XACTIONS_OFFSET);
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mgmtdev->hw_version =
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readl(mgmtdev->virtaddr + HIDMA_HW_VERSION_OFFSET);
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mgmtdev->hw_version_major = (mgmtdev->hw_version >> 28) & 0xF;
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mgmtdev->hw_version_minor = (mgmtdev->hw_version >> 16) & 0xF;
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for (i = 0; i < mgmtdev->dma_channels; i++) {
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u32 weight = mgmtdev->weight[i];
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u32 priority = mgmtdev->priority[i];
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val = readl(mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
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val &= ~(1 << HIDMA_PRIORITY_BIT_POS);
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val |= (priority & 0x1) << HIDMA_PRIORITY_BIT_POS;
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val &= ~(HIDMA_WEIGHT_MASK << HIDMA_WRR_BIT_POS);
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val |= (weight & HIDMA_WEIGHT_MASK) << HIDMA_WRR_BIT_POS;
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writel(val, mgmtdev->virtaddr + HIDMA_QOS_N_OFFSET + (4 * i));
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}
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val = readl(mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
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val &= ~HIDMA_CHRESET_TIMEOUT_MASK;
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val |= mgmtdev->chreset_timeout_cycles & HIDMA_CHRESET_TIMEOUT_MASK;
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writel(val, mgmtdev->virtaddr + HIDMA_CHRESET_TIMEOUT_OFFSET);
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pm_runtime_mark_last_busy(&mgmtdev->pdev->dev);
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pm_runtime_put_autosuspend(&mgmtdev->pdev->dev);
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return 0;
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}
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EXPORT_SYMBOL_GPL(hidma_mgmt_setup);
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static int hidma_mgmt_probe(struct platform_device *pdev)
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{
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struct hidma_mgmt_dev *mgmtdev;
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struct resource *res;
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void __iomem *virtaddr;
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int irq;
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int rc;
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u32 val;
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pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT);
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pm_runtime_use_autosuspend(&pdev->dev);
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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pm_runtime_get_sync(&pdev->dev);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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virtaddr = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(virtaddr)) {
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rc = -ENOMEM;
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goto out;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "irq resources not found\n");
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rc = irq;
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goto out;
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}
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mgmtdev = devm_kzalloc(&pdev->dev, sizeof(*mgmtdev), GFP_KERNEL);
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if (!mgmtdev) {
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rc = -ENOMEM;
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goto out;
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}
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mgmtdev->pdev = pdev;
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mgmtdev->addrsize = resource_size(res);
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mgmtdev->virtaddr = virtaddr;
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rc = device_property_read_u32(&pdev->dev, "dma-channels",
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&mgmtdev->dma_channels);
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if (rc) {
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dev_err(&pdev->dev, "number of channels missing\n");
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goto out;
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}
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rc = device_property_read_u32(&pdev->dev,
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"channel-reset-timeout-cycles",
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&mgmtdev->chreset_timeout_cycles);
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if (rc) {
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dev_err(&pdev->dev, "channel reset timeout missing\n");
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goto out;
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}
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rc = device_property_read_u32(&pdev->dev, "max-write-burst-bytes",
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&mgmtdev->max_write_request);
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if (rc) {
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dev_err(&pdev->dev, "max-write-burst-bytes missing\n");
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goto out;
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}
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rc = device_property_read_u32(&pdev->dev, "max-read-burst-bytes",
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&mgmtdev->max_read_request);
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if (rc) {
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dev_err(&pdev->dev, "max-read-burst-bytes missing\n");
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goto out;
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}
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rc = device_property_read_u32(&pdev->dev, "max-write-transactions",
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&mgmtdev->max_wr_xactions);
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if (rc) {
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dev_err(&pdev->dev, "max-write-transactions missing\n");
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goto out;
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}
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rc = device_property_read_u32(&pdev->dev, "max-read-transactions",
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&mgmtdev->max_rd_xactions);
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if (rc) {
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dev_err(&pdev->dev, "max-read-transactions missing\n");
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goto out;
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}
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mgmtdev->priority = devm_kcalloc(&pdev->dev,
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mgmtdev->dma_channels,
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sizeof(*mgmtdev->priority),
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GFP_KERNEL);
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if (!mgmtdev->priority) {
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rc = -ENOMEM;
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goto out;
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}
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mgmtdev->weight = devm_kcalloc(&pdev->dev,
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mgmtdev->dma_channels,
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sizeof(*mgmtdev->weight), GFP_KERNEL);
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if (!mgmtdev->weight) {
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rc = -ENOMEM;
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goto out;
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}
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rc = hidma_mgmt_setup(mgmtdev);
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if (rc) {
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dev_err(&pdev->dev, "setup failed\n");
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goto out;
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}
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/* start the HW */
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val = readl(mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
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val |= 1;
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writel(val, mgmtdev->virtaddr + HIDMA_CFG_OFFSET);
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rc = hidma_mgmt_init_sys(mgmtdev);
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if (rc) {
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dev_err(&pdev->dev, "sysfs setup failed\n");
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goto out;
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}
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dev_info(&pdev->dev,
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"HW rev: %d.%d @ %pa with %d physical channels\n",
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mgmtdev->hw_version_major, mgmtdev->hw_version_minor,
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&res->start, mgmtdev->dma_channels);
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platform_set_drvdata(pdev, mgmtdev);
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pm_runtime_mark_last_busy(&pdev->dev);
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pm_runtime_put_autosuspend(&pdev->dev);
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return 0;
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out:
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pm_runtime_put_sync_suspend(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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return rc;
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}
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#if IS_ENABLED(CONFIG_ACPI)
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static const struct acpi_device_id hidma_mgmt_acpi_ids[] = {
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{"QCOM8060"},
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{},
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};
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#endif
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static const struct of_device_id hidma_mgmt_match[] = {
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{.compatible = "qcom,hidma-mgmt-1.0",},
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{},
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};
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MODULE_DEVICE_TABLE(of, hidma_mgmt_match);
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static struct platform_driver hidma_mgmt_driver = {
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.probe = hidma_mgmt_probe,
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.driver = {
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.name = "hidma-mgmt",
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.of_match_table = hidma_mgmt_match,
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.acpi_match_table = ACPI_PTR(hidma_mgmt_acpi_ids),
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},
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};
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|
2016-05-01 07:25:28 +03:00
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#if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
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static int object_counter;
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static int __init hidma_mgmt_of_populate_channels(struct device_node *np)
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{
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struct platform_device *pdev_parent = of_find_device_by_node(np);
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struct platform_device_info pdevinfo;
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struct of_phandle_args out_irq;
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struct device_node *child;
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struct resource *res;
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const __be32 *cell;
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int ret = 0, size, i, num;
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u64 addr, addr_size;
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for_each_available_child_of_node(np, child) {
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struct resource *res_iter;
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struct platform_device *new_pdev;
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cell = of_get_property(child, "reg", &size);
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if (!cell) {
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ret = -EINVAL;
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goto out;
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}
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size /= sizeof(*cell);
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num = size /
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(of_n_addr_cells(child) + of_n_size_cells(child)) + 1;
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/* allocate a resource array */
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res = kcalloc(num, sizeof(*res), GFP_KERNEL);
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if (!res) {
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ret = -ENOMEM;
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goto out;
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}
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/* read each reg value */
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i = 0;
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res_iter = res;
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while (i < size) {
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addr = of_read_number(&cell[i],
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of_n_addr_cells(child));
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i += of_n_addr_cells(child);
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addr_size = of_read_number(&cell[i],
|
|
|
|
of_n_size_cells(child));
|
|
|
|
i += of_n_size_cells(child);
|
|
|
|
|
|
|
|
res_iter->start = addr;
|
|
|
|
res_iter->end = res_iter->start + addr_size - 1;
|
|
|
|
res_iter->flags = IORESOURCE_MEM;
|
|
|
|
res_iter++;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = of_irq_parse_one(child, 0, &out_irq);
|
|
|
|
if (ret)
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
res_iter->start = irq_create_of_mapping(&out_irq);
|
|
|
|
res_iter->name = "hidma event irq";
|
|
|
|
res_iter->flags = IORESOURCE_IRQ;
|
|
|
|
|
|
|
|
memset(&pdevinfo, 0, sizeof(pdevinfo));
|
|
|
|
pdevinfo.fwnode = &child->fwnode;
|
|
|
|
pdevinfo.parent = pdev_parent ? &pdev_parent->dev : NULL;
|
|
|
|
pdevinfo.name = child->name;
|
|
|
|
pdevinfo.id = object_counter++;
|
|
|
|
pdevinfo.res = res;
|
|
|
|
pdevinfo.num_res = num;
|
|
|
|
pdevinfo.data = NULL;
|
|
|
|
pdevinfo.size_data = 0;
|
|
|
|
pdevinfo.dma_mask = DMA_BIT_MASK(64);
|
|
|
|
new_pdev = platform_device_register_full(&pdevinfo);
|
2016-07-06 15:19:09 +03:00
|
|
|
if (IS_ERR(new_pdev)) {
|
|
|
|
ret = PTR_ERR(new_pdev);
|
2016-05-01 07:25:28 +03:00
|
|
|
goto out;
|
|
|
|
}
|
2016-10-07 08:25:09 +03:00
|
|
|
of_node_get(child);
|
|
|
|
new_pdev->dev.of_node = child;
|
2016-05-01 07:25:28 +03:00
|
|
|
of_dma_configure(&new_pdev->dev, child);
|
2016-10-07 08:25:09 +03:00
|
|
|
/*
|
|
|
|
* It is assumed that calling of_msi_configure is safe on
|
|
|
|
* platforms with or without MSI support.
|
|
|
|
*/
|
|
|
|
of_msi_configure(&new_pdev->dev, child);
|
|
|
|
of_node_put(child);
|
2016-05-01 07:25:28 +03:00
|
|
|
kfree(res);
|
|
|
|
res = NULL;
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
kfree(res);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static int __init hidma_mgmt_init(void)
|
|
|
|
{
|
|
|
|
#if defined(CONFIG_OF) && defined(CONFIG_OF_IRQ)
|
|
|
|
struct device_node *child;
|
|
|
|
|
2016-07-13 15:55:06 +03:00
|
|
|
for_each_matching_node(child, hidma_mgmt_match) {
|
2016-05-01 07:25:28 +03:00
|
|
|
/* device tree based firmware here */
|
|
|
|
hidma_mgmt_of_populate_channels(child);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
platform_driver_register(&hidma_mgmt_driver);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
module_init(hidma_mgmt_init);
|
2016-02-05 07:34:34 +03:00
|
|
|
MODULE_LICENSE("GPL v2");
|