2009-01-19 14:33:24 +03:00
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/*
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* GE Fanuc SBC310 Device Tree Source
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*
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* Copyright 2008 GE Fanuc Intelligent Platforms Embedded Systems, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Based on: SBS CM6 Device Tree Source
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* Copyright 2007 SBS Technologies GmbH & Co. KG
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* And: mpc8641_hpcn.dts (MPC8641 HPCN Device Tree Source)
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* Copyright 2006 Freescale Semiconductor Inc.
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*/
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/*
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* Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
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*/
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/dts-v1/;
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/ {
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model = "GEF_SBC310";
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compatible = "gef,sbc310";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8641@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <32768>; // L1, 32K
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i-cache-size = <32768>; // L1, 32K
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timebase-frequency = <0>; // From uboot
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bus-frequency = <0>; // From uboot
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clock-frequency = <0>; // From uboot
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};
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PowerPC,8641@1 {
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device_type = "cpu";
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reg = <1>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <32768>; // L1, 32K
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i-cache-size = <32768>; // L1, 32K
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timebase-frequency = <0>; // From uboot
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bus-frequency = <0>; // From uboot
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clock-frequency = <0>; // From uboot
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};
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};
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memory {
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device_type = "memory";
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reg = <0x0 0x40000000>; // set by uboot
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};
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localbus@fef05000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,mpc8641-localbus", "simple-bus";
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reg = <0xfef05000 0x1000>;
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interrupts = <19 2>;
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interrupt-parent = <&mpic>;
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ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
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1 0 0xe0000000 0x08000000 // Paged Flash 0
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2 0 0xe8000000 0x08000000 // Paged Flash 1
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3 0 0xfc100000 0x00020000 // NVRAM
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4 0 0xfc000000 0x00010000>; // FPGA
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/* flash@0,0 is a mirror of part of the memory in flash@1,0
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x01000000>;
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bank-width = <2>;
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device-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "firmware";
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reg = <0x00000000 0x01000000>;
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read-only;
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};
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};
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*/
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flash@1,0 {
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compatible = "cfi-flash";
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reg = <1 0 0x8000000>;
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bank-width = <2>;
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device-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "user";
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reg = <0x00000000 0x07800000>;
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};
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partition@7800000 {
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label = "firmware";
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reg = <0x07800000 0x00800000>;
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read-only;
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};
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};
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fpga@4,0 {
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compatible = "gef,fpga-regs";
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reg = <0x4 0x0 0x40>;
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};
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wdt@4,2000 {
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#interrupt-cells = <2>;
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device_type = "watchdog";
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compatible = "gef,fpga-wdt";
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reg = <0x4 0x2000 0x8>;
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interrupts = <0x1a 0x4>;
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interrupt-parent = <&gef_pic>;
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};
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/*
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wdt@4,2010 {
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#interrupt-cells = <2>;
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device_type = "watchdog";
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compatible = "gef,fpga-wdt";
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reg = <0x4 0x2010 0x8>;
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interrupts = <0x1b 0x4>;
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interrupt-parent = <&gef_pic>;
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};
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*/
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gef_pic: pic@4,4000 {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "gef,fpga-pic";
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reg = <0x4 0x4000 0x20>;
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interrupts = <0x8
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0x9>;
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interrupt-parent = <&mpic>;
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};
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gef_gpio: gpio@4,8000 {
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#gpio-cells = <2>;
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compatible = "gef,sbc310-gpio";
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reg = <0x4 0x8000 0x24>;
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gpio-controller;
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};
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};
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soc@fef00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <2>;
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device_type = "soc";
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compatible = "simple-bus";
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ranges = <0x0 0xfef00000 0x00100000>;
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reg = <0xfef00000 0x100000>; // CCSRBAR 1M
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bus-frequency = <33333333>;
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i2c1: i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <0x2b 0x2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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rtc@51 {
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compatible = "epson,rx8581";
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reg = <0x00000051>;
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};
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};
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i2c2: i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <0x2b 0x2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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hwmon@48 {
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compatible = "national,lm92";
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reg = <0x48>;
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};
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hwmon@4c {
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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eti@6b {
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compatible = "dallas,ds1682";
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reg = <0x6b>;
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};
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};
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dma@21300 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
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reg = <0x21300 0x4>;
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ranges = <0x0 0x21100 0x200>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x0 0x80>;
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cell-index = <0>;
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interrupt-parent = <&mpic>;
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interrupts = <20 2>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x80 0x80>;
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cell-index = <1>;
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interrupt-parent = <&mpic>;
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interrupts = <21 2>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x100 0x80>;
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cell-index = <2>;
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interrupt-parent = <&mpic>;
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interrupts = <22 2>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8641-dma-channel",
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"fsl,eloplus-dma-channel";
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reg = <0x180 0x80>;
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cell-index = <3>;
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interrupt-parent = <&mpic>;
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interrupts = <23 2>;
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};
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};
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enet0: ethernet@24000 {
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2009-03-19 21:01:51 +03:00
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#address-cells = <1>;
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#size-cells = <1>;
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2009-01-19 14:33:24 +03:00
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x24000 0x1000>;
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2009-03-19 21:01:51 +03:00
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ranges = <0x0 0x24000 0x1000>;
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2009-01-19 14:33:24 +03:00
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>;
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phy-connection-type = "gmii";
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2009-03-19 21:01:51 +03:00
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mdio@520 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,gianfar-mdio";
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reg = <0x520 0x20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&gef_pic>;
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interrupts = <0x9 0x4>;
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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interrupt-parent = <&gef_pic>;
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interrupts = <0x8 0x4>;
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reg = <3>;
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};
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};
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2009-01-19 14:33:24 +03:00
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};
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enet1: ethernet@26000 {
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device_type = "network";
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model = "eTSEC";
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compatible = "gianfar";
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reg = <0x26000 0x1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <0x1f 0x2 0x20 0x2 0x21 0x2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy2>;
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phy-connection-type = "gmii";
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <0>;
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interrupts = <0x2a 0x2>;
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interrupt-parent = <&mpic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4600 0x100>;
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clock-frequency = <0>;
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interrupts = <0x1c 0x2>;
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interrupt-parent = <&mpic>;
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};
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mpic: pic@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <0x40000 0x40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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};
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global-utilities@e0000 {
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compatible = "fsl,mpc8641-guts";
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reg = <0xe0000 0x1000>;
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fsl,has-rstcr;
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};
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};
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pci0: pcie@fef08000 {
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compatible = "fsl,mpc8641-pcie";
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
#interrupt-cells = <1>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
reg = <0xfef08000 0x1000>;
|
|
|
|
|
bus-range = <0x0 0xff>;
|
|
|
|
|
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x40000000
|
|
|
|
|
0x01000000 0x0 0x00000000 0xfe000000 0x0 0x00400000>;
|
|
|
|
|
clock-frequency = <33333333>;
|
|
|
|
|
interrupt-parent = <&mpic>;
|
|
|
|
|
interrupts = <0x18 0x2>;
|
|
|
|
|
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
|
|
|
|
|
interrupt-map = <
|
|
|
|
|
0x0000 0x0 0x0 0x1 &mpic 0x0 0x2
|
|
|
|
|
0x0000 0x0 0x0 0x2 &mpic 0x1 0x2
|
|
|
|
|
0x0000 0x0 0x0 0x3 &mpic 0x2 0x2
|
|
|
|
|
0x0000 0x0 0x0 0x4 &mpic 0x3 0x2
|
|
|
|
|
>;
|
|
|
|
|
|
|
|
|
|
pcie@0 {
|
|
|
|
|
reg = <0 0 0 0 0>;
|
|
|
|
|
#size-cells = <2>;
|
|
|
|
|
#address-cells = <3>;
|
|
|
|
|
device_type = "pci";
|
|
|
|
|
ranges = <0x02000000 0x0 0x80000000
|
|
|
|
|
0x02000000 0x0 0x80000000
|
|
|
|
|
0x0 0x40000000
|
|
|
|
|
|
|
|
|
|
0x01000000 0x0 0x00000000
|
|
|
|
|
0x01000000 0x0 0x00000000
|
|
|
|
|
0x0 0x00400000>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
