2005-04-17 02:20:36 +04:00
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/types.h>
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#include <asm/byteorder.h>
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) ({ \
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2006-09-28 18:56:43 +04:00
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unsigned int __sh = (ah); \
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unsigned int __sl = (al); \
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asm volatile( \
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" alr %1,%3\n" \
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" brc 12,0f\n" \
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" ahi %0,1\n" \
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"0: alr %0,%2" \
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: "+&d" (__sh), "+d" (__sl) \
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: "d" (bh), "d" (bl) : "cc"); \
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(sh) = __sh; \
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(sl) = __sl; \
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2005-04-17 02:20:36 +04:00
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})
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) ({ \
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2006-09-28 18:56:43 +04:00
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unsigned int __sh = (ah); \
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unsigned int __sl = (al); \
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asm volatile( \
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" slr %1,%3\n" \
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" brc 3,0f\n" \
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" ahi %0,-1\n" \
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"0: slr %0,%2" \
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: "+&d" (__sh), "+d" (__sl) \
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: "d" (bh), "d" (bl) : "cc"); \
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(sh) = __sh; \
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(sl) = __sl; \
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2005-04-17 02:20:36 +04:00
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})
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/* a umul b = a mul b + (a>=2<<31) ? b<<32:0 + (b>=2<<31) ? a<<32:0 */
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#define umul_ppmm(wh, wl, u, v) ({ \
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2006-09-28 18:56:43 +04:00
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unsigned int __wh = u; \
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unsigned int __wl = v; \
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asm volatile( \
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" ltr 1,%0\n" \
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" mr 0,%1\n" \
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" jnm 0f\n" \
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" alr 0,%1\n" \
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"0: ltr %1,%1\n" \
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" jnm 1f\n" \
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" alr 0,%0\n" \
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"1: lr %0,0\n" \
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" lr %1,1\n" \
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: "+d" (__wh), "+d" (__wl) \
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: : "0", "1", "cc"); \
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wh = __wh; \
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wl = __wl; \
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2005-04-17 02:20:36 +04:00
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})
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2007-07-10 13:24:14 +04:00
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#ifdef __s390x__
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#define udiv_qrnnd(q, r, n1, n0, d) \
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do { unsigned long __n; \
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unsigned int __r, __d; \
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__n = ((unsigned long)(n1) << 32) + n0; \
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__d = (d); \
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(q) = __n / __d; \
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(r) = __n % __d; \
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} while (0)
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#else
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2005-04-17 02:20:36 +04:00
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#define udiv_qrnnd(q, r, n1, n0, d) \
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2007-02-05 23:18:31 +03:00
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do { unsigned int __r; \
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2005-04-17 02:20:36 +04:00
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(q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
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(r) = __r; \
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} while (0)
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2007-02-05 23:18:31 +03:00
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extern unsigned long __udiv_qrnnd (unsigned int *, unsigned int,
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unsigned int , unsigned int);
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2007-07-10 13:24:14 +04:00
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#endif
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2005-04-17 02:20:36 +04:00
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#define UDIV_NEEDS_NORMALIZATION 0
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#define abort() return 0
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#define __BYTE_ORDER __BIG_ENDIAN
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