2019-05-27 09:55:01 +03:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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2006-10-04 12:48:57 +04:00
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/* Copyright (C) 2003-2006, Advanced Micro Devices, Inc.
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*/
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#ifndef _GEODE_AES_H_
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#define _GEODE_AES_H_
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2007-10-21 12:21:25 +04:00
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/* driver logic flags */
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2006-10-04 12:48:57 +04:00
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#define AES_MODE_ECB 0
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#define AES_MODE_CBC 1
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#define AES_DIR_DECRYPT 0
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#define AES_DIR_ENCRYPT 1
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2007-05-24 15:23:24 +04:00
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#define AES_FLAGS_HIDDENKEY (1 << 0)
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2006-10-04 12:48:57 +04:00
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2007-10-21 12:21:25 +04:00
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/* Register definitions */
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#define AES_CTRLA_REG 0x0000
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#define AES_CTRL_START 0x01
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#define AES_CTRL_DECRYPT 0x00
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#define AES_CTRL_ENCRYPT 0x02
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#define AES_CTRL_WRKEY 0x04
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#define AES_CTRL_DCA 0x08
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#define AES_CTRL_SCA 0x10
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#define AES_CTRL_CBC 0x20
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#define AES_INTR_REG 0x0008
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#define AES_INTRA_PENDING (1 << 16)
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#define AES_INTRB_PENDING (1 << 17)
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#define AES_INTR_PENDING (AES_INTRA_PENDING | AES_INTRB_PENDING)
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#define AES_INTR_MASK 0x07
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#define AES_SOURCEA_REG 0x0010
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#define AES_DSTA_REG 0x0014
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#define AES_LENA_REG 0x0018
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#define AES_WRITEKEY0_REG 0x0030
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#define AES_WRITEIV0_REG 0x0040
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/* A very large counter that is used to gracefully bail out of an
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* operation in case of trouble
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*/
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#define AES_OP_TIMEOUT 0x50000
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2019-10-11 07:51:32 +03:00
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struct geode_aes_tfm_ctx {
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2014-05-14 13:36:40 +04:00
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u8 key[AES_KEYSIZE_128];
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2007-11-10 14:29:33 +03:00
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union {
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2019-10-11 07:51:32 +03:00
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struct crypto_skcipher *skcipher;
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2007-11-10 14:29:33 +03:00
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struct crypto_cipher *cip;
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} fallback;
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u32 keylen;
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2006-10-04 12:48:57 +04:00
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};
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#endif
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