80 строки
2.2 KiB
Plaintext
80 строки
2.2 KiB
Plaintext
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/*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*
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* Carveout for multimedia usecases
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* It should be the last 48MB of the first 512MB memory part
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* In theory, it should not even exist. That zone should be reserved
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* dynamically during the .reserve callback.
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*/
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/memreserve/ 0x9d000000 0x03000000;
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/include/ "skeleton.dtsi"
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/ {
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compatible = "ti,omap4430", "ti,omap4";
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interrupt-parent = <&gic>;
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aliases {
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};
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/*
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* The soc node represents the soc top level view. It is uses for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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};
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/*
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* XXX: Use a flat representation of the OMAP4 interconnect.
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* The real OMAP interconnect network is quite complex.
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*
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* MPU -+-- MPU_PRIVATE - GIC, L2
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* |
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* +----------------+----------+
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* | | |
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* + +- EMIF - DDR |
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* | | |
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* | + +--------+
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* | | |
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* | +- L4_ABE - AESS, MCBSP, TIMERs...
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* | |
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* +- L3_MAIN --+- L4_CORE - IPs...
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* |
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* +- L4_PER - IPs...
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* |
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* +- L4_CFG -+- L4_WKUP - IPs...
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* | |
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* | +- IPs...
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* +- IPU ----+
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* | |
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* +- DSP ----+
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* | |
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* +- DSS ----+
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*
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* Since that will not bring real advantage to represent that in DT for
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* the moment, just use a fake OCP bus entry to represent the whole bus
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* hierarchy.
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*/
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ocp {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gic: interrupt-controller@48241000 {
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compatible = "arm,cortex-a9-gic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x48241000 0x1000>,
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<0x48240100 0x0100>;
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};
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};
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};
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