2008-10-14 19:30:03 +04:00
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/*
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* Renesas Solutions Highlander FPGA I2C/SMBus support.
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*
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* Supported devices: R0P7780LC0011RL, R0P7785LC0011RL
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*
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* Copyright (C) 2008 Paul Mundt
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* Copyright (C) 2008 Renesas Solutions Corp.
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* Copyright (C) 2008 Atom Create Engineering Co., Ltd.
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License version 2. See the file "COPYING" in the main directory
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* of this archive for more details.
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/i2c.h>
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#include <linux/platform_device.h>
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#include <linux/completion.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 11:04:11 +03:00
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#include <linux/slab.h>
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2008-10-14 19:30:03 +04:00
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#define SMCR 0x00
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#define SMCR_START (1 << 0)
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#define SMCR_IRIC (1 << 1)
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#define SMCR_BBSY (1 << 2)
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#define SMCR_ACKE (1 << 3)
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#define SMCR_RST (1 << 4)
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#define SMCR_IEIC (1 << 6)
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#define SMSMADR 0x02
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#define SMMR 0x04
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#define SMMR_MODE0 (1 << 0)
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#define SMMR_MODE1 (1 << 1)
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#define SMMR_CAP (1 << 3)
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#define SMMR_TMMD (1 << 4)
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#define SMMR_SP (1 << 7)
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#define SMSADR 0x06
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#define SMTRDR 0x46
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struct highlander_i2c_dev {
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struct device *dev;
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void __iomem *base;
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struct i2c_adapter adapter;
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struct completion cmd_complete;
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unsigned long last_read_time;
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int irq;
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u8 *buf;
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size_t buf_len;
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};
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2012-01-13 03:02:20 +04:00
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static bool iic_force_poll, iic_force_normal;
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2008-10-14 19:30:03 +04:00
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static int iic_timeout = 1000, iic_read_delay;
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static inline void highlander_i2c_irq_enable(struct highlander_i2c_dev *dev)
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{
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iowrite16(ioread16(dev->base + SMCR) | SMCR_IEIC, dev->base + SMCR);
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}
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static inline void highlander_i2c_irq_disable(struct highlander_i2c_dev *dev)
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{
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iowrite16(ioread16(dev->base + SMCR) & ~SMCR_IEIC, dev->base + SMCR);
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}
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static inline void highlander_i2c_start(struct highlander_i2c_dev *dev)
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{
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iowrite16(ioread16(dev->base + SMCR) | SMCR_START, dev->base + SMCR);
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}
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static inline void highlander_i2c_done(struct highlander_i2c_dev *dev)
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{
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iowrite16(ioread16(dev->base + SMCR) | SMCR_IRIC, dev->base + SMCR);
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}
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static void highlander_i2c_setup(struct highlander_i2c_dev *dev)
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{
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u16 smmr;
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smmr = ioread16(dev->base + SMMR);
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smmr |= SMMR_TMMD;
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if (iic_force_normal)
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smmr &= ~SMMR_SP;
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else
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smmr |= SMMR_SP;
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iowrite16(smmr, dev->base + SMMR);
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}
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static void smbus_write_data(u8 *src, u16 *dst, int len)
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{
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for (; len > 1; len -= 2) {
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2008-12-11 14:11:21 +03:00
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*dst++ = be16_to_cpup((__be16 *)src);
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2008-10-14 19:30:03 +04:00
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src += 2;
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}
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if (len)
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*dst = *src << 8;
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}
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static void smbus_read_data(u16 *src, u8 *dst, int len)
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{
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for (; len > 1; len -= 2) {
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2008-12-11 14:11:21 +03:00
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*(__be16 *)dst = cpu_to_be16p(src++);
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2008-10-14 19:30:03 +04:00
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dst += 2;
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}
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if (len)
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*dst = *src >> 8;
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}
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static void highlander_i2c_command(struct highlander_i2c_dev *dev,
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u8 command, int len)
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{
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unsigned int i;
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u16 cmd = (command << 8) | command;
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for (i = 0; i < len; i += 2) {
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if (len - i == 1)
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cmd = command << 8;
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iowrite16(cmd, dev->base + SMSADR + i);
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dev_dbg(dev->dev, "command data[%x] 0x%04x\n", i/2, cmd);
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}
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}
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static int highlander_i2c_wait_for_bbsy(struct highlander_i2c_dev *dev)
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{
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unsigned long timeout;
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timeout = jiffies + msecs_to_jiffies(iic_timeout);
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while (ioread16(dev->base + SMCR) & SMCR_BBSY) {
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if (time_after(jiffies, timeout)) {
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dev_warn(dev->dev, "timeout waiting for bus ready\n");
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return -ETIMEDOUT;
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}
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msleep(1);
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}
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return 0;
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}
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static int highlander_i2c_reset(struct highlander_i2c_dev *dev)
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{
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iowrite16(ioread16(dev->base + SMCR) | SMCR_RST, dev->base + SMCR);
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return highlander_i2c_wait_for_bbsy(dev);
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}
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static int highlander_i2c_wait_for_ack(struct highlander_i2c_dev *dev)
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{
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u16 tmp = ioread16(dev->base + SMCR);
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if ((tmp & (SMCR_IRIC | SMCR_ACKE)) == SMCR_ACKE) {
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dev_warn(dev->dev, "ack abnormality\n");
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return highlander_i2c_reset(dev);
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}
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return 0;
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}
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static irqreturn_t highlander_i2c_irq(int irq, void *dev_id)
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{
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struct highlander_i2c_dev *dev = dev_id;
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highlander_i2c_done(dev);
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complete(&dev->cmd_complete);
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return IRQ_HANDLED;
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}
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static void highlander_i2c_poll(struct highlander_i2c_dev *dev)
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{
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unsigned long timeout;
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u16 smcr;
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timeout = jiffies + msecs_to_jiffies(iic_timeout);
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for (;;) {
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smcr = ioread16(dev->base + SMCR);
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/*
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* Don't bother checking ACKE here, this and the reset
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* are handled in highlander_i2c_wait_xfer_done() when
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* waiting for the ACK.
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*/
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if (smcr & SMCR_IRIC)
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return;
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if (time_after(jiffies, timeout))
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break;
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cpu_relax();
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cond_resched();
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}
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dev_err(dev->dev, "polling timed out\n");
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}
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static inline int highlander_i2c_wait_xfer_done(struct highlander_i2c_dev *dev)
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{
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if (dev->irq)
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wait_for_completion_timeout(&dev->cmd_complete,
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msecs_to_jiffies(iic_timeout));
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else
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/* busy looping, the IRQ of champions */
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highlander_i2c_poll(dev);
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return highlander_i2c_wait_for_ack(dev);
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}
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static int highlander_i2c_read(struct highlander_i2c_dev *dev)
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{
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int i, cnt;
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u16 data[16];
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if (highlander_i2c_wait_for_bbsy(dev))
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return -EAGAIN;
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highlander_i2c_start(dev);
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if (highlander_i2c_wait_xfer_done(dev)) {
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dev_err(dev->dev, "Arbitration loss\n");
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return -EAGAIN;
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}
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/*
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* The R0P7780LC0011RL FPGA needs a significant delay between
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2011-06-23 22:39:20 +04:00
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* data read cycles, otherwise the transceiver gets confused and
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2008-10-14 19:30:03 +04:00
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* garbage is returned when the read is subsequently aborted.
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*
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* It is not sufficient to wait for BBSY.
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*
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* While this generally only applies to the older SH7780-based
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* Highlanders, the same issue can be observed on SH7785 ones,
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* albeit less frequently. SH7780-based Highlanders may need
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* this to be as high as 1000 ms.
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*/
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if (iic_read_delay && time_before(jiffies, dev->last_read_time +
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msecs_to_jiffies(iic_read_delay)))
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msleep(jiffies_to_msecs((dev->last_read_time +
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msecs_to_jiffies(iic_read_delay)) - jiffies));
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cnt = (dev->buf_len + 1) >> 1;
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for (i = 0; i < cnt; i++) {
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data[i] = ioread16(dev->base + SMTRDR + (i * sizeof(u16)));
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dev_dbg(dev->dev, "read data[%x] 0x%04x\n", i, data[i]);
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}
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smbus_read_data(data, dev->buf, dev->buf_len);
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dev->last_read_time = jiffies;
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return 0;
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}
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static int highlander_i2c_write(struct highlander_i2c_dev *dev)
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{
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int i, cnt;
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u16 data[16];
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smbus_write_data(dev->buf, data, dev->buf_len);
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cnt = (dev->buf_len + 1) >> 1;
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for (i = 0; i < cnt; i++) {
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iowrite16(data[i], dev->base + SMTRDR + (i * sizeof(u16)));
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dev_dbg(dev->dev, "write data[%x] 0x%04x\n", i, data[i]);
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}
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if (highlander_i2c_wait_for_bbsy(dev))
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return -EAGAIN;
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highlander_i2c_start(dev);
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return highlander_i2c_wait_xfer_done(dev);
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}
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static int highlander_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr,
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unsigned short flags, char read_write,
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u8 command, int size,
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union i2c_smbus_data *data)
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{
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struct highlander_i2c_dev *dev = i2c_get_adapdata(adap);
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u16 tmp;
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init_completion(&dev->cmd_complete);
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dev_dbg(dev->dev, "addr %04x, command %02x, read_write %d, size %d\n",
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addr, command, read_write, size);
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/*
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* Set up the buffer and transfer size
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*/
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switch (size) {
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case I2C_SMBUS_BYTE_DATA:
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dev->buf = &data->byte;
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dev->buf_len = 1;
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break;
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case I2C_SMBUS_I2C_BLOCK_DATA:
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dev->buf = &data->block[1];
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dev->buf_len = data->block[0];
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break;
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default:
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dev_err(dev->dev, "unsupported command %d\n", size);
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return -EINVAL;
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}
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/*
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* Encode the mode setting
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*/
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tmp = ioread16(dev->base + SMMR);
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tmp &= ~(SMMR_MODE0 | SMMR_MODE1);
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switch (dev->buf_len) {
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case 1:
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|
|
/* default */
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
tmp |= SMMR_MODE0;
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
tmp |= SMMR_MODE1;
|
|
|
|
break;
|
|
|
|
case 32:
|
|
|
|
tmp |= (SMMR_MODE0 | SMMR_MODE1);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
dev_err(dev->dev, "unsupported xfer size %d\n", dev->buf_len);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
iowrite16(tmp, dev->base + SMMR);
|
|
|
|
|
|
|
|
/* Ensure we're in a sane state */
|
|
|
|
highlander_i2c_done(dev);
|
|
|
|
|
|
|
|
/* Set slave address */
|
2010-02-02 15:03:31 +03:00
|
|
|
iowrite16((addr << 1) | read_write, dev->base + SMSMADR);
|
2008-10-14 19:30:03 +04:00
|
|
|
|
|
|
|
highlander_i2c_command(dev, command, dev->buf_len);
|
|
|
|
|
2010-02-02 15:03:31 +03:00
|
|
|
if (read_write == I2C_SMBUS_READ)
|
2008-10-14 19:30:03 +04:00
|
|
|
return highlander_i2c_read(dev);
|
|
|
|
else
|
|
|
|
return highlander_i2c_write(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32 highlander_i2c_func(struct i2c_adapter *adapter)
|
|
|
|
{
|
|
|
|
return I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct i2c_algorithm highlander_i2c_algo = {
|
|
|
|
.smbus_xfer = highlander_i2c_smbus_xfer,
|
|
|
|
.functionality = highlander_i2c_func,
|
|
|
|
};
|
|
|
|
|
2012-11-28 00:59:38 +04:00
|
|
|
static int highlander_i2c_probe(struct platform_device *pdev)
|
2008-10-14 19:30:03 +04:00
|
|
|
{
|
|
|
|
struct highlander_i2c_dev *dev;
|
|
|
|
struct i2c_adapter *adap;
|
|
|
|
struct resource *res;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (unlikely(!res)) {
|
|
|
|
dev_err(&pdev->dev, "no mem resource\n");
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev = kzalloc(sizeof(struct highlander_i2c_dev), GFP_KERNEL);
|
|
|
|
if (unlikely(!dev))
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2009-06-14 02:20:36 +04:00
|
|
|
dev->base = ioremap_nocache(res->start, resource_size(res));
|
2008-10-14 19:30:03 +04:00
|
|
|
if (unlikely(!dev->base)) {
|
|
|
|
ret = -ENXIO;
|
|
|
|
goto err;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->dev = &pdev->dev;
|
|
|
|
platform_set_drvdata(pdev, dev);
|
|
|
|
|
|
|
|
dev->irq = platform_get_irq(pdev, 0);
|
|
|
|
if (iic_force_poll)
|
|
|
|
dev->irq = 0;
|
|
|
|
|
|
|
|
if (dev->irq) {
|
2011-09-21 13:28:33 +04:00
|
|
|
ret = request_irq(dev->irq, highlander_i2c_irq, 0,
|
2008-10-14 19:30:03 +04:00
|
|
|
pdev->name, dev);
|
|
|
|
if (unlikely(ret))
|
|
|
|
goto err_unmap;
|
|
|
|
|
|
|
|
highlander_i2c_irq_enable(dev);
|
|
|
|
} else {
|
|
|
|
dev_notice(&pdev->dev, "no IRQ, using polling mode\n");
|
|
|
|
highlander_i2c_irq_disable(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->last_read_time = jiffies; /* initial read jiffies */
|
|
|
|
|
|
|
|
highlander_i2c_setup(dev);
|
|
|
|
|
|
|
|
adap = &dev->adapter;
|
|
|
|
i2c_set_adapdata(adap, dev);
|
|
|
|
adap->owner = THIS_MODULE;
|
|
|
|
adap->class = I2C_CLASS_HWMON;
|
|
|
|
strlcpy(adap->name, "HL FPGA I2C adapter", sizeof(adap->name));
|
|
|
|
adap->algo = &highlander_i2c_algo;
|
|
|
|
adap->dev.parent = &pdev->dev;
|
|
|
|
adap->nr = pdev->id;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Reset the adapter
|
|
|
|
*/
|
|
|
|
ret = highlander_i2c_reset(dev);
|
|
|
|
if (unlikely(ret)) {
|
|
|
|
dev_err(&pdev->dev, "controller didn't come up\n");
|
|
|
|
goto err_free_irq;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = i2c_add_numbered_adapter(adap);
|
|
|
|
if (unlikely(ret)) {
|
|
|
|
dev_err(&pdev->dev, "failure adding adapter\n");
|
|
|
|
goto err_free_irq;
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_free_irq:
|
|
|
|
if (dev->irq)
|
|
|
|
free_irq(dev->irq, dev);
|
|
|
|
err_unmap:
|
|
|
|
iounmap(dev->base);
|
|
|
|
err:
|
|
|
|
kfree(dev);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2012-11-28 00:59:38 +04:00
|
|
|
static int highlander_i2c_remove(struct platform_device *pdev)
|
2008-10-14 19:30:03 +04:00
|
|
|
{
|
|
|
|
struct highlander_i2c_dev *dev = platform_get_drvdata(pdev);
|
|
|
|
|
|
|
|
i2c_del_adapter(&dev->adapter);
|
|
|
|
|
|
|
|
if (dev->irq)
|
|
|
|
free_irq(dev->irq, dev);
|
|
|
|
|
|
|
|
iounmap(dev->base);
|
|
|
|
kfree(dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct platform_driver highlander_i2c_driver = {
|
|
|
|
.driver = {
|
|
|
|
.name = "i2c-highlander",
|
|
|
|
},
|
|
|
|
|
|
|
|
.probe = highlander_i2c_probe,
|
2012-11-28 00:59:38 +04:00
|
|
|
.remove = highlander_i2c_remove,
|
2008-10-14 19:30:03 +04:00
|
|
|
};
|
|
|
|
|
2012-01-12 23:32:04 +04:00
|
|
|
module_platform_driver(highlander_i2c_driver);
|
2008-10-14 19:30:03 +04:00
|
|
|
|
|
|
|
MODULE_AUTHOR("Paul Mundt");
|
|
|
|
MODULE_DESCRIPTION("Renesas Highlander FPGA I2C/SMBus adapter");
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
|
|
|
|
module_param(iic_force_poll, bool, 0);
|
|
|
|
module_param(iic_force_normal, bool, 0);
|
|
|
|
module_param(iic_timeout, int, 0);
|
|
|
|
module_param(iic_read_delay, int, 0);
|
|
|
|
|
|
|
|
MODULE_PARM_DESC(iic_force_poll, "Force polling mode");
|
|
|
|
MODULE_PARM_DESC(iic_force_normal,
|
|
|
|
"Force normal mode (100 kHz), default is fast mode (400 kHz)");
|
|
|
|
MODULE_PARM_DESC(iic_timeout, "Set timeout value in msecs (default 1000 ms)");
|
|
|
|
MODULE_PARM_DESC(iic_read_delay,
|
|
|
|
"Delay between data read cycles (default 0 ms)");
|