clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
/*
|
|
|
|
* Copyright (C) 2013 Broadcom Corporation
|
|
|
|
* Copyright 2013 Linaro Limited
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU General Public License as
|
|
|
|
* published by the Free Software Foundation version 2.
|
|
|
|
*
|
|
|
|
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
|
|
|
* kind, whether express or implied; without even the implied warranty
|
|
|
|
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include "clk-kona.h"
|
|
|
|
#include "dt-bindings/clock/bcm281xx.h"
|
|
|
|
|
2014-04-22 01:11:40 +04:00
|
|
|
#define BCM281XX_CCU_COMMON(_name, _ucase_name) \
|
|
|
|
KONA_CCU_COMMON(BCM281XX, _name, _ucase_name)
|
|
|
|
|
|
|
|
/* Root CCU */
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
|
|
|
|
static struct peri_clk_data frac_1m_data = {
|
|
|
|
.gate = HW_SW_GATE(0x214, 16, 0, 1),
|
|
|
|
.trig = TRIGGER(0x0e04, 0),
|
|
|
|
.div = FRAC_DIVIDER(0x0e00, 0, 22, 16),
|
|
|
|
.clocks = CLOCKS("ref_crystal"),
|
|
|
|
};
|
|
|
|
|
2014-04-22 01:11:40 +04:00
|
|
|
static struct ccu_data root_ccu_data = {
|
|
|
|
BCM281XX_CCU_COMMON(root, ROOT),
|
2014-04-22 01:11:41 +04:00
|
|
|
.kona_clks = {
|
|
|
|
[BCM281XX_ROOT_CCU_FRAC_1M] =
|
|
|
|
KONA_CLK(root, frac_1m, peri),
|
|
|
|
[BCM281XX_ROOT_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
|
|
|
|
},
|
2014-04-22 01:11:40 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
/* AON CCU */
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
|
|
|
|
static struct peri_clk_data hub_timer_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0414, 16, 0, 1),
|
|
|
|
.clocks = CLOCKS("bbl_32k",
|
|
|
|
"frac_1m",
|
|
|
|
"dft_19_5m"),
|
|
|
|
.sel = SELECTOR(0x0a10, 0, 2),
|
|
|
|
.trig = TRIGGER(0x0a40, 4),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data pmu_bsc_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0418, 16, 0, 1),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"pmu_bsc_var",
|
|
|
|
"bbl_32k"),
|
|
|
|
.sel = SELECTOR(0x0a04, 0, 2),
|
|
|
|
.div = DIVIDER(0x0a04, 3, 4),
|
|
|
|
.trig = TRIGGER(0x0a40, 0),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data pmu_bsc_var_data = {
|
|
|
|
.clocks = CLOCKS("var_312m",
|
|
|
|
"ref_312m"),
|
|
|
|
.sel = SELECTOR(0x0a00, 0, 2),
|
|
|
|
.div = DIVIDER(0x0a00, 4, 5),
|
|
|
|
.trig = TRIGGER(0x0a40, 2),
|
|
|
|
};
|
|
|
|
|
2014-04-22 01:11:40 +04:00
|
|
|
static struct ccu_data aon_ccu_data = {
|
|
|
|
BCM281XX_CCU_COMMON(aon, AON),
|
2014-04-22 01:11:41 +04:00
|
|
|
.kona_clks = {
|
|
|
|
[BCM281XX_AON_CCU_HUB_TIMER] =
|
|
|
|
KONA_CLK(aon, hub_timer, peri),
|
|
|
|
[BCM281XX_AON_CCU_PMU_BSC] =
|
|
|
|
KONA_CLK(aon, pmu_bsc, peri),
|
|
|
|
[BCM281XX_AON_CCU_PMU_BSC_VAR] =
|
|
|
|
KONA_CLK(aon, pmu_bsc_var, peri),
|
|
|
|
[BCM281XX_AON_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
|
|
|
|
},
|
2014-04-22 01:11:40 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
/* Hub CCU */
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
|
|
|
|
static struct peri_clk_data tmon_1m_data = {
|
|
|
|
.gate = HW_SW_GATE(0x04a4, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"frac_1m"),
|
|
|
|
.sel = SELECTOR(0x0e74, 0, 2),
|
|
|
|
.trig = TRIGGER(0x0e84, 1),
|
|
|
|
};
|
|
|
|
|
2014-04-22 01:11:40 +04:00
|
|
|
static struct ccu_data hub_ccu_data = {
|
|
|
|
BCM281XX_CCU_COMMON(hub, HUB),
|
2014-04-22 01:11:41 +04:00
|
|
|
.kona_clks = {
|
|
|
|
[BCM281XX_HUB_CCU_TMON_1M] =
|
|
|
|
KONA_CLK(hub, tmon_1m, peri),
|
|
|
|
[BCM281XX_HUB_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
|
|
|
|
},
|
2014-04-22 01:11:40 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
/* Master CCU */
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
|
|
|
|
static struct peri_clk_data sdio1_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0358, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_52m",
|
|
|
|
"ref_52m",
|
|
|
|
"var_96m",
|
|
|
|
"ref_96m"),
|
|
|
|
.sel = SELECTOR(0x0a28, 0, 3),
|
|
|
|
.div = DIVIDER(0x0a28, 4, 14),
|
|
|
|
.trig = TRIGGER(0x0afc, 9),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data sdio2_data = {
|
|
|
|
.gate = HW_SW_GATE(0x035c, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_52m",
|
|
|
|
"ref_52m",
|
|
|
|
"var_96m",
|
|
|
|
"ref_96m"),
|
|
|
|
.sel = SELECTOR(0x0a2c, 0, 3),
|
|
|
|
.div = DIVIDER(0x0a2c, 4, 14),
|
|
|
|
.trig = TRIGGER(0x0afc, 10),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data sdio3_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0364, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_52m",
|
|
|
|
"ref_52m",
|
|
|
|
"var_96m",
|
|
|
|
"ref_96m"),
|
|
|
|
.sel = SELECTOR(0x0a34, 0, 3),
|
|
|
|
.div = DIVIDER(0x0a34, 4, 14),
|
|
|
|
.trig = TRIGGER(0x0afc, 12),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data sdio4_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0360, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_52m",
|
|
|
|
"ref_52m",
|
|
|
|
"var_96m",
|
|
|
|
"ref_96m"),
|
|
|
|
.sel = SELECTOR(0x0a30, 0, 3),
|
|
|
|
.div = DIVIDER(0x0a30, 4, 14),
|
|
|
|
.trig = TRIGGER(0x0afc, 11),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data usb_ic_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0354, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_96m",
|
|
|
|
"ref_96m"),
|
|
|
|
.div = FIXED_DIVIDER(2),
|
|
|
|
.sel = SELECTOR(0x0a24, 0, 2),
|
|
|
|
.trig = TRIGGER(0x0afc, 7),
|
|
|
|
};
|
|
|
|
|
|
|
|
/* also called usbh_48m */
|
|
|
|
static struct peri_clk_data hsic2_48m_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0370, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_96m",
|
|
|
|
"ref_96m"),
|
|
|
|
.sel = SELECTOR(0x0a38, 0, 2),
|
|
|
|
.div = FIXED_DIVIDER(2),
|
|
|
|
.trig = TRIGGER(0x0afc, 5),
|
|
|
|
};
|
|
|
|
|
|
|
|
/* also called usbh_12m */
|
|
|
|
static struct peri_clk_data hsic2_12m_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0370, 20, 4, 5),
|
|
|
|
.div = DIVIDER(0x0a38, 12, 2),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_96m",
|
|
|
|
"ref_96m"),
|
|
|
|
.pre_div = FIXED_DIVIDER(2),
|
|
|
|
.sel = SELECTOR(0x0a38, 0, 2),
|
|
|
|
.trig = TRIGGER(0x0afc, 5),
|
|
|
|
};
|
|
|
|
|
2014-04-22 01:11:40 +04:00
|
|
|
static struct ccu_data master_ccu_data = {
|
|
|
|
BCM281XX_CCU_COMMON(master, MASTER),
|
2014-04-22 01:11:41 +04:00
|
|
|
.kona_clks = {
|
|
|
|
[BCM281XX_MASTER_CCU_SDIO1] =
|
|
|
|
KONA_CLK(master, sdio1, peri),
|
|
|
|
[BCM281XX_MASTER_CCU_SDIO2] =
|
|
|
|
KONA_CLK(master, sdio2, peri),
|
|
|
|
[BCM281XX_MASTER_CCU_SDIO3] =
|
|
|
|
KONA_CLK(master, sdio3, peri),
|
|
|
|
[BCM281XX_MASTER_CCU_SDIO4] =
|
|
|
|
KONA_CLK(master, sdio4, peri),
|
|
|
|
[BCM281XX_MASTER_CCU_USB_IC] =
|
|
|
|
KONA_CLK(master, usb_ic, peri),
|
|
|
|
[BCM281XX_MASTER_CCU_HSIC2_48M] =
|
|
|
|
KONA_CLK(master, hsic2_48m, peri),
|
|
|
|
[BCM281XX_MASTER_CCU_HSIC2_12M] =
|
|
|
|
KONA_CLK(master, hsic2_12m, peri),
|
|
|
|
[BCM281XX_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
|
|
|
|
},
|
2014-04-22 01:11:40 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
/* Slave CCU */
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
|
|
|
|
static struct peri_clk_data uartb_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0400, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_156m",
|
|
|
|
"ref_156m"),
|
|
|
|
.sel = SELECTOR(0x0a10, 0, 2),
|
|
|
|
.div = FRAC_DIVIDER(0x0a10, 4, 12, 8),
|
|
|
|
.trig = TRIGGER(0x0afc, 2),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data uartb2_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0404, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_156m",
|
|
|
|
"ref_156m"),
|
|
|
|
.sel = SELECTOR(0x0a14, 0, 2),
|
|
|
|
.div = FRAC_DIVIDER(0x0a14, 4, 12, 8),
|
|
|
|
.trig = TRIGGER(0x0afc, 3),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data uartb3_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0408, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_156m",
|
|
|
|
"ref_156m"),
|
|
|
|
.sel = SELECTOR(0x0a18, 0, 2),
|
|
|
|
.div = FRAC_DIVIDER(0x0a18, 4, 12, 8),
|
|
|
|
.trig = TRIGGER(0x0afc, 4),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data uartb4_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0408, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_156m",
|
|
|
|
"ref_156m"),
|
|
|
|
.sel = SELECTOR(0x0a1c, 0, 2),
|
|
|
|
.div = FRAC_DIVIDER(0x0a1c, 4, 12, 8),
|
|
|
|
.trig = TRIGGER(0x0afc, 5),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data ssp0_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0410, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_104m",
|
|
|
|
"ref_104m",
|
|
|
|
"var_96m",
|
|
|
|
"ref_96m"),
|
|
|
|
.sel = SELECTOR(0x0a20, 0, 3),
|
|
|
|
.div = DIVIDER(0x0a20, 4, 14),
|
|
|
|
.trig = TRIGGER(0x0afc, 6),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data ssp2_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0418, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_104m",
|
|
|
|
"ref_104m",
|
|
|
|
"var_96m",
|
|
|
|
"ref_96m"),
|
|
|
|
.sel = SELECTOR(0x0a28, 0, 3),
|
|
|
|
.div = DIVIDER(0x0a28, 4, 14),
|
|
|
|
.trig = TRIGGER(0x0afc, 8),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data bsc1_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0458, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_104m",
|
|
|
|
"ref_104m",
|
|
|
|
"var_13m",
|
|
|
|
"ref_13m"),
|
|
|
|
.sel = SELECTOR(0x0a64, 0, 3),
|
|
|
|
.trig = TRIGGER(0x0afc, 23),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data bsc2_data = {
|
|
|
|
.gate = HW_SW_GATE(0x045c, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_104m",
|
|
|
|
"ref_104m",
|
|
|
|
"var_13m",
|
|
|
|
"ref_13m"),
|
|
|
|
.sel = SELECTOR(0x0a68, 0, 3),
|
|
|
|
.trig = TRIGGER(0x0afc, 24),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data bsc3_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0484, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_104m",
|
|
|
|
"ref_104m",
|
|
|
|
"var_13m",
|
|
|
|
"ref_13m"),
|
|
|
|
.sel = SELECTOR(0x0a84, 0, 3),
|
|
|
|
.trig = TRIGGER(0x0b00, 2),
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct peri_clk_data pwm_data = {
|
|
|
|
.gate = HW_SW_GATE(0x0468, 18, 2, 3),
|
|
|
|
.clocks = CLOCKS("ref_crystal",
|
|
|
|
"var_104m"),
|
|
|
|
.sel = SELECTOR(0x0a70, 0, 2),
|
|
|
|
.div = DIVIDER(0x0a70, 4, 3),
|
|
|
|
.trig = TRIGGER(0x0afc, 15),
|
|
|
|
};
|
|
|
|
|
2014-04-22 01:11:40 +04:00
|
|
|
static struct ccu_data slave_ccu_data = {
|
|
|
|
BCM281XX_CCU_COMMON(slave, SLAVE),
|
2014-04-22 01:11:41 +04:00
|
|
|
.kona_clks = {
|
|
|
|
[BCM281XX_SLAVE_CCU_UARTB] =
|
|
|
|
KONA_CLK(slave, uartb, peri),
|
|
|
|
[BCM281XX_SLAVE_CCU_UARTB2] =
|
|
|
|
KONA_CLK(slave, uartb2, peri),
|
|
|
|
[BCM281XX_SLAVE_CCU_UARTB3] =
|
|
|
|
KONA_CLK(slave, uartb3, peri),
|
|
|
|
[BCM281XX_SLAVE_CCU_UARTB4] =
|
|
|
|
KONA_CLK(slave, uartb4, peri),
|
|
|
|
[BCM281XX_SLAVE_CCU_SSP0] =
|
|
|
|
KONA_CLK(slave, ssp0, peri),
|
|
|
|
[BCM281XX_SLAVE_CCU_SSP2] =
|
|
|
|
KONA_CLK(slave, ssp2, peri),
|
|
|
|
[BCM281XX_SLAVE_CCU_BSC1] =
|
|
|
|
KONA_CLK(slave, bsc1, peri),
|
|
|
|
[BCM281XX_SLAVE_CCU_BSC2] =
|
|
|
|
KONA_CLK(slave, bsc2, peri),
|
|
|
|
[BCM281XX_SLAVE_CCU_BSC3] =
|
|
|
|
KONA_CLK(slave, bsc3, peri),
|
|
|
|
[BCM281XX_SLAVE_CCU_PWM] =
|
|
|
|
KONA_CLK(slave, pwm, peri),
|
|
|
|
[BCM281XX_SLAVE_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
|
|
|
|
},
|
2014-04-22 01:11:40 +04:00
|
|
|
};
|
|
|
|
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
/* Device tree match table callback functions */
|
|
|
|
|
|
|
|
static void __init kona_dt_root_ccu_setup(struct device_node *node)
|
|
|
|
{
|
2014-04-22 01:11:41 +04:00
|
|
|
kona_dt_ccu_setup(&root_ccu_data, node);
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __init kona_dt_aon_ccu_setup(struct device_node *node)
|
|
|
|
{
|
2014-04-22 01:11:41 +04:00
|
|
|
kona_dt_ccu_setup(&aon_ccu_data, node);
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __init kona_dt_hub_ccu_setup(struct device_node *node)
|
|
|
|
{
|
2014-04-22 01:11:41 +04:00
|
|
|
kona_dt_ccu_setup(&hub_ccu_data, node);
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __init kona_dt_master_ccu_setup(struct device_node *node)
|
|
|
|
{
|
2014-04-22 01:11:41 +04:00
|
|
|
kona_dt_ccu_setup(&master_ccu_data, node);
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void __init kona_dt_slave_ccu_setup(struct device_node *node)
|
|
|
|
{
|
2014-04-22 01:11:41 +04:00
|
|
|
kona_dt_ccu_setup(&slave_ccu_data, node);
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
}
|
|
|
|
|
2014-04-22 01:11:39 +04:00
|
|
|
CLK_OF_DECLARE(bcm281xx_root_ccu, BCM281XX_DT_ROOT_CCU_COMPAT,
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
kona_dt_root_ccu_setup);
|
2014-04-22 01:11:39 +04:00
|
|
|
CLK_OF_DECLARE(bcm281xx_aon_ccu, BCM281XX_DT_AON_CCU_COMPAT,
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
kona_dt_aon_ccu_setup);
|
2014-04-22 01:11:39 +04:00
|
|
|
CLK_OF_DECLARE(bcm281xx_hub_ccu, BCM281XX_DT_HUB_CCU_COMPAT,
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
kona_dt_hub_ccu_setup);
|
2014-04-22 01:11:39 +04:00
|
|
|
CLK_OF_DECLARE(bcm281xx_master_ccu, BCM281XX_DT_MASTER_CCU_COMPAT,
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
kona_dt_master_ccu_setup);
|
2014-04-22 01:11:39 +04:00
|
|
|
CLK_OF_DECLARE(bcm281xx_slave_ccu, BCM281XX_DT_SLAVE_CCU_COMPAT,
|
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of
SoCs. Machines in this family use peripheral clocks implemented by
"Kona" clock control units (CCUs). (Other Broadcom SoC families use
Kona style CCUs as well, but support for them is not yet upstream.)
A BCM281xx SoC has multiple CCUs, each of which manages a set of
clocks on the SoC. A Kona peripheral clock is composite clock that
may include a gate, a parent clock multiplexor, and zero, one
or two dividers. There is a variety of gate types, and many gates
implement hardware-managed gating (often called "auto-gating").
Most dividers divide their input clock signal by an integer value
(one or more). There are also "fractional" dividers which allow
division by non-integer values. To accomodate such dividers,
clock rates and dividers are generally maintained by the code in
"scaled" form, which allows integer and fractional dividers to
be handled in a uniform way.
If present, the gate for a Kona peripheral clock must be enabled
when a change is made to its multiplexor or one of its dividers.
Additionally, dividers and multiplexors have trigger registers which
must be used whenever the divider value or selected parent clock is
changed. The same trigger is often used for a divider and
multiplexor, and a BCM281xx peripheral clock occasionally has two
triggers.
The gate, dividers, and parent clock selector are treated in this
code as "components" of a peripheral clock. Their functionality is
implemented directly--e.g. the common clock framework gate
implementation is not used for a Kona peripheral clock gate. (This
has being considered though, and the intention is to evolve this
code to leverage common code as much as possible.)
The source code is divided into three general portions:
drivers/clk/bcm/clk-kona.h
drivers/clk/bcm/clk-kona.c
These implement the basic Kona clock functionality,
including the clk_ops methods and various routines to
manipulate registers and interpret their values. This
includes some functions used to set clocks to a desired
initial state (though this feature is only partially
implemented here).
drivers/clk/bcm/clk-kona-setup.c
This contains generic run-time initialization code for
data structures representing Kona CCUs and clocks. This
encapsulates the clock structure initialization that can't
be done statically. Note that there is a great deal of
validity-checking code here, making explicit certain
assumptions in the code. This is mostly useful for adding
new clock definitions and could possibly be disabled for
production use.
drivers/clk/bcm/clk-bcm281xx.c
This file defines the specific CCUs used by BCM281XX family
SoCs, as well as the specific clocks implemented by each.
It declares a device tree clock match entry for each CCU
defined.
include/dt-bindings/clock/bcm281xx.h
This file defines the selector (index) values used to
identify a particular clock provided by a CCU. It consists
entirely of C preprocessor constants, to be used by both the
C source and device tree source files.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Matt Porter <mporter@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Matt Porter <mporter@linaro.org>
2014-02-14 22:29:18 +04:00
|
|
|
kona_dt_slave_ccu_setup);
|