2005-11-19 12:17:32 +03:00
|
|
|
#ifndef _ASM_POWERPC_MMU_H_
|
|
|
|
#define _ASM_POWERPC_MMU_H_
|
2005-12-17 00:43:46 +03:00
|
|
|
#ifdef __KERNEL__
|
2005-11-19 12:17:32 +03:00
|
|
|
|
2008-12-18 22:13:32 +03:00
|
|
|
#include <asm/asm-compat.h>
|
|
|
|
#include <asm/feature-fixups.h>
|
|
|
|
|
|
|
|
/*
|
|
|
|
* MMU features bit definitions
|
|
|
|
*/
|
|
|
|
|
|
|
|
/*
|
|
|
|
* First half is MMU families
|
|
|
|
*/
|
|
|
|
#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
|
|
|
|
#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
|
|
|
|
#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
|
|
|
|
#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
|
|
|
|
#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This is individual features
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* Enable use of high BAT registers */
|
|
|
|
#define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
|
|
|
|
|
|
|
|
/* Enable >32-bit physical addresses on 32-bit processor, only used
|
|
|
|
* by CONFIG_6xx currently as BookE supports that from day 1
|
|
|
|
*/
|
|
|
|
#define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
|
|
|
|
|
2008-12-18 22:13:38 +03:00
|
|
|
/* Enable use of broadcast TLB invalidations. We don't always set it
|
|
|
|
* on processors that support it due to other constraints with the
|
|
|
|
* use of such invalidations
|
|
|
|
*/
|
|
|
|
#define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
|
|
|
|
|
|
|
|
/* Enable use of tlbilx invalidate-by-PID variant.
|
|
|
|
*/
|
|
|
|
#define MMU_FTR_USE_TLBILX_PID ASM_CONST(0x00080000)
|
|
|
|
|
|
|
|
/* This indicates that the processor cannot handle multiple outstanding
|
|
|
|
* broadcast tlbivax or tlbsync. This makes the code use a spinlock
|
|
|
|
* around such invalidate forms.
|
|
|
|
*/
|
|
|
|
#define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
|
|
|
|
|
2008-12-18 22:13:32 +03:00
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#include <asm/cputable.h>
|
|
|
|
|
|
|
|
static inline int mmu_has_feature(unsigned long feature)
|
|
|
|
{
|
|
|
|
return (cur_cpu_spec->mmu_features & feature);
|
|
|
|
}
|
|
|
|
|
|
|
|
extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
|
|
|
|
|
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
|
|
|
|
|
|
|
2007-04-27 05:53:52 +04:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
/* 64-bit classic hash table MMU */
|
|
|
|
# include <asm/mmu-hash64.h>
|
2007-06-13 08:52:54 +04:00
|
|
|
#elif defined(CONFIG_PPC_STD_MMU)
|
|
|
|
/* 32-bit classic hash table MMU */
|
|
|
|
# include <asm/mmu-hash32.h>
|
2007-08-20 16:28:48 +04:00
|
|
|
#elif defined(CONFIG_40x)
|
|
|
|
/* 40x-style software loaded TLB */
|
|
|
|
# include <asm/mmu-40x.h>
|
2007-04-30 08:06:25 +04:00
|
|
|
#elif defined(CONFIG_44x)
|
|
|
|
/* 44x-style software loaded TLB */
|
|
|
|
# include <asm/mmu-44x.h>
|
2007-06-15 09:33:09 +04:00
|
|
|
#elif defined(CONFIG_FSL_BOOKE)
|
|
|
|
/* Freescale Book-E software loaded TLB */
|
|
|
|
# include <asm/mmu-fsl-booke.h>
|
2007-06-22 08:58:55 +04:00
|
|
|
#elif defined (CONFIG_PPC_8xx)
|
|
|
|
/* Motorola/Freescale 8xx software loaded TLB */
|
|
|
|
# include <asm/mmu-8xx.h>
|
2005-05-06 03:15:13 +04:00
|
|
|
#endif
|
|
|
|
|
2005-12-17 00:43:46 +03:00
|
|
|
#endif /* __KERNEL__ */
|
2005-11-19 12:17:32 +03:00
|
|
|
#endif /* _ASM_POWERPC_MMU_H_ */
|