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WSL2-Linux-Kernel
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WSL2-Linux-Kernel/drivers/sh/Kconfig

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sh: intc: userimask support. This adds support for hardware-assisted userspace irq masking for special priority levels. Due to the SR.IMASK interactivity, only some platforms implement this in hardware (including but not limited to SH-4A interrupt controllers, and ARM-based SH-Mobile CPUs). Each CPU needs to wire this up on its own, for now only SH7786 is wired up as an example. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-04-13 09:43:03 +04:00
config INTC_USERIMASK
bool "Userspace interrupt masking support"
depends on ARCH_SHMOBILE || (SUPERH && CPU_SH4A)
help
This enables support for hardware-assisted userspace hardirq
masking.
SH-4A and newer interrupt blocks all support a special shadowed
page with all non-masking registers obscured when mapped in to
userspace. This is primarily for use by userspace device
drivers that are using special priority levels.
If in doubt, say N.
sh: intc: IRQ auto-distribution support. This implements support for hardware-managed IRQ balancing as implemented by SH-X3 cores (presently only hooked up for SH7786, but can probably be carried over to other SH-X3 cores, too). CPUs need to specify their distribution register along with the mask definitions, as these follow the same format. Peripheral IRQs that don't opt out of balancing will be automatically distributed at the whim of the hardware block, while each CPU needs to verify whether it is handling the IRQ or not, especially before clearing the mask. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-04-15 08:13:52 +04:00
config INTC_BALANCING
bool "Hardware IRQ balancing support"
sh: Support IRQ balancing for SH-X3 proto cores, too. This adds in hardware IRQ auto-distribution support for SH-X3 proto CPUs, following the SH7786 support. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-10-01 20:04:30 +04:00
depends on SMP && SUPERH && CPU_SHX3
sh: intc: IRQ auto-distribution support. This implements support for hardware-managed IRQ balancing as implemented by SH-X3 cores (presently only hooked up for SH7786, but can probably be carried over to other SH-X3 cores, too). CPUs need to specify their distribution register along with the mask definitions, as these follow the same format. Peripheral IRQs that don't opt out of balancing will be automatically distributed at the whim of the hardware block, while each CPU needs to verify whether it is handling the IRQ or not, especially before clearing the mask. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-04-15 08:13:52 +04:00
help
This enables support for IRQ auto-distribution mode on SH-X3
SMP parts. All of the balancing and CPU wakeup decisions are
taken care of automatically by hardware for distributed
vectors.
If in doubt, say N.
sh: intc: Implement reverse mapping for IRQs to per-controller IDs. This implements a scheme roughly analogous to the PowerPC virtual to hardware IRQ mapping, which we use for IRQ to per-controller ID mapping. This makes it possible for drivers to use the IDs directly for lookup instead of hardcoding the vector. The main motivation for this work is as a building block for dynamically allocating virtual IRQs for demuxing INTC events sharing a single INTEVT in addition to a common masking source. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2010-09-23 15:09:38 +04:00
config INTC_MAPPING_DEBUG
bool "Expose IRQ to per-controller id mapping via debugfs"
depends on DEBUG_FS
help
This will create a debugfs entry for showing the relationship
between system IRQs and the per-controller id tables.
If in doubt, say N.