2019-06-04 11:11:33 +03:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2017-04-05 10:54:56 +03:00
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/*
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* Copyright 2017 Benjamin Herrenschmidt, IBM Corporation
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*/
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#ifndef _KVM_PPC_BOOK3S_XIVE_H
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#define _KVM_PPC_BOOK3S_XIVE_H
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#ifdef CONFIG_KVM_XICS
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#include "book3s_xics.h"
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2019-04-18 13:39:29 +03:00
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/*
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* The XIVE Interrupt source numbers are within the range 0 to
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* KVMPPC_XICS_NR_IRQS.
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*/
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#define KVMPPC_XIVE_FIRST_IRQ 0
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#define KVMPPC_XIVE_NR_IRQS KVMPPC_XICS_NR_IRQS
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2017-04-05 10:54:56 +03:00
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/*
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* State for one guest irq source.
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*
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* For each guest source we allocate a HW interrupt in the XIVE
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* which we use for all SW triggers. It will be unused for
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* pass-through but it's easier to keep around as the same
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* guest interrupt can alternatively be emulated or pass-through
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* if a physical device is hot unplugged and replaced with an
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* emulated one.
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*
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* This state structure is very similar to the XICS one with
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* additional XIVE specific tracking.
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*/
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struct kvmppc_xive_irq_state {
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bool valid; /* Interrupt entry is valid */
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u32 number; /* Guest IRQ number */
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u32 ipi_number; /* XIVE IPI HW number */
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struct xive_irq_data ipi_data; /* XIVE IPI associated data */
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u32 pt_number; /* XIVE Pass-through number if any */
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struct xive_irq_data *pt_data; /* XIVE Pass-through associated data */
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/* Targetting as set by guest */
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u8 guest_priority; /* Guest set priority */
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u8 saved_priority; /* Saved priority when masking */
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/* Actual targetting */
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u32 act_server; /* Actual server */
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u8 act_priority; /* Actual priority */
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/* Various state bits */
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bool in_eoi; /* Synchronize with H_EOI */
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bool old_p; /* P bit state when masking */
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bool old_q; /* Q bit state when masking */
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bool lsi; /* level-sensitive interrupt */
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bool asserted; /* Only for emulated LSI: current state */
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/* Saved for migration state */
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bool in_queue;
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bool saved_p;
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bool saved_q;
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u8 saved_scan_prio;
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2019-04-18 13:39:30 +03:00
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/* Xive native */
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u32 eisn; /* Guest Effective IRQ number */
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2017-04-05 10:54:56 +03:00
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};
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/* Select the "right" interrupt (IPI vs. passthrough) */
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static inline void kvmppc_xive_select_irq(struct kvmppc_xive_irq_state *state,
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u32 *out_hw_irq,
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struct xive_irq_data **out_xd)
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{
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if (state->pt_number) {
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if (out_hw_irq)
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*out_hw_irq = state->pt_number;
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if (out_xd)
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*out_xd = state->pt_data;
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} else {
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if (out_hw_irq)
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*out_hw_irq = state->ipi_number;
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if (out_xd)
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*out_xd = &state->ipi_data;
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}
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}
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/*
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* This corresponds to an "ICS" in XICS terminology, we use it
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* as a mean to break up source information into multiple structures.
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*/
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struct kvmppc_xive_src_block {
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arch_spinlock_t lock;
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u16 id;
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struct kvmppc_xive_irq_state irq_state[KVMPPC_XICS_IRQ_PER_ICS];
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};
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KVM: PPC: Book3S HV: XIVE: Add passthrough support
The KVM XICS-over-XIVE device and the proposed KVM XIVE native device
implement an IRQ space for the guest using the generic IPI interrupts
of the XIVE IC controller. These interrupts are allocated at the OPAL
level and "mapped" into the guest IRQ number space in the range 0-0x1FFF.
Interrupt management is performed in the XIVE way: using loads and
stores on the addresses of the XIVE IPI interrupt ESB pages.
Both KVM devices share the same internal structure caching information
on the interrupts, among which the xive_irq_data struct containing the
addresses of the IPI ESB pages and an extra one in case of pass-through.
The later contains the addresses of the ESB pages of the underlying HW
controller interrupts, PHB4 in all cases for now.
A guest, when running in the XICS legacy interrupt mode, lets the KVM
XICS-over-XIVE device "handle" interrupt management, that is to
perform the loads and stores on the addresses of the ESB pages of the
guest interrupts. However, when running in XIVE native exploitation
mode, the KVM XIVE native device exposes the interrupt ESB pages to
the guest and lets the guest perform directly the loads and stores.
The VMA exposing the ESB pages make use of a custom VM fault handler
which role is to populate the VMA with appropriate pages. When a fault
occurs, the guest IRQ number is deduced from the offset, and the ESB
pages of associated XIVE IPI interrupt are inserted in the VMA (using
the internal structure caching information on the interrupts).
Supporting device passthrough in the guest running in XIVE native
exploitation mode adds some extra refinements because the ESB pages
of a different HW controller (PHB4) need to be exposed to the guest
along with the initial IPI ESB pages of the XIVE IC controller. But
the overall mechanic is the same.
When the device HW irqs are mapped into or unmapped from the guest
IRQ number space, the passthru_irq helpers, kvmppc_xive_set_mapped()
and kvmppc_xive_clr_mapped(), are called to record or clear the
passthrough interrupt information and to perform the switch.
The approach taken by this patch is to clear the ESB pages of the
guest IRQ number being mapped and let the VM fault handler repopulate.
The handler will insert the ESB page corresponding to the HW interrupt
of the device being passed-through or the initial IPI ESB page if the
device is being removed.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2019-04-18 13:39:39 +03:00
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struct kvmppc_xive;
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struct kvmppc_xive_ops {
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int (*reset_mapped)(struct kvm *kvm, unsigned long guest_irq);
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};
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2017-04-05 10:54:56 +03:00
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struct kvmppc_xive {
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struct kvm *kvm;
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struct kvm_device *dev;
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struct dentry *dentry;
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/* VP block associated with the VM */
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u32 vp_base;
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/* Blocks of sources */
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struct kvmppc_xive_src_block *src_blocks[KVMPPC_XICS_MAX_ICS_ID + 1];
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u32 max_sbid;
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/*
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* For state save, we lazily scan the queues on the first interrupt
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* being migrated. We don't have a clean way to reset that flags
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* so we keep track of the number of valid sources and how many of
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* them were migrated so we can reset when all of them have been
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* processed.
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*/
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u32 src_count;
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u32 saved_src_count;
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/*
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* Some irqs are delayed on restore until the source is created,
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* keep track here of how many of them
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*/
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u32 delayed_irqs;
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/* Which queues (priorities) are in use by the guest */
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u8 qmap;
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/* Queue orders */
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u32 q_order;
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u32 q_page_order;
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2018-01-12 05:37:12 +03:00
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/* Flags */
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u8 single_escalation;
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KVM: PPC: Book3S HV: XIVE: Add passthrough support
The KVM XICS-over-XIVE device and the proposed KVM XIVE native device
implement an IRQ space for the guest using the generic IPI interrupts
of the XIVE IC controller. These interrupts are allocated at the OPAL
level and "mapped" into the guest IRQ number space in the range 0-0x1FFF.
Interrupt management is performed in the XIVE way: using loads and
stores on the addresses of the XIVE IPI interrupt ESB pages.
Both KVM devices share the same internal structure caching information
on the interrupts, among which the xive_irq_data struct containing the
addresses of the IPI ESB pages and an extra one in case of pass-through.
The later contains the addresses of the ESB pages of the underlying HW
controller interrupts, PHB4 in all cases for now.
A guest, when running in the XICS legacy interrupt mode, lets the KVM
XICS-over-XIVE device "handle" interrupt management, that is to
perform the loads and stores on the addresses of the ESB pages of the
guest interrupts. However, when running in XIVE native exploitation
mode, the KVM XIVE native device exposes the interrupt ESB pages to
the guest and lets the guest perform directly the loads and stores.
The VMA exposing the ESB pages make use of a custom VM fault handler
which role is to populate the VMA with appropriate pages. When a fault
occurs, the guest IRQ number is deduced from the offset, and the ESB
pages of associated XIVE IPI interrupt are inserted in the VMA (using
the internal structure caching information on the interrupts).
Supporting device passthrough in the guest running in XIVE native
exploitation mode adds some extra refinements because the ESB pages
of a different HW controller (PHB4) need to be exposed to the guest
along with the initial IPI ESB pages of the XIVE IC controller. But
the overall mechanic is the same.
When the device HW irqs are mapped into or unmapped from the guest
IRQ number space, the passthru_irq helpers, kvmppc_xive_set_mapped()
and kvmppc_xive_clr_mapped(), are called to record or clear the
passthrough interrupt information and to perform the switch.
The approach taken by this patch is to clear the ESB pages of the
guest IRQ number being mapped and let the VM fault handler repopulate.
The handler will insert the ESB page corresponding to the HW interrupt
of the device being passed-through or the initial IPI ESB page if the
device is being removed.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2019-04-18 13:39:39 +03:00
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2019-09-27 14:54:01 +03:00
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/* Number of entries in the VP block */
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u32 nr_servers;
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KVM: PPC: Book3S HV: XIVE: Add passthrough support
The KVM XICS-over-XIVE device and the proposed KVM XIVE native device
implement an IRQ space for the guest using the generic IPI interrupts
of the XIVE IC controller. These interrupts are allocated at the OPAL
level and "mapped" into the guest IRQ number space in the range 0-0x1FFF.
Interrupt management is performed in the XIVE way: using loads and
stores on the addresses of the XIVE IPI interrupt ESB pages.
Both KVM devices share the same internal structure caching information
on the interrupts, among which the xive_irq_data struct containing the
addresses of the IPI ESB pages and an extra one in case of pass-through.
The later contains the addresses of the ESB pages of the underlying HW
controller interrupts, PHB4 in all cases for now.
A guest, when running in the XICS legacy interrupt mode, lets the KVM
XICS-over-XIVE device "handle" interrupt management, that is to
perform the loads and stores on the addresses of the ESB pages of the
guest interrupts. However, when running in XIVE native exploitation
mode, the KVM XIVE native device exposes the interrupt ESB pages to
the guest and lets the guest perform directly the loads and stores.
The VMA exposing the ESB pages make use of a custom VM fault handler
which role is to populate the VMA with appropriate pages. When a fault
occurs, the guest IRQ number is deduced from the offset, and the ESB
pages of associated XIVE IPI interrupt are inserted in the VMA (using
the internal structure caching information on the interrupts).
Supporting device passthrough in the guest running in XIVE native
exploitation mode adds some extra refinements because the ESB pages
of a different HW controller (PHB4) need to be exposed to the guest
along with the initial IPI ESB pages of the XIVE IC controller. But
the overall mechanic is the same.
When the device HW irqs are mapped into or unmapped from the guest
IRQ number space, the passthru_irq helpers, kvmppc_xive_set_mapped()
and kvmppc_xive_clr_mapped(), are called to record or clear the
passthrough interrupt information and to perform the switch.
The approach taken by this patch is to clear the ESB pages of the
guest IRQ number being mapped and let the VM fault handler repopulate.
The handler will insert the ESB page corresponding to the HW interrupt
of the device being passed-through or the initial IPI ESB page if the
device is being removed.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2019-04-18 13:39:39 +03:00
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struct kvmppc_xive_ops *ops;
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struct address_space *mapping;
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struct mutex mapping_lock;
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2019-05-24 16:20:30 +03:00
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struct mutex lock;
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2017-04-05 10:54:56 +03:00
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};
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#define KVMPPC_XIVE_Q_COUNT 8
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struct kvmppc_xive_vcpu {
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struct kvmppc_xive *xive;
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struct kvm_vcpu *vcpu;
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bool valid;
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/* Server number. This is the HW CPU ID from a guest perspective */
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u32 server_num;
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/*
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* HW VP corresponding to this VCPU. This is the base of the VP
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* block plus the server number.
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*/
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u32 vp_id;
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u32 vp_chip_id;
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u32 vp_cam;
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/* IPI used for sending ... IPIs */
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u32 vp_ipi;
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struct xive_irq_data vp_ipi_data;
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/* Local emulation state */
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uint8_t cppr; /* guest CPPR */
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uint8_t hw_cppr;/* Hardware CPPR */
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uint8_t mfrr;
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uint8_t pending;
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/* Each VP has 8 queues though we only provision some */
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struct xive_q queues[KVMPPC_XIVE_Q_COUNT];
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u32 esc_virq[KVMPPC_XIVE_Q_COUNT];
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char *esc_virq_names[KVMPPC_XIVE_Q_COUNT];
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/* Stash a delayed irq on restore from migration (see set_icp) */
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u32 delayed_irq;
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/* Stats */
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u64 stat_rm_h_xirr;
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u64 stat_rm_h_ipoll;
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u64 stat_rm_h_cppr;
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u64 stat_rm_h_eoi;
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u64 stat_rm_h_ipi;
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u64 stat_vm_h_xirr;
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u64 stat_vm_h_ipoll;
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u64 stat_vm_h_cppr;
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u64 stat_vm_h_eoi;
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u64 stat_vm_h_ipi;
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};
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static inline struct kvm_vcpu *kvmppc_xive_find_server(struct kvm *kvm, u32 nr)
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{
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struct kvm_vcpu *vcpu = NULL;
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int i;
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kvm_for_each_vcpu(i, vcpu, kvm) {
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if (vcpu->arch.xive_vcpu && nr == vcpu->arch.xive_vcpu->server_num)
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return vcpu;
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}
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return NULL;
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}
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static inline struct kvmppc_xive_src_block *kvmppc_xive_find_source(struct kvmppc_xive *xive,
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u32 irq, u16 *source)
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{
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u32 bid = irq >> KVMPPC_XICS_ICS_SHIFT;
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u16 src = irq & KVMPPC_XICS_SRC_MASK;
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if (source)
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*source = src;
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if (bid > KVMPPC_XICS_MAX_ICS_ID)
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return NULL;
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return xive->src_blocks[bid];
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}
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2019-04-18 13:39:28 +03:00
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static inline u32 kvmppc_xive_vp(struct kvmppc_xive *xive, u32 server)
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{
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return xive->vp_base + kvmppc_pack_vcpu_id(xive->kvm, server);
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}
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KVM: PPC: Book3S HV: XIVE: Ensure VP isn't already in use
Connecting a vCPU to a XIVE KVM device means establishing a 1:1
association between a vCPU id and the offset (VP id) of a VP
structure within a fixed size block of VPs. We currently try to
enforce the 1:1 relationship by checking that a vCPU with the
same id isn't already connected. This is good but unfortunately
not enough because we don't map VP ids to raw vCPU ids but to
packed vCPU ids, and the packing function kvmppc_pack_vcpu_id()
isn't bijective by design. We got away with it because QEMU passes
vCPU ids that fit well in the packing pattern. But nothing prevents
userspace to come up with a forged vCPU id resulting in a packed id
collision which causes the KVM device to associate two vCPUs to the
same VP. This greatly confuses the irq layer and ultimately crashes
the kernel, as shown below.
Example: a guest with 1 guest thread per core, a core stride of
8 and 300 vCPUs has vCPU ids 0,8,16...2392. If QEMU is patched to
inject at some point an invalid vCPU id 348, which is the packed
version of itself and 2392, we get:
genirq: Flags mismatch irq 199. 00010000 (kvm-2-2392) vs. 00010000 (kvm-2-348)
CPU: 24 PID: 88176 Comm: qemu-system-ppc Not tainted 5.3.0-xive-nr-servers-5.3-gku+ #38
Call Trace:
[c000003f7f9937e0] [c000000000c0110c] dump_stack+0xb0/0xf4 (unreliable)
[c000003f7f993820] [c0000000001cb480] __setup_irq+0xa70/0xad0
[c000003f7f9938d0] [c0000000001cb75c] request_threaded_irq+0x13c/0x260
[c000003f7f993940] [c00800000d44e7ac] kvmppc_xive_attach_escalation+0x104/0x270 [kvm]
[c000003f7f9939d0] [c00800000d45013c] kvmppc_xive_connect_vcpu+0x424/0x620 [kvm]
[c000003f7f993ac0] [c00800000d444428] kvm_arch_vcpu_ioctl+0x260/0x448 [kvm]
[c000003f7f993b90] [c00800000d43593c] kvm_vcpu_ioctl+0x154/0x7c8 [kvm]
[c000003f7f993d00] [c0000000004840f0] do_vfs_ioctl+0xe0/0xc30
[c000003f7f993db0] [c000000000484d44] ksys_ioctl+0x104/0x120
[c000003f7f993e00] [c000000000484d88] sys_ioctl+0x28/0x80
[c000003f7f993e20] [c00000000000b278] system_call+0x5c/0x68
xive-kvm: Failed to request escalation interrupt for queue 0 of VCPU 2392
------------[ cut here ]------------
remove_proc_entry: removing non-empty directory 'irq/199', leaking at least 'kvm-2-348'
WARNING: CPU: 24 PID: 88176 at /home/greg/Work/linux/kernel-kvm-ppc/fs/proc/generic.c:684 remove_proc_entry+0x1ec/0x200
Modules linked in: kvm_hv kvm dm_mod vhost_net vhost tap xt_CHECKSUM iptable_mangle xt_MASQUERADE iptable_nat nf_nat xt_conntrack nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 ipt_REJECT nf_reject_ipv4 tun bridge stp llc ebtable_filter ebtables ip6table_filter ip6_tables iptable_filter squashfs loop fuse i2c_dev sg ofpart ocxl powernv_flash at24 xts mtd uio_pdrv_genirq vmx_crypto opal_prd ipmi_powernv uio ipmi_devintf ipmi_msghandler ibmpowernv ib_iser rdma_cm iw_cm ib_cm ib_core iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi ip_tables ext4 mbcache jbd2 raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor xor async_tx raid6_pq libcrc32c raid1 raid0 linear sd_mod ast i2c_algo_bit drm_vram_helper ttm drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops drm ahci libahci libata tg3 drm_panel_orientation_quirks [last unloaded: kvm]
CPU: 24 PID: 88176 Comm: qemu-system-ppc Not tainted 5.3.0-xive-nr-servers-5.3-gku+ #38
NIP: c00000000053b0cc LR: c00000000053b0c8 CTR: c0000000000ba3b0
REGS: c000003f7f9934b0 TRAP: 0700 Not tainted (5.3.0-xive-nr-servers-5.3-gku+)
MSR: 9000000000029033 <SF,HV,EE,ME,IR,DR,RI,LE> CR: 48228222 XER: 20040000
CFAR: c000000000131a50 IRQMASK: 0
GPR00: c00000000053b0c8 c000003f7f993740 c0000000015ec500 0000000000000057
GPR04: 0000000000000001 0000000000000000 000049fb98484262 0000000000001bcf
GPR08: 0000000000000007 0000000000000007 0000000000000001 9000000000001033
GPR12: 0000000000008000 c000003ffffeb800 0000000000000000 000000012f4ce5a1
GPR16: 000000012ef5a0c8 0000000000000000 000000012f113bb0 0000000000000000
GPR20: 000000012f45d918 c000003f863758b0 c000003f86375870 0000000000000006
GPR24: c000003f86375a30 0000000000000007 c0002039373d9020 c0000000014c4a48
GPR28: 0000000000000001 c000003fe62a4f6b c00020394b2e9fab c000003fe62a4ec0
NIP [c00000000053b0cc] remove_proc_entry+0x1ec/0x200
LR [c00000000053b0c8] remove_proc_entry+0x1e8/0x200
Call Trace:
[c000003f7f993740] [c00000000053b0c8] remove_proc_entry+0x1e8/0x200 (unreliable)
[c000003f7f9937e0] [c0000000001d3654] unregister_irq_proc+0x114/0x150
[c000003f7f993880] [c0000000001c6284] free_desc+0x54/0xb0
[c000003f7f9938c0] [c0000000001c65ec] irq_free_descs+0xac/0x100
[c000003f7f993910] [c0000000001d1ff8] irq_dispose_mapping+0x68/0x80
[c000003f7f993940] [c00800000d44e8a4] kvmppc_xive_attach_escalation+0x1fc/0x270 [kvm]
[c000003f7f9939d0] [c00800000d45013c] kvmppc_xive_connect_vcpu+0x424/0x620 [kvm]
[c000003f7f993ac0] [c00800000d444428] kvm_arch_vcpu_ioctl+0x260/0x448 [kvm]
[c000003f7f993b90] [c00800000d43593c] kvm_vcpu_ioctl+0x154/0x7c8 [kvm]
[c000003f7f993d00] [c0000000004840f0] do_vfs_ioctl+0xe0/0xc30
[c000003f7f993db0] [c000000000484d44] ksys_ioctl+0x104/0x120
[c000003f7f993e00] [c000000000484d88] sys_ioctl+0x28/0x80
[c000003f7f993e20] [c00000000000b278] system_call+0x5c/0x68
Instruction dump:
2c230000 41820008 3923ff78 e8e900a0 3c82ff69 3c62ff8d 7fa6eb78 7fc5f378
3884f080 3863b948 4bbf6925 60000000 <0fe00000> 4bffff7c fba10088 4bbf6e41
---[ end trace b925b67a74a1d8d1 ]---
BUG: Kernel NULL pointer dereference at 0x00000010
Faulting instruction address: 0xc00800000d44fc04
Oops: Kernel access of bad area, sig: 11 [#1]
LE PAGE_SIZE=64K MMU=Radix MMU=Hash SMP NR_CPUS=2048 NUMA PowerNV
Modules linked in: kvm_hv kvm dm_mod vhost_net vhost tap xt_CHECKSUM iptable_mangle xt_MASQUERADE iptable_nat nf_nat xt_conntrack nf_conntrack nf_defrag_ipv6 nf_defrag_ipv4 ipt_REJECT nf_reject_ipv4 tun bridge stp llc ebtable_filter ebtables ip6table_filter ip6_tables iptable_filter squashfs loop fuse i2c_dev sg ofpart ocxl powernv_flash at24 xts mtd uio_pdrv_genirq vmx_crypto opal_prd ipmi_powernv uio ipmi_devintf ipmi_msghandler ibmpowernv ib_iser rdma_cm iw_cm ib_cm ib_core iscsi_tcp libiscsi_tcp libiscsi scsi_transport_iscsi ip_tables ext4 mbcache jbd2 raid10 raid456 async_raid6_recov async_memcpy async_pq async_xor xor async_tx raid6_pq libcrc32c raid1 raid0 linear sd_mod ast i2c_algo_bit drm_vram_helper ttm drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops drm ahci libahci libata tg3 drm_panel_orientation_quirks [last unloaded: kvm]
CPU: 24 PID: 88176 Comm: qemu-system-ppc Tainted: G W 5.3.0-xive-nr-servers-5.3-gku+ #38
NIP: c00800000d44fc04 LR: c00800000d44fc00 CTR: c0000000001cd970
REGS: c000003f7f9938e0 TRAP: 0300 Tainted: G W (5.3.0-xive-nr-servers-5.3-gku+)
MSR: 9000000000009033 <SF,HV,EE,ME,IR,DR,RI,LE> CR: 24228882 XER: 20040000
CFAR: c0000000001cd9ac DAR: 0000000000000010 DSISR: 40000000 IRQMASK: 0
GPR00: c00800000d44fc00 c000003f7f993b70 c00800000d468300 0000000000000000
GPR04: 00000000000000c7 0000000000000000 0000000000000000 c000003ffacd06d8
GPR08: 0000000000000000 c000003ffacd0738 0000000000000000 fffffffffffffffd
GPR12: 0000000000000040 c000003ffffeb800 0000000000000000 000000012f4ce5a1
GPR16: 000000012ef5a0c8 0000000000000000 000000012f113bb0 0000000000000000
GPR20: 000000012f45d918 00007ffffe0d9a80 000000012f4f5df0 000000012ef8c9f8
GPR24: 0000000000000001 0000000000000000 c000003fe4501ed0 c000003f8b1d0000
GPR28: c0000033314689c0 c000003fe4501c00 c000003fe4501e70 c000003fe4501e90
NIP [c00800000d44fc04] kvmppc_xive_cleanup_vcpu+0xfc/0x210 [kvm]
LR [c00800000d44fc00] kvmppc_xive_cleanup_vcpu+0xf8/0x210 [kvm]
Call Trace:
[c000003f7f993b70] [c00800000d44fc00] kvmppc_xive_cleanup_vcpu+0xf8/0x210 [kvm] (unreliable)
[c000003f7f993bd0] [c00800000d450bd4] kvmppc_xive_release+0xdc/0x1b0 [kvm]
[c000003f7f993c30] [c00800000d436a98] kvm_device_release+0xb0/0x110 [kvm]
[c000003f7f993c70] [c00000000046730c] __fput+0xec/0x320
[c000003f7f993cd0] [c000000000164ae0] task_work_run+0x150/0x1c0
[c000003f7f993d30] [c000000000025034] do_notify_resume+0x304/0x440
[c000003f7f993e20] [c00000000000dcc4] ret_from_except_lite+0x70/0x74
Instruction dump:
3bff0008 7fbfd040 419e0054 847e0004 2fa30000 419effec e93d0000 8929203c
2f890000 419effb8 4800821d e8410018 <e9230010> e9490008 9b2a0039 7c0004ac
---[ end trace b925b67a74a1d8d2 ]---
Kernel panic - not syncing: Fatal exception
This affects both XIVE and XICS-on-XIVE devices since the beginning.
Check the VP id instead of the vCPU id when a new vCPU is connected.
The allocation of the XIVE CPU structure in kvmppc_xive_connect_vcpu()
is moved after the check to avoid the need for rollback.
Cc: stable@vger.kernel.org # v4.12+
Signed-off-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
2019-09-27 14:53:43 +03:00
|
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static inline bool kvmppc_xive_vp_in_use(struct kvm *kvm, u32 vp_id)
|
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{
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struct kvm_vcpu *vcpu = NULL;
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int i;
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kvm_for_each_vcpu(i, vcpu, kvm) {
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if (vcpu->arch.xive_vcpu && vp_id == vcpu->arch.xive_vcpu->vp_id)
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return true;
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}
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return false;
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}
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2017-04-05 10:54:56 +03:00
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/*
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* Mapping between guest priorities and host priorities
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* is as follow.
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*
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* Guest request for 0...6 are honored. Guest request for anything
|
2018-01-12 05:37:12 +03:00
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* higher results in a priority of 6 being applied.
|
2017-04-05 10:54:56 +03:00
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*
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* Similar mapping is done for CPPR values
|
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*/
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static inline u8 xive_prio_from_guest(u8 prio)
|
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{
|
2018-01-12 05:37:12 +03:00
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if (prio == 0xff || prio < 6)
|
2017-04-05 10:54:56 +03:00
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return prio;
|
2018-01-12 05:37:12 +03:00
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return 6;
|
2017-04-05 10:54:56 +03:00
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}
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static inline u8 xive_prio_to_guest(u8 prio)
|
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|
|
|
{
|
2018-01-12 05:37:12 +03:00
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|
return prio;
|
2017-04-05 10:54:56 +03:00
|
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}
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static inline u32 __xive_read_eq(__be32 *qpage, u32 msk, u32 *idx, u32 *toggle)
|
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|
{
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u32 cur;
|
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if (!qpage)
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return 0;
|
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cur = be32_to_cpup(qpage + *idx);
|
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if ((cur >> 31) == *toggle)
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return 0;
|
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*idx = (*idx + 1) & msk;
|
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if (*idx == 0)
|
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(*toggle) ^= 1;
|
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return cur & 0x7fffffff;
|
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}
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extern unsigned long xive_rm_h_xirr(struct kvm_vcpu *vcpu);
|
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extern unsigned long xive_rm_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server);
|
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extern int xive_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server,
|
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unsigned long mfrr);
|
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extern int xive_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr);
|
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extern int xive_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr);
|
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extern unsigned long (*__xive_vm_h_xirr)(struct kvm_vcpu *vcpu);
|
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extern unsigned long (*__xive_vm_h_ipoll)(struct kvm_vcpu *vcpu, unsigned long server);
|
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|
extern int (*__xive_vm_h_ipi)(struct kvm_vcpu *vcpu, unsigned long server,
|
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|
|
|
unsigned long mfrr);
|
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|
|
|
extern int (*__xive_vm_h_cppr)(struct kvm_vcpu *vcpu, unsigned long cppr);
|
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|
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|
extern int (*__xive_vm_h_eoi)(struct kvm_vcpu *vcpu, unsigned long xirr);
|
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|
|
|
|
2019-04-18 13:39:28 +03:00
|
|
|
/*
|
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|
|
|
* Common Xive routines for XICS-over-XIVE and XIVE native
|
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|
|
|
*/
|
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|
|
|
void kvmppc_xive_disable_vcpu_interrupts(struct kvm_vcpu *vcpu);
|
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|
|
|
int kvmppc_xive_debug_show_queues(struct seq_file *m, struct kvm_vcpu *vcpu);
|
2019-04-18 13:39:29 +03:00
|
|
|
struct kvmppc_xive_src_block *kvmppc_xive_create_src_block(
|
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|
|
|
struct kvmppc_xive *xive, int irq);
|
|
|
|
|
void kvmppc_xive_free_sources(struct kvmppc_xive_src_block *sb);
|
2019-04-18 13:39:30 +03:00
|
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|
int kvmppc_xive_select_target(struct kvm *kvm, u32 *server, u8 prio);
|
2019-04-18 13:39:31 +03:00
|
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|
int kvmppc_xive_attach_escalation(struct kvm_vcpu *vcpu, u8 prio,
|
|
|
|
|
bool single_escalation);
|
2019-04-18 13:39:42 +03:00
|
|
|
struct kvmppc_xive *kvmppc_xive_get_device(struct kvm *kvm, u32 type);
|
powerpc/xive: Implement get_irqchip_state method for XIVE to fix shutdown race
Testing has revealed the existence of a race condition where a XIVE
interrupt being shut down can be in one of the XIVE interrupt queues
(of which there are up to 8 per CPU, one for each priority) at the
point where free_irq() is called. If this happens, can return an
interrupt number which has been shut down. This can lead to various
symptoms:
- irq_to_desc(irq) can be NULL. In this case, no end-of-interrupt
function gets called, resulting in the CPU's elevated interrupt
priority (numerically lowered CPPR) never gets reset. That then
means that the CPU stops processing interrupts, causing device
timeouts and other errors in various device drivers.
- The irq descriptor or related data structures can be in the process
of being freed as the interrupt code is using them. This typically
leads to crashes due to bad pointer dereferences.
This race is basically what commit 62e0468650c3 ("genirq: Add optional
hardware synchronization for shutdown", 2019-06-28) is intended to
fix, given a get_irqchip_state() method for the interrupt controller
being used. It works by polling the interrupt controller when an
interrupt is being freed until the controller says it is not pending.
With XIVE, the PQ bits of the interrupt source indicate the state of
the interrupt source, and in particular the P bit goes from 0 to 1 at
the point where the hardware writes an entry into the interrupt queue
that this interrupt is directed towards. Normally, the code will then
process the interrupt and do an end-of-interrupt (EOI) operation which
will reset PQ to 00 (assuming another interrupt hasn't been generated
in the meantime). However, there are situations where the code resets
P even though a queue entry exists (for example, by setting PQ to 01,
which disables the interrupt source), and also situations where the
code leaves P at 1 after removing the queue entry (for example, this
is done for escalation interrupts so they cannot fire again until
they are explicitly re-enabled).
The code already has a 'saved_p' flag for the interrupt source which
indicates that a queue entry exists, although it isn't maintained
consistently. This patch adds a 'stale_p' flag to indicate that
P has been left at 1 after processing a queue entry, and adds code
to set and clear saved_p and stale_p as necessary to maintain a
consistent indication of whether a queue entry may or may not exist.
With this, we can implement xive_get_irqchip_state() by looking at
stale_p, saved_p and the ESB PQ bits for the interrupt.
There is some additional code to handle escalation interrupts
properly; because they are enabled and disabled in KVM assembly code,
which does not have access to the xive_irq_data struct for the
escalation interrupt. Hence, stale_p may be incorrect when the
escalation interrupt is freed in kvmppc_xive_{,native_}cleanup_vcpu().
Fortunately, we can fix it up by looking at vcpu->arch.xive_esc_on,
with some careful attention to barriers in order to ensure the correct
result if xive_esc_irq() races with kvmppc_xive_cleanup_vcpu().
Finally, this adds code to make noise on the console (pr_crit and
WARN_ON(1)) if we find an interrupt queue entry for an interrupt
which does not have a descriptor. While this won't catch the race
reliably, if it does get triggered it will be an indication that
the race is occurring and needs to be debugged.
Fixes: 243e25112d06 ("powerpc/xive: Native exploitation of the XIVE interrupt controller")
Cc: stable@vger.kernel.org # v4.12+
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20190813100648.GE9567@blackberry
2019-08-13 13:06:48 +03:00
|
|
|
void xive_cleanup_single_escalation(struct kvm_vcpu *vcpu,
|
|
|
|
|
struct kvmppc_xive_vcpu *xc, int irq);
|
2019-09-27 14:53:55 +03:00
|
|
|
int kvmppc_xive_compute_vp_id(struct kvmppc_xive *xive, u32 cpu, u32 *vp);
|
2019-09-27 14:54:01 +03:00
|
|
|
int kvmppc_xive_set_nr_servers(struct kvmppc_xive *xive, u64 addr);
|
2019-04-18 13:39:28 +03:00
|
|
|
|
2017-04-05 10:54:56 +03:00
|
|
|
#endif /* CONFIG_KVM_XICS */
|
|
|
|
|
#endif /* _KVM_PPC_BOOK3S_XICS_H */
|
