2012-09-13 19:41:48 +04:00
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/*
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* Device Tree Include file for Marvell Armada XP family SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* Contains definitions specific to the Armada XP MV78260 SoC that are not
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* common to all Armada XP SoCs.
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*/
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2013-07-26 17:17:56 +04:00
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#include "armada-xp.dtsi"
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2012-09-13 19:41:48 +04:00
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/ {
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model = "Marvell Armada XP MV78260 SoC";
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compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
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2012-09-20 00:53:01 +04:00
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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gpio2 = &gpio2;
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};
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2012-11-17 18:22:24 +04:00
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cpus {
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2013-04-12 18:29:06 +04:00
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#address-cells = <1>;
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#size-cells = <0>;
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2012-11-17 18:22:24 +04:00
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2013-04-12 18:29:06 +04:00
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cpu@0 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <0>;
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clocks = <&cpuclk 0>;
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};
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2012-11-17 18:22:24 +04:00
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2013-04-12 18:29:06 +04:00
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cpu@1 {
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device_type = "cpu";
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compatible = "marvell,sheeva-v7";
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reg = <1>;
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clocks = <&cpuclk 1>;
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};
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2012-11-17 18:22:24 +04:00
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};
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2012-09-13 19:41:48 +04:00
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soc {
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2013-04-12 18:29:09 +04:00
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internal-regs {
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pinctrl {
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compatible = "marvell,mv78260-pinctrl";
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reg = <0x18000 0x38>;
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sdio_pins: sdio-pins {
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marvell,pins = "mpp30", "mpp31", "mpp32",
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"mpp33", "mpp34", "mpp35";
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marvell,function = "sd0";
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};
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2012-12-21 18:49:06 +04:00
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};
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2012-09-20 00:53:01 +04:00
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2013-04-12 18:29:09 +04:00
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gpio0: gpio@18100 {
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compatible = "marvell,orion-gpio";
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reg = <0x18100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <82>, <83>, <84>, <85>;
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};
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2012-09-20 00:53:01 +04:00
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2013-04-12 18:29:09 +04:00
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gpio1: gpio@18140 {
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compatible = "marvell,orion-gpio";
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reg = <0x18140 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <87>, <88>, <89>, <90>;
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};
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2012-09-20 00:53:01 +04:00
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2013-04-12 18:29:09 +04:00
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gpio2: gpio@18180 {
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compatible = "marvell,orion-gpio";
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reg = <0x18180 0x40>;
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ngpios = <3>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupts-cells = <2>;
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interrupts = <91>;
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};
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2013-01-06 14:10:41 +04:00
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2013-04-12 18:29:09 +04:00
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ethernet@34000 {
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2013-01-06 14:10:41 +04:00
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compatible = "marvell,armada-370-neta";
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2013-06-22 20:52:27 +04:00
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reg = <0x34000 0x4000>;
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2013-01-06 14:10:41 +04:00
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interrupts = <14>;
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clocks = <&gateclk 1>;
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status = "disabled";
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2013-04-10 01:06:34 +04:00
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};
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2013-04-12 18:29:09 +04:00
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/*
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* MV78260 has 3 PCIe units Gen2.0: Two units can be
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* configured as x4 or quad x1 lanes. One unit is
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* x4/x1.
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*/
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pcie-controller {
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compatible = "marvell,armada-xp-pcie";
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2013-04-10 01:06:34 +04:00
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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2013-04-12 18:29:09 +04:00
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bus-range = <0x00 0xff>;
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ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
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0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
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0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
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0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
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0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
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0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
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0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
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0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
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0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 58>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 5>;
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status = "disabled";
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};
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pcie@2,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
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reg = <0x1000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 59>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <1>;
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clocks = <&gateclk 6>;
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status = "disabled";
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};
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pcie@3,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
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reg = <0x1800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 60>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <2>;
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clocks = <&gateclk 7>;
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status = "disabled";
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};
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pcie@4,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
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reg = <0x2000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 61>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <3>;
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clocks = <&gateclk 8>;
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status = "disabled";
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};
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pcie@9,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
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reg = <0x4800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 99>;
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marvell,pcie-port = <2>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 26>;
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status = "disabled";
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};
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pcie@10,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
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reg = <0x5000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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ranges;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 103>;
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marvell,pcie-port = <3>;
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marvell,pcie-lane = <0>;
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clocks = <&gateclk 27>;
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status = "disabled";
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};
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2013-04-10 01:06:34 +04:00
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};
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};
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2012-09-13 19:41:48 +04:00
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};
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};
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