x86: dtb: Add a device tree for CE4100
History:
v1..v2:
- dropped device_type except for cpu & pci. I have the compatible string
for pci so I can drop the device_type once it is possible
- I lowercased all compatible types. I will need to resend some patches
which have upper case intel
- The cpu had the same compatible string as the soc node. So I added to
the soc node -immr for internel memory mapped registers.
- I added generic names for all parts.
- I reworked the i2c bars matching the way you suggested. I added a
compatible node for the PCI device which only the PCI ids in its
compatible string. The bars (each represents a complete i2c
controller) have a "intel,ce4100-i2c-controller" compatible node. It
is not used by the driver.
The driver is probed via PCI ids (by the pci subsystem not OF) and
matches the bar address against the ressource in the child node. Once
there is a hit the node is attached.
- The SPI driver is also probed via pci. However I also attached a
compatible property based on PCI ids
v2..v3:
- intel,ce4100-immr become intel,ce4100-cp. cp stands for core
peripherals. The Atom data sheet talks here about ACPI devices. Since
we don't have ACPI this does not apply here.
- The interrupt map is gone. There are now plenty of device nodes.
- The "unit address string" got fixed, it uses not DD,V format.
v3..v4:
- added descriptions for compatible nodes introduced here:
- intel,ce4100-ioapic
- intel,ce4100-lapic
- intel,ce4100-hpet
- intel,ce4100
- intel,ce4100-cp
- intel,ce4100-pci
- added a description about I2C controller magic.
- Added gpio-controller and gpio-cells property to gpio devices. Those
properties are not (yet) used.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Cc: sodaville@linutronix.de
Cc: devicetree-discuss@lists.ozlabs.org
LKML-Reference: <1298405266-1624-4-git-send-email-bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-02-22 23:07:38 +03:00
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/*
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* CE4100 on Falcon Falls
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*
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* (c) Copyright 2010 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; version 2 of the License.
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*/
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/dts-v1/;
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/ {
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model = "intel,falconfalls";
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compatible = "intel,falconfalls";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "intel,ce4100";
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reg = <0>;
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lapic = <&lapic0>;
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};
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};
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soc@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "intel,ce4100-cp";
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ranges;
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ioapic1: interrupt-controller@fec00000 {
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#interrupt-cells = <2>;
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compatible = "intel,ce4100-ioapic";
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interrupt-controller;
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reg = <0xfec00000 0x1000>;
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};
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timer@fed00000 {
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compatible = "intel,ce4100-hpet";
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reg = <0xfed00000 0x200>;
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};
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lapic0: interrupt-controller@fee00000 {
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compatible = "intel,ce4100-lapic";
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reg = <0xfee00000 0x1000>;
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};
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pci@3fc {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "intel,ce4100-pci", "pci";
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device_type = "pci";
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bus-range = <0 0>;
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ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
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0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
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0x0000000 0 0x0 0x0 0 0x100>;
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/* Secondary IO-APIC */
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ioapic2: interrupt-controller@0,1 {
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#interrupt-cells = <2>;
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compatible = "intel,ce4100-ioapic";
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interrupt-controller;
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reg = <0x100 0x0 0x0 0x0 0x0>;
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assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>;
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};
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pci@1,0 {
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#address-cells = <3>;
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#size-cells = <2>;
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compatible = "intel,ce4100-pci", "pci";
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device_type = "pci";
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bus-range = <1 1>;
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2011-04-07 16:13:15 +04:00
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reg = <0x0800 0x0 0x0 0x0 0x0>;
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x86: dtb: Add a device tree for CE4100
History:
v1..v2:
- dropped device_type except for cpu & pci. I have the compatible string
for pci so I can drop the device_type once it is possible
- I lowercased all compatible types. I will need to resend some patches
which have upper case intel
- The cpu had the same compatible string as the soc node. So I added to
the soc node -immr for internel memory mapped registers.
- I added generic names for all parts.
- I reworked the i2c bars matching the way you suggested. I added a
compatible node for the PCI device which only the PCI ids in its
compatible string. The bars (each represents a complete i2c
controller) have a "intel,ce4100-i2c-controller" compatible node. It
is not used by the driver.
The driver is probed via PCI ids (by the pci subsystem not OF) and
matches the bar address against the ressource in the child node. Once
there is a hit the node is attached.
- The SPI driver is also probed via pci. However I also attached a
compatible property based on PCI ids
v2..v3:
- intel,ce4100-immr become intel,ce4100-cp. cp stands for core
peripherals. The Atom data sheet talks here about ACPI devices. Since
we don't have ACPI this does not apply here.
- The interrupt map is gone. There are now plenty of device nodes.
- The "unit address string" got fixed, it uses not DD,V format.
v3..v4:
- added descriptions for compatible nodes introduced here:
- intel,ce4100-ioapic
- intel,ce4100-lapic
- intel,ce4100-hpet
- intel,ce4100
- intel,ce4100-cp
- intel,ce4100-pci
- added a description about I2C controller magic.
- Added gpio-controller and gpio-cells property to gpio devices. Those
properties are not (yet) used.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Cc: sodaville@linutronix.de
Cc: devicetree-discuss@lists.ozlabs.org
LKML-Reference: <1298405266-1624-4-git-send-email-bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-02-22 23:07:38 +03:00
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ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>;
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interrupt-parent = <&ioapic2>;
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display@2,0 {
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compatible = "pci8086,2e5b.2",
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"pci8086,2e5b",
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"pciclass038000",
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"pciclass0380";
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reg = <0x11000 0x0 0x0 0x0 0x0>;
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interrupts = <0 1>;
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};
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multimedia@3,0 {
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compatible = "pci8086,2e5c.2",
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"pci8086,2e5c",
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"pciclass048000",
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"pciclass0480";
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reg = <0x11800 0x0 0x0 0x0 0x0>;
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interrupts = <2 1>;
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};
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multimedia@4,0 {
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compatible = "pci8086,2e5d.2",
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"pci8086,2e5d",
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"pciclass048000",
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"pciclass0480";
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reg = <0x12000 0x0 0x0 0x0 0x0>;
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interrupts = <4 1>;
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};
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multimedia@4,1 {
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compatible = "pci8086,2e5e.2",
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"pci8086,2e5e",
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"pciclass048000",
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"pciclass0480";
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reg = <0x12100 0x0 0x0 0x0 0x0>;
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interrupts = <5 1>;
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};
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sound@6,0 {
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compatible = "pci8086,2e5f.2",
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"pci8086,2e5f",
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"pciclass040100",
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"pciclass0401";
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reg = <0x13000 0x0 0x0 0x0 0x0>;
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interrupts = <6 1>;
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};
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sound@6,1 {
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compatible = "pci8086,2e5f.2",
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"pci8086,2e5f",
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"pciclass040100",
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"pciclass0401";
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reg = <0x13100 0x0 0x0 0x0 0x0>;
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interrupts = <7 1>;
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};
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sound@6,2 {
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compatible = "pci8086,2e60.2",
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"pci8086,2e60",
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"pciclass040100",
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"pciclass0401";
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reg = <0x13200 0x0 0x0 0x0 0x0>;
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interrupts = <8 1>;
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};
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display@8,0 {
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compatible = "pci8086,2e61.2",
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"pci8086,2e61",
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"pciclass038000",
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"pciclass0380";
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reg = <0x14000 0x0 0x0 0x0 0x0>;
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interrupts = <9 1>;
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};
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display@8,1 {
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compatible = "pci8086,2e62.2",
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"pci8086,2e62",
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"pciclass038000",
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"pciclass0380";
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reg = <0x14100 0x0 0x0 0x0 0x0>;
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interrupts = <10 1>;
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};
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multimedia@8,2 {
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compatible = "pci8086,2e63.2",
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"pci8086,2e63",
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"pciclass048000",
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"pciclass0480";
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reg = <0x14200 0x0 0x0 0x0 0x0>;
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interrupts = <11 1>;
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};
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entertainment-encryption@9,0 {
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compatible = "pci8086,2e64.2",
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"pci8086,2e64",
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"pciclass101000",
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"pciclass1010";
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reg = <0x14800 0x0 0x0 0x0 0x0>;
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interrupts = <12 1>;
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};
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localbus@a,0 {
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compatible = "pci8086,2e65.2",
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"pci8086,2e65",
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"pciclassff0000",
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"pciclassff00";
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reg = <0x15000 0x0 0x0 0x0 0x0>;
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};
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serial@b,0 {
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compatible = "pci8086,2e66.2",
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"pci8086,2e66",
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"pciclass070003",
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"pciclass0700";
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reg = <0x15800 0x0 0x0 0x0 0x0>;
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interrupts = <14 1>;
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};
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2011-06-27 11:26:23 +04:00
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pcigpio: gpio@b,1 {
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#gpio-cells = <2>;
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#interrupt-cells = <2>;
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x86: dtb: Add a device tree for CE4100
History:
v1..v2:
- dropped device_type except for cpu & pci. I have the compatible string
for pci so I can drop the device_type once it is possible
- I lowercased all compatible types. I will need to resend some patches
which have upper case intel
- The cpu had the same compatible string as the soc node. So I added to
the soc node -immr for internel memory mapped registers.
- I added generic names for all parts.
- I reworked the i2c bars matching the way you suggested. I added a
compatible node for the PCI device which only the PCI ids in its
compatible string. The bars (each represents a complete i2c
controller) have a "intel,ce4100-i2c-controller" compatible node. It
is not used by the driver.
The driver is probed via PCI ids (by the pci subsystem not OF) and
matches the bar address against the ressource in the child node. Once
there is a hit the node is attached.
- The SPI driver is also probed via pci. However I also attached a
compatible property based on PCI ids
v2..v3:
- intel,ce4100-immr become intel,ce4100-cp. cp stands for core
peripherals. The Atom data sheet talks here about ACPI devices. Since
we don't have ACPI this does not apply here.
- The interrupt map is gone. There are now plenty of device nodes.
- The "unit address string" got fixed, it uses not DD,V format.
v3..v4:
- added descriptions for compatible nodes introduced here:
- intel,ce4100-ioapic
- intel,ce4100-lapic
- intel,ce4100-hpet
- intel,ce4100
- intel,ce4100-cp
- intel,ce4100-pci
- added a description about I2C controller magic.
- Added gpio-controller and gpio-cells property to gpio devices. Those
properties are not (yet) used.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Cc: sodaville@linutronix.de
Cc: devicetree-discuss@lists.ozlabs.org
LKML-Reference: <1298405266-1624-4-git-send-email-bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-02-22 23:07:38 +03:00
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compatible = "pci8086,2e67.2",
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"pci8086,2e67",
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"pciclassff0000",
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"pciclassff00";
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reg = <0x15900 0x0 0x0 0x0 0x0>;
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interrupts = <15 1>;
|
2011-06-27 11:26:23 +04:00
|
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|
interrupt-controller;
|
x86: dtb: Add a device tree for CE4100
History:
v1..v2:
- dropped device_type except for cpu & pci. I have the compatible string
for pci so I can drop the device_type once it is possible
- I lowercased all compatible types. I will need to resend some patches
which have upper case intel
- The cpu had the same compatible string as the soc node. So I added to
the soc node -immr for internel memory mapped registers.
- I added generic names for all parts.
- I reworked the i2c bars matching the way you suggested. I added a
compatible node for the PCI device which only the PCI ids in its
compatible string. The bars (each represents a complete i2c
controller) have a "intel,ce4100-i2c-controller" compatible node. It
is not used by the driver.
The driver is probed via PCI ids (by the pci subsystem not OF) and
matches the bar address against the ressource in the child node. Once
there is a hit the node is attached.
- The SPI driver is also probed via pci. However I also attached a
compatible property based on PCI ids
v2..v3:
- intel,ce4100-immr become intel,ce4100-cp. cp stands for core
peripherals. The Atom data sheet talks here about ACPI devices. Since
we don't have ACPI this does not apply here.
- The interrupt map is gone. There are now plenty of device nodes.
- The "unit address string" got fixed, it uses not DD,V format.
v3..v4:
- added descriptions for compatible nodes introduced here:
- intel,ce4100-ioapic
- intel,ce4100-lapic
- intel,ce4100-hpet
- intel,ce4100
- intel,ce4100-cp
- intel,ce4100-pci
- added a description about I2C controller magic.
- Added gpio-controller and gpio-cells property to gpio devices. Those
properties are not (yet) used.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Cc: sodaville@linutronix.de
Cc: devicetree-discuss@lists.ozlabs.org
LKML-Reference: <1298405266-1624-4-git-send-email-bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-02-22 23:07:38 +03:00
|
|
|
gpio-controller;
|
2011-06-27 11:26:23 +04:00
|
|
|
intel,muxctl = <0>;
|
x86: dtb: Add a device tree for CE4100
History:
v1..v2:
- dropped device_type except for cpu & pci. I have the compatible string
for pci so I can drop the device_type once it is possible
- I lowercased all compatible types. I will need to resend some patches
which have upper case intel
- The cpu had the same compatible string as the soc node. So I added to
the soc node -immr for internel memory mapped registers.
- I added generic names for all parts.
- I reworked the i2c bars matching the way you suggested. I added a
compatible node for the PCI device which only the PCI ids in its
compatible string. The bars (each represents a complete i2c
controller) have a "intel,ce4100-i2c-controller" compatible node. It
is not used by the driver.
The driver is probed via PCI ids (by the pci subsystem not OF) and
matches the bar address against the ressource in the child node. Once
there is a hit the node is attached.
- The SPI driver is also probed via pci. However I also attached a
compatible property based on PCI ids
v2..v3:
- intel,ce4100-immr become intel,ce4100-cp. cp stands for core
peripherals. The Atom data sheet talks here about ACPI devices. Since
we don't have ACPI this does not apply here.
- The interrupt map is gone. There are now plenty of device nodes.
- The "unit address string" got fixed, it uses not DD,V format.
v3..v4:
- added descriptions for compatible nodes introduced here:
- intel,ce4100-ioapic
- intel,ce4100-lapic
- intel,ce4100-hpet
- intel,ce4100
- intel,ce4100-cp
- intel,ce4100-pci
- added a description about I2C controller magic.
- Added gpio-controller and gpio-cells property to gpio devices. Those
properties are not (yet) used.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Cc: sodaville@linutronix.de
Cc: devicetree-discuss@lists.ozlabs.org
LKML-Reference: <1298405266-1624-4-git-send-email-bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-02-22 23:07:38 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c-controller@b,2 {
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
compatible = "pci8086,2e68.2",
|
|
|
|
|
"pci8086,2e68",
|
|
|
|
|
"pciclass,ff0000",
|
|
|
|
|
"pciclass,ff00";
|
|
|
|
|
|
|
|
|
|
reg = <0x15a00 0x0 0x0 0x0 0x0>;
|
|
|
|
|
interrupts = <16 1>;
|
|
|
|
|
ranges = <0 0 0x02000000 0 0xdffe0500 0x100
|
|
|
|
|
1 0 0x02000000 0 0xdffe0600 0x100
|
|
|
|
|
2 0 0x02000000 0 0xdffe0700 0x100>;
|
|
|
|
|
|
|
|
|
|
i2c@0 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "intel,ce4100-i2c-controller";
|
|
|
|
|
reg = <0 0 0x100>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@1 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "intel,ce4100-i2c-controller";
|
|
|
|
|
reg = <1 0 0x100>;
|
|
|
|
|
|
|
|
|
|
gpio@26 {
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
compatible = "ti,pcf8575";
|
|
|
|
|
reg = <0x26>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c@2 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible = "intel,ce4100-i2c-controller";
|
|
|
|
|
reg = <2 0 0x100>;
|
|
|
|
|
|
|
|
|
|
gpio@26 {
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
compatible = "ti,pcf8575";
|
|
|
|
|
reg = <0x26>;
|
|
|
|
|
gpio-controller;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
smard-card@b,3 {
|
|
|
|
|
compatible = "pci8086,2e69.2",
|
|
|
|
|
"pci8086,2e69",
|
|
|
|
|
"pciclass070500",
|
|
|
|
|
"pciclass0705";
|
|
|
|
|
|
|
|
|
|
reg = <0x15b00 0x0 0x0 0x0 0x0>;
|
|
|
|
|
interrupts = <15 1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
spi-controller@b,4 {
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
compatible =
|
|
|
|
|
"pci8086,2e6a.2",
|
|
|
|
|
"pci8086,2e6a",
|
|
|
|
|
"pciclass,ff0000",
|
|
|
|
|
"pciclass,ff00";
|
|
|
|
|
|
|
|
|
|
reg = <0x15c00 0x0 0x0 0x0 0x0>;
|
|
|
|
|
interrupts = <15 1>;
|
|
|
|
|
|
|
|
|
|
dac@0 {
|
|
|
|
|
compatible = "ti,pcm1755";
|
|
|
|
|
reg = <0>;
|
|
|
|
|
spi-max-frequency = <115200>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dac@1 {
|
|
|
|
|
compatible = "ti,pcm1609a";
|
|
|
|
|
reg = <1>;
|
|
|
|
|
spi-max-frequency = <115200>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
eeprom@2 {
|
|
|
|
|
compatible = "atmel,at93c46";
|
|
|
|
|
reg = <2>;
|
|
|
|
|
spi-max-frequency = <115200>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
multimedia@b,7 {
|
|
|
|
|
compatible = "pci8086,2e6d.2",
|
|
|
|
|
"pci8086,2e6d",
|
|
|
|
|
"pciclassff0000",
|
|
|
|
|
"pciclassff00";
|
|
|
|
|
|
|
|
|
|
reg = <0x15f00 0x0 0x0 0x0 0x0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
ethernet@c,0 {
|
|
|
|
|
compatible = "pci8086,2e6e.2",
|
|
|
|
|
"pci8086,2e6e",
|
|
|
|
|
"pciclass020000",
|
|
|
|
|
"pciclass0200";
|
|
|
|
|
|
|
|
|
|
reg = <0x16000 0x0 0x0 0x0 0x0>;
|
|
|
|
|
interrupts = <21 1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
clock@c,1 {
|
|
|
|
|
compatible = "pci8086,2e6f.2",
|
|
|
|
|
"pci8086,2e6f",
|
|
|
|
|
"pciclassff0000",
|
|
|
|
|
"pciclassff00";
|
|
|
|
|
|
|
|
|
|
reg = <0x16100 0x0 0x0 0x0 0x0>;
|
|
|
|
|
interrupts = <3 1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb@d,0 {
|
|
|
|
|
compatible = "pci8086,2e70.2",
|
|
|
|
|
"pci8086,2e70",
|
|
|
|
|
"pciclass0c0320",
|
|
|
|
|
"pciclass0c03";
|
|
|
|
|
|
|
|
|
|
reg = <0x16800 0x0 0x0 0x0 0x0>;
|
2011-04-27 18:30:52 +04:00
|
|
|
interrupts = <22 1>;
|
x86: dtb: Add a device tree for CE4100
History:
v1..v2:
- dropped device_type except for cpu & pci. I have the compatible string
for pci so I can drop the device_type once it is possible
- I lowercased all compatible types. I will need to resend some patches
which have upper case intel
- The cpu had the same compatible string as the soc node. So I added to
the soc node -immr for internel memory mapped registers.
- I added generic names for all parts.
- I reworked the i2c bars matching the way you suggested. I added a
compatible node for the PCI device which only the PCI ids in its
compatible string. The bars (each represents a complete i2c
controller) have a "intel,ce4100-i2c-controller" compatible node. It
is not used by the driver.
The driver is probed via PCI ids (by the pci subsystem not OF) and
matches the bar address against the ressource in the child node. Once
there is a hit the node is attached.
- The SPI driver is also probed via pci. However I also attached a
compatible property based on PCI ids
v2..v3:
- intel,ce4100-immr become intel,ce4100-cp. cp stands for core
peripherals. The Atom data sheet talks here about ACPI devices. Since
we don't have ACPI this does not apply here.
- The interrupt map is gone. There are now plenty of device nodes.
- The "unit address string" got fixed, it uses not DD,V format.
v3..v4:
- added descriptions for compatible nodes introduced here:
- intel,ce4100-ioapic
- intel,ce4100-lapic
- intel,ce4100-hpet
- intel,ce4100
- intel,ce4100-cp
- intel,ce4100-pci
- added a description about I2C controller magic.
- Added gpio-controller and gpio-cells property to gpio devices. Those
properties are not (yet) used.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Cc: sodaville@linutronix.de
Cc: devicetree-discuss@lists.ozlabs.org
LKML-Reference: <1298405266-1624-4-git-send-email-bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-02-22 23:07:38 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb@d,1 {
|
|
|
|
|
compatible = "pci8086,2e70.2",
|
|
|
|
|
"pci8086,2e70",
|
|
|
|
|
"pciclass0c0320",
|
|
|
|
|
"pciclass0c03";
|
|
|
|
|
|
|
|
|
|
reg = <0x16900 0x0 0x0 0x0 0x0>;
|
2011-04-27 18:30:52 +04:00
|
|
|
interrupts = <22 1>;
|
x86: dtb: Add a device tree for CE4100
History:
v1..v2:
- dropped device_type except for cpu & pci. I have the compatible string
for pci so I can drop the device_type once it is possible
- I lowercased all compatible types. I will need to resend some patches
which have upper case intel
- The cpu had the same compatible string as the soc node. So I added to
the soc node -immr for internel memory mapped registers.
- I added generic names for all parts.
- I reworked the i2c bars matching the way you suggested. I added a
compatible node for the PCI device which only the PCI ids in its
compatible string. The bars (each represents a complete i2c
controller) have a "intel,ce4100-i2c-controller" compatible node. It
is not used by the driver.
The driver is probed via PCI ids (by the pci subsystem not OF) and
matches the bar address against the ressource in the child node. Once
there is a hit the node is attached.
- The SPI driver is also probed via pci. However I also attached a
compatible property based on PCI ids
v2..v3:
- intel,ce4100-immr become intel,ce4100-cp. cp stands for core
peripherals. The Atom data sheet talks here about ACPI devices. Since
we don't have ACPI this does not apply here.
- The interrupt map is gone. There are now plenty of device nodes.
- The "unit address string" got fixed, it uses not DD,V format.
v3..v4:
- added descriptions for compatible nodes introduced here:
- intel,ce4100-ioapic
- intel,ce4100-lapic
- intel,ce4100-hpet
- intel,ce4100
- intel,ce4100-cp
- intel,ce4100-pci
- added a description about I2C controller magic.
- Added gpio-controller and gpio-cells property to gpio devices. Those
properties are not (yet) used.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Cc: sodaville@linutronix.de
Cc: devicetree-discuss@lists.ozlabs.org
LKML-Reference: <1298405266-1624-4-git-send-email-bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-02-22 23:07:38 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
sata@e,0 {
|
|
|
|
|
compatible = "pci8086,2e71.0",
|
|
|
|
|
"pci8086,2e71",
|
|
|
|
|
"pciclass010601",
|
|
|
|
|
"pciclass0106";
|
|
|
|
|
|
|
|
|
|
reg = <0x17000 0x0 0x0 0x0 0x0>;
|
2011-04-27 18:30:52 +04:00
|
|
|
interrupts = <23 1>;
|
x86: dtb: Add a device tree for CE4100
History:
v1..v2:
- dropped device_type except for cpu & pci. I have the compatible string
for pci so I can drop the device_type once it is possible
- I lowercased all compatible types. I will need to resend some patches
which have upper case intel
- The cpu had the same compatible string as the soc node. So I added to
the soc node -immr for internel memory mapped registers.
- I added generic names for all parts.
- I reworked the i2c bars matching the way you suggested. I added a
compatible node for the PCI device which only the PCI ids in its
compatible string. The bars (each represents a complete i2c
controller) have a "intel,ce4100-i2c-controller" compatible node. It
is not used by the driver.
The driver is probed via PCI ids (by the pci subsystem not OF) and
matches the bar address against the ressource in the child node. Once
there is a hit the node is attached.
- The SPI driver is also probed via pci. However I also attached a
compatible property based on PCI ids
v2..v3:
- intel,ce4100-immr become intel,ce4100-cp. cp stands for core
peripherals. The Atom data sheet talks here about ACPI devices. Since
we don't have ACPI this does not apply here.
- The interrupt map is gone. There are now plenty of device nodes.
- The "unit address string" got fixed, it uses not DD,V format.
v3..v4:
- added descriptions for compatible nodes introduced here:
- intel,ce4100-ioapic
- intel,ce4100-lapic
- intel,ce4100-hpet
- intel,ce4100
- intel,ce4100-cp
- intel,ce4100-pci
- added a description about I2C controller magic.
- Added gpio-controller and gpio-cells property to gpio devices. Those
properties are not (yet) used.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Cc: sodaville@linutronix.de
Cc: devicetree-discuss@lists.ozlabs.org
LKML-Reference: <1298405266-1624-4-git-send-email-bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-02-22 23:07:38 +03:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
flash@f,0 {
|
|
|
|
|
compatible = "pci8086,701.1",
|
|
|
|
|
"pci8086,701",
|
|
|
|
|
"pciclass050100",
|
|
|
|
|
"pciclass0501";
|
|
|
|
|
|
|
|
|
|
reg = <0x17800 0x0 0x0 0x0 0x0>;
|
|
|
|
|
interrupts = <13 1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
entertainment-encryption@10,0 {
|
|
|
|
|
compatible = "pci8086,702.1",
|
|
|
|
|
"pci8086,702",
|
|
|
|
|
"pciclass101000",
|
|
|
|
|
"pciclass1010";
|
|
|
|
|
|
|
|
|
|
reg = <0x18000 0x0 0x0 0x0 0x0>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
co-processor@11,0 {
|
|
|
|
|
compatible = "pci8086,703.1",
|
|
|
|
|
"pci8086,703",
|
|
|
|
|
"pciclass0b4000",
|
|
|
|
|
"pciclass0b40";
|
|
|
|
|
|
|
|
|
|
reg = <0x18800 0x0 0x0 0x0 0x0>;
|
|
|
|
|
interrupts = <1 1>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
multimedia@12,0 {
|
|
|
|
|
compatible = "pci8086,704.0",
|
|
|
|
|
"pci8086,704",
|
|
|
|
|
"pciclass048000",
|
|
|
|
|
"pciclass0480";
|
|
|
|
|
|
|
|
|
|
reg = <0x19000 0x0 0x0 0x0 0x0>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
isa@1f,0 {
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
compatible = "isa";
|
2011-04-07 16:13:15 +04:00
|
|
|
reg = <0xf800 0x0 0x0 0x0 0x0>;
|
x86: dtb: Add a device tree for CE4100
History:
v1..v2:
- dropped device_type except for cpu & pci. I have the compatible string
for pci so I can drop the device_type once it is possible
- I lowercased all compatible types. I will need to resend some patches
which have upper case intel
- The cpu had the same compatible string as the soc node. So I added to
the soc node -immr for internel memory mapped registers.
- I added generic names for all parts.
- I reworked the i2c bars matching the way you suggested. I added a
compatible node for the PCI device which only the PCI ids in its
compatible string. The bars (each represents a complete i2c
controller) have a "intel,ce4100-i2c-controller" compatible node. It
is not used by the driver.
The driver is probed via PCI ids (by the pci subsystem not OF) and
matches the bar address against the ressource in the child node. Once
there is a hit the node is attached.
- The SPI driver is also probed via pci. However I also attached a
compatible property based on PCI ids
v2..v3:
- intel,ce4100-immr become intel,ce4100-cp. cp stands for core
peripherals. The Atom data sheet talks here about ACPI devices. Since
we don't have ACPI this does not apply here.
- The interrupt map is gone. There are now plenty of device nodes.
- The "unit address string" got fixed, it uses not DD,V format.
v3..v4:
- added descriptions for compatible nodes introduced here:
- intel,ce4100-ioapic
- intel,ce4100-lapic
- intel,ce4100-hpet
- intel,ce4100
- intel,ce4100-cp
- intel,ce4100-pci
- added a description about I2C controller magic.
- Added gpio-controller and gpio-cells property to gpio devices. Those
properties are not (yet) used.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Cc: sodaville@linutronix.de
Cc: devicetree-discuss@lists.ozlabs.org
LKML-Reference: <1298405266-1624-4-git-send-email-bigeasy@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2011-02-22 23:07:38 +03:00
|
|
|
ranges = <1 0 0 0 0 0x100>;
|
|
|
|
|
|
|
|
|
|
rtc@70 {
|
|
|
|
|
compatible = "intel,ce4100-rtc", "motorola,mc146818";
|
|
|
|
|
interrupts = <8 3>;
|
|
|
|
|
interrupt-parent = <&ioapic1>;
|
|
|
|
|
ctrl-reg = <2>;
|
|
|
|
|
freq-reg = <0x26>;
|
|
|
|
|
reg = <1 0x70 2>;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
};
|