2019-01-21 21:05:50 +03:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2009-07-01 05:29:36 +04:00
|
|
|
/*
|
|
|
|
* Driver for Broadcom 63xx SOCs integrated PHYs
|
|
|
|
*/
|
2015-10-06 22:25:48 +03:00
|
|
|
#include "bcm-phy-lib.h"
|
2009-07-01 05:29:36 +04:00
|
|
|
#include <linux/module.h>
|
|
|
|
#include <linux/phy.h>
|
|
|
|
|
|
|
|
#define MII_BCM63XX_IR 0x1a /* interrupt register */
|
|
|
|
#define MII_BCM63XX_IR_EN 0x4000 /* global interrupt enable */
|
|
|
|
#define MII_BCM63XX_IR_DUPLEX 0x0800 /* duplex changed */
|
|
|
|
#define MII_BCM63XX_IR_SPEED 0x0400 /* speed changed */
|
|
|
|
#define MII_BCM63XX_IR_LINK 0x0200 /* link changed */
|
|
|
|
#define MII_BCM63XX_IR_GMASK 0x0100 /* global interrupt mask */
|
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Broadcom 63xx internal PHY driver");
|
|
|
|
MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|
2017-01-18 03:26:55 +03:00
|
|
|
static int bcm63xx_config_intr(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
int reg, err;
|
|
|
|
|
|
|
|
reg = phy_read(phydev, MII_BCM63XX_IR);
|
|
|
|
if (reg < 0)
|
|
|
|
return reg;
|
|
|
|
|
|
|
|
if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
|
|
|
|
reg &= ~MII_BCM63XX_IR_GMASK;
|
|
|
|
else
|
|
|
|
reg |= MII_BCM63XX_IR_GMASK;
|
|
|
|
|
|
|
|
err = phy_write(phydev, MII_BCM63XX_IR, reg);
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
2009-07-01 05:29:36 +04:00
|
|
|
static int bcm63xx_config_init(struct phy_device *phydev)
|
|
|
|
{
|
|
|
|
int reg, err;
|
|
|
|
|
2018-09-30 00:04:16 +03:00
|
|
|
/* ASYM_PAUSE bit is marked RO in datasheet, so don't cheat */
|
2018-11-11 01:43:33 +03:00
|
|
|
linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
|
2018-09-30 00:04:16 +03:00
|
|
|
|
2009-07-01 05:29:36 +04:00
|
|
|
reg = phy_read(phydev, MII_BCM63XX_IR);
|
|
|
|
if (reg < 0)
|
|
|
|
return reg;
|
|
|
|
|
|
|
|
/* Mask interrupts globally. */
|
|
|
|
reg |= MII_BCM63XX_IR_GMASK;
|
|
|
|
err = phy_write(phydev, MII_BCM63XX_IR, reg);
|
|
|
|
if (err < 0)
|
|
|
|
return err;
|
|
|
|
|
|
|
|
/* Unmask events we are interested in */
|
|
|
|
reg = ~(MII_BCM63XX_IR_DUPLEX |
|
|
|
|
MII_BCM63XX_IR_SPEED |
|
|
|
|
MII_BCM63XX_IR_LINK) |
|
|
|
|
MII_BCM63XX_IR_EN;
|
2012-04-02 10:24:55 +04:00
|
|
|
return phy_write(phydev, MII_BCM63XX_IR, reg);
|
2009-07-01 05:29:36 +04:00
|
|
|
}
|
|
|
|
|
2012-07-04 09:44:34 +04:00
|
|
|
static struct phy_driver bcm63xx_driver[] = {
|
|
|
|
{
|
2009-07-01 05:29:36 +04:00
|
|
|
.phy_id = 0x00406000,
|
|
|
|
.phy_id_mask = 0xfffffc00,
|
|
|
|
.name = "Broadcom BCM63XX (1)",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_BASIC_FEATURES */
|
2018-11-09 20:17:22 +03:00
|
|
|
.flags = PHY_IS_INTERNAL,
|
2009-07-01 05:29:36 +04:00
|
|
|
.config_init = bcm63xx_config_init,
|
2015-10-06 22:25:48 +03:00
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
2017-01-18 03:26:55 +03:00
|
|
|
.config_intr = bcm63xx_config_intr,
|
2012-07-04 09:44:34 +04:00
|
|
|
}, {
|
|
|
|
/* same phy as above, with just a different OUI */
|
2009-07-01 05:29:36 +04:00
|
|
|
.phy_id = 0x002bdc00,
|
|
|
|
.phy_id_mask = 0xfffffc00,
|
2020-03-02 22:46:57 +03:00
|
|
|
.name = "Broadcom BCM63XX (2)",
|
2019-04-12 21:47:03 +03:00
|
|
|
/* PHY_BASIC_FEATURES */
|
2018-11-09 20:17:22 +03:00
|
|
|
.flags = PHY_IS_INTERNAL,
|
2009-07-01 05:29:36 +04:00
|
|
|
.config_init = bcm63xx_config_init,
|
2015-10-06 22:25:48 +03:00
|
|
|
.ack_interrupt = bcm_phy_ack_intr,
|
2017-01-18 03:26:55 +03:00
|
|
|
.config_intr = bcm63xx_config_intr,
|
2012-07-04 09:44:34 +04:00
|
|
|
} };
|
2009-07-01 05:29:36 +04:00
|
|
|
|
2014-11-11 21:45:59 +03:00
|
|
|
module_phy_driver(bcm63xx_driver);
|
2010-04-02 05:05:56 +04:00
|
|
|
|
2010-10-04 03:43:32 +04:00
|
|
|
static struct mdio_device_id __maybe_unused bcm63xx_tbl[] = {
|
2010-04-02 05:05:56 +04:00
|
|
|
{ 0x00406000, 0xfffffc00 },
|
|
|
|
{ 0x002bdc00, 0xfffffc00 },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
2010-04-09 05:04:45 +04:00
|
|
|
MODULE_DEVICE_TABLE(mdio, bcm63xx_tbl);
|