2019-06-04 11:11:33 +03:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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2005-04-17 02:20:36 +04:00
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/*
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* linux/arch/arm/lib/delay.S
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*
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* Copyright (C) 1995, 1996 Russell King
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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2012-07-06 18:47:17 +04:00
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#include <asm/delay.h>
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2015-02-26 00:50:39 +03:00
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2005-04-17 02:20:36 +04:00
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.text
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2005-11-12 00:51:49 +03:00
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.LC0: .word loops_per_jiffy
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2012-07-06 18:47:17 +04:00
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.LC1: .word UDELAY_MULT
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2005-04-17 02:20:36 +04:00
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/*
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2016-10-07 07:38:35 +03:00
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* loops = r0 * HZ * loops_per_jiffy / 1000000
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*
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2006-03-20 20:10:09 +03:00
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* r0 <= 2000
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* HZ <= 1000
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2005-04-17 02:20:36 +04:00
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*/
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2006-03-20 20:10:09 +03:00
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2012-07-06 18:47:17 +04:00
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ENTRY(__loop_udelay)
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2006-03-20 20:10:09 +03:00
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ldr r2, .LC1
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2016-10-07 07:38:35 +03:00
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mul r0, r2, r0 @ r0 = delay_us * UDELAY_MULT
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ENTRY(__loop_const_udelay) @ 0 <= r0 <= 0xfffffaf0
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2005-11-12 00:51:49 +03:00
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ldr r2, .LC0
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2015-02-26 00:50:39 +03:00
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ldr r2, [r2]
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2016-10-07 07:38:35 +03:00
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umull r1, r0, r2, r0 @ r0-r1 = r0 * loops_per_jiffy
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adds r1, r1, #0xffffffff @ rounding up ...
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adcs r0, r0, r0 @ and right shift by 31
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2014-06-30 19:29:12 +04:00
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reteq lr
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2005-04-17 02:20:36 +04:00
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ARM: 7907/1: lib: delay-loop: Add align directive to fix BogoMIPS calculation
Currently mx53 (CortexA8) running at 1GHz reports:
Calibrating delay loop... 663.55 BogoMIPS (lpj=3317760)
Tom Evans verified that alignments of 0x0 and 0x8 run the two instructions of __loop_delay in one clock cycle (1 clock/loop), while alignments of 0x4 and 0xc take 3 clocks to run the loop twice. (1.5 clock/loop)
The original object code looks like this:
00000010 <__loop_const_udelay>:
10: e3e01000 mvn r1, #0
14: e51f201c ldr r2, [pc, #-28] ; 0 <__loop_udelay-0x8>
18: e5922000 ldr r2, [r2]
1c: e0800921 add r0, r0, r1, lsr #18
20: e1a00720 lsr r0, r0, #14
24: e0822b21 add r2, r2, r1, lsr #22
28: e1a02522 lsr r2, r2, #10
2c: e0000092 mul r0, r2, r0
30: e0800d21 add r0, r0, r1, lsr #26
34: e1b00320 lsrs r0, r0, #6
38: 01a0f00e moveq pc, lr
0000003c <__loop_delay>:
3c: e2500001 subs r0, r0, #1
40: 8afffffe bhi 3c <__loop_delay>
44: e1a0f00e mov pc, lr
After adding the 'align 3' directive to __loop_delay (align to 8 bytes):
00000010 <__loop_const_udelay>:
10: e3e01000 mvn r1, #0
14: e51f201c ldr r2, [pc, #-28] ; 0 <__loop_udelay-0x8>
18: e5922000 ldr r2, [r2]
1c: e0800921 add r0, r0, r1, lsr #18
20: e1a00720 lsr r0, r0, #14
24: e0822b21 add r2, r2, r1, lsr #22
28: e1a02522 lsr r2, r2, #10
2c: e0000092 mul r0, r2, r0
30: e0800d21 add r0, r0, r1, lsr #26
34: e1b00320 lsrs r0, r0, #6
38: 01a0f00e moveq pc, lr
3c: e320f000 nop {0}
00000040 <__loop_delay>:
40: e2500001 subs r0, r0, #1
44: 8afffffe bhi 40 <__loop_delay>
48: e1a0f00e mov pc, lr
4c: e320f000 nop {0}
, which now reports:
Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
Some more test results:
On mx31 (ARM1136) running at 532 MHz, before the patch:
Calibrating delay loop... 351.43 BogoMIPS (lpj=1757184)
On mx31 (ARM1136) running at 532 MHz after the patch:
Calibrating delay loop... 528.79 BogoMIPS (lpj=2643968)
Also tested on mx6 (CortexA9) and on mx27 (ARM926), which shows the same
BogoMIPS value before and after this patch.
Reported-by: Tom Evans <tom_usenet@optusnet.com.au>
Suggested-by: Tom Evans <tom_usenet@optusnet.com.au>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2013-11-30 18:24:42 +04:00
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.align 3
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2005-04-17 02:20:36 +04:00
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@ Delay routine
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2012-07-06 18:47:17 +04:00
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ENTRY(__loop_delay)
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2005-04-17 02:20:36 +04:00
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subs r0, r0, #1
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#if 0
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2014-06-30 19:29:12 +04:00
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retls lr
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2005-04-17 02:20:36 +04:00
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subs r0, r0, #1
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2014-06-30 19:29:12 +04:00
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retls lr
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2005-04-17 02:20:36 +04:00
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subs r0, r0, #1
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2014-06-30 19:29:12 +04:00
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retls lr
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2005-04-17 02:20:36 +04:00
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subs r0, r0, #1
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2014-06-30 19:29:12 +04:00
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retls lr
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2005-04-17 02:20:36 +04:00
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subs r0, r0, #1
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2014-06-30 19:29:12 +04:00
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retls lr
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2005-04-17 02:20:36 +04:00
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subs r0, r0, #1
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2014-06-30 19:29:12 +04:00
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retls lr
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2005-04-17 02:20:36 +04:00
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subs r0, r0, #1
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2014-06-30 19:29:12 +04:00
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retls lr
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2005-04-17 02:20:36 +04:00
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subs r0, r0, #1
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#endif
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2012-07-06 18:47:17 +04:00
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bhi __loop_delay
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2014-06-30 19:29:12 +04:00
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ret lr
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2012-07-06 18:47:17 +04:00
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ENDPROC(__loop_udelay)
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ENDPROC(__loop_const_udelay)
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ENDPROC(__loop_delay)
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