2014-12-12 18:07:46 +03:00
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/*
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* Rockchip usb PHY driver
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*
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* Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
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* Copyright (C) 2014 ROCKCHIP, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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2015-11-20 00:22:26 +03:00
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#include <linux/clk-provider.h>
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2014-12-12 18:07:46 +03:00
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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2015-11-20 00:22:26 +03:00
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#include <linux/of_platform.h>
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2014-12-12 18:07:46 +03:00
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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/*
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* The higher 16-bit of this register is used for write protection
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* only if BIT(13 + 16) set to 1 the BIT(13) can be written.
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*/
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#define SIDDQ_WRITE_ENA BIT(29)
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#define SIDDQ_ON BIT(13)
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#define SIDDQ_OFF (0 << 13)
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2015-11-20 00:22:26 +03:00
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struct rockchip_usb_phys {
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int reg;
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const char *pll_name;
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};
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struct rockchip_usb_phy_pdata {
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struct rockchip_usb_phys *phys;
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};
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2015-11-20 00:22:23 +03:00
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struct rockchip_usb_phy_base {
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struct device *dev;
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struct regmap *reg_base;
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2015-11-20 00:22:26 +03:00
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const struct rockchip_usb_phy_pdata *pdata;
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2015-11-20 00:22:23 +03:00
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};
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2014-12-12 18:07:46 +03:00
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struct rockchip_usb_phy {
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2015-11-20 00:22:23 +03:00
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struct rockchip_usb_phy_base *base;
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2015-11-20 00:22:26 +03:00
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struct device_node *np;
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2014-12-12 18:07:46 +03:00
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unsigned int reg_offset;
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struct clk *clk;
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2015-11-20 00:22:26 +03:00
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struct clk *clk480m;
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struct clk_hw clk480m_hw;
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2014-12-12 18:07:46 +03:00
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struct phy *phy;
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};
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static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
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bool siddq)
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{
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2015-11-20 00:22:23 +03:00
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return regmap_write(phy->base->reg_base, phy->reg_offset,
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2014-12-12 18:07:46 +03:00
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SIDDQ_WRITE_ENA | (siddq ? SIDDQ_ON : SIDDQ_OFF));
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}
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2015-11-20 00:22:26 +03:00
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static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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2014-12-12 18:07:46 +03:00
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{
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2015-11-20 00:22:26 +03:00
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return 480000000;
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}
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static void rockchip_usb_phy480m_disable(struct clk_hw *hw)
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{
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struct rockchip_usb_phy *phy = container_of(hw,
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struct rockchip_usb_phy,
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clk480m_hw);
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2014-12-12 18:07:46 +03:00
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/* Power down usb phy analog blocks by set siddq 1 */
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2015-11-20 00:22:26 +03:00
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rockchip_usb_phy_power(phy, 1);
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}
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static int rockchip_usb_phy480m_enable(struct clk_hw *hw)
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{
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struct rockchip_usb_phy *phy = container_of(hw,
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struct rockchip_usb_phy,
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clk480m_hw);
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/* Power up usb phy analog blocks by set siddq 0 */
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return rockchip_usb_phy_power(phy, 0);
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}
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static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
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{
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struct rockchip_usb_phy *phy = container_of(hw,
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struct rockchip_usb_phy,
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clk480m_hw);
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int ret;
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u32 val;
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ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);
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if (ret < 0)
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2014-12-12 18:07:46 +03:00
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return ret;
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2015-11-20 00:22:26 +03:00
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return (val & SIDDQ_ON) ? 0 : 1;
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}
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static const struct clk_ops rockchip_usb_phy480m_ops = {
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.enable = rockchip_usb_phy480m_enable,
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.disable = rockchip_usb_phy480m_disable,
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.is_enabled = rockchip_usb_phy480m_is_enabled,
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.recalc_rate = rockchip_usb_phy480m_recalc_rate,
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};
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static int rockchip_usb_phy_power_off(struct phy *_phy)
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{
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struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
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clk_disable_unprepare(phy->clk480m);
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2014-12-12 18:07:46 +03:00
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return 0;
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}
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static int rockchip_usb_phy_power_on(struct phy *_phy)
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{
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struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
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2015-11-20 00:22:26 +03:00
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return clk_prepare_enable(phy->clk480m);
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2014-12-12 18:07:46 +03:00
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}
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2015-07-15 10:33:51 +03:00
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static const struct phy_ops ops = {
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2014-12-12 18:07:46 +03:00
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.power_on = rockchip_usb_phy_power_on,
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.power_off = rockchip_usb_phy_power_off,
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.owner = THIS_MODULE,
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};
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2015-11-20 00:22:22 +03:00
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static void rockchip_usb_phy_action(void *data)
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{
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struct rockchip_usb_phy *rk_phy = data;
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2015-11-20 00:22:26 +03:00
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of_clk_del_provider(rk_phy->np);
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clk_unregister(rk_phy->clk480m);
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2015-11-20 00:22:22 +03:00
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if (rk_phy->clk)
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clk_put(rk_phy->clk);
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}
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2015-11-20 00:22:24 +03:00
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static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
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struct device_node *child)
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{
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struct rockchip_usb_phy *rk_phy;
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unsigned int reg_offset;
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2015-11-20 00:22:26 +03:00
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const char *clk_name;
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struct clk_init_data init;
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int err, i;
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2015-11-20 00:22:24 +03:00
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rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
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if (!rk_phy)
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return -ENOMEM;
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rk_phy->base = base;
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2015-11-20 00:22:26 +03:00
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rk_phy->np = child;
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2015-11-20 00:22:24 +03:00
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if (of_property_read_u32(child, "reg", ®_offset)) {
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dev_err(base->dev, "missing reg property in node %s\n",
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child->name);
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return -EINVAL;
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}
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rk_phy->reg_offset = reg_offset;
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rk_phy->clk = of_clk_get_by_name(child, "phyclk");
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if (IS_ERR(rk_phy->clk))
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rk_phy->clk = NULL;
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2015-11-20 00:22:26 +03:00
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i = 0;
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init.name = NULL;
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while (base->pdata->phys[i].reg) {
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if (base->pdata->phys[i].reg == reg_offset) {
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init.name = base->pdata->phys[i].pll_name;
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break;
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}
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i++;
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}
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if (!init.name) {
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dev_err(base->dev, "phy data not found\n");
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return -EINVAL;
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}
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if (rk_phy->clk) {
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clk_name = __clk_get_name(rk_phy->clk);
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init.flags = 0;
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init.parent_names = &clk_name;
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init.num_parents = 1;
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} else {
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init.flags = CLK_IS_ROOT;
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init.parent_names = NULL;
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init.num_parents = 0;
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}
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init.ops = &rockchip_usb_phy480m_ops;
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rk_phy->clk480m_hw.init = &init;
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rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
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if (IS_ERR(rk_phy->clk480m)) {
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err = PTR_ERR(rk_phy->clk480m);
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goto err_clk;
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}
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err = of_clk_add_provider(child, of_clk_src_simple_get,
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rk_phy->clk480m);
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if (err < 0)
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goto err_clk_prov;
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err = devm_add_action(base->dev, rockchip_usb_phy_action, rk_phy);
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if (err)
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goto err_devm_action;
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2015-11-20 00:22:24 +03:00
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rk_phy->phy = devm_phy_create(base->dev, child, &ops);
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if (IS_ERR(rk_phy->phy)) {
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dev_err(base->dev, "failed to create PHY\n");
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return PTR_ERR(rk_phy->phy);
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}
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phy_set_drvdata(rk_phy->phy, rk_phy);
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/* only power up usb phy when it use, so disable it when init*/
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return rockchip_usb_phy_power(rk_phy, 1);
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2015-11-20 00:22:26 +03:00
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err_devm_action:
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of_clk_del_provider(child);
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err_clk_prov:
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clk_unregister(rk_phy->clk480m);
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err_clk:
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if (rk_phy->clk)
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clk_put(rk_phy->clk);
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return err;
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2015-11-20 00:22:24 +03:00
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}
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2015-11-20 00:22:26 +03:00
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static const struct rockchip_usb_phy_pdata rk3066a_pdata = {
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.phys = (struct rockchip_usb_phys[]){
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{ .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" },
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{ .reg = 0x188, .pll_name = "sclk_otgphy1_480m" },
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{ /* sentinel */ }
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},
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};
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static const struct rockchip_usb_phy_pdata rk3188_pdata = {
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.phys = (struct rockchip_usb_phys[]){
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{ .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" },
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{ .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" },
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{ /* sentinel */ }
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},
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};
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static const struct rockchip_usb_phy_pdata rk3288_pdata = {
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.phys = (struct rockchip_usb_phys[]){
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{ .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
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{ .reg = 0x334, .pll_name = "sclk_otgphy1_480m" },
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{ .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
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{ /* sentinel */ }
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},
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};
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2014-12-12 18:07:46 +03:00
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static int rockchip_usb_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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2015-11-20 00:22:23 +03:00
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struct rockchip_usb_phy_base *phy_base;
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2014-12-12 18:07:46 +03:00
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struct phy_provider *phy_provider;
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2015-11-20 00:22:26 +03:00
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const struct of_device_id *match;
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2014-12-12 18:07:46 +03:00
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struct device_node *child;
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2015-07-17 10:29:25 +03:00
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int err;
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2014-12-12 18:07:46 +03:00
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2015-11-20 00:22:23 +03:00
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phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL);
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if (!phy_base)
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return -ENOMEM;
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2015-11-20 00:22:26 +03:00
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match = of_match_device(dev->driver->of_match_table, dev);
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if (!match || !match->data) {
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dev_err(dev, "missing phy data\n");
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return -EINVAL;
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}
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phy_base->pdata = match->data;
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2015-11-20 00:22:23 +03:00
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phy_base->dev = dev;
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phy_base->reg_base = syscon_regmap_lookup_by_phandle(dev->of_node,
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"rockchip,grf");
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if (IS_ERR(phy_base->reg_base)) {
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2014-12-12 18:07:46 +03:00
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dev_err(&pdev->dev, "Missing rockchip,grf property\n");
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2015-11-20 00:22:23 +03:00
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return PTR_ERR(phy_base->reg_base);
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2014-12-12 18:07:46 +03:00
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}
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for_each_available_child_of_node(dev->of_node, child) {
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2015-11-20 00:22:24 +03:00
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err = rockchip_usb_phy_init(phy_base, child);
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if (err) {
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of_node_put(child);
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2015-11-20 00:22:22 +03:00
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return err;
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2014-12-12 18:07:46 +03:00
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}
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}
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id rockchip_usb_phy_dt_ids[] = {
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2015-11-20 00:22:26 +03:00
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{ .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
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{ .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata },
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{ .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
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2014-12-12 18:07:46 +03:00
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{}
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};
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MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids);
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static struct platform_driver rockchip_usb_driver = {
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.probe = rockchip_usb_phy_probe,
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.driver = {
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.name = "rockchip-usb-phy",
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.of_match_table = rockchip_usb_phy_dt_ids,
|
|
|
|
},
|
|
|
|
};
|
|
|
|
|
|
|
|
module_platform_driver(rockchip_usb_driver);
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
|
|
|
|
MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
|
|
|
|
MODULE_LICENSE("GPL v2");
|