2012-05-10 18:16:00 +04:00
|
|
|
/*
|
|
|
|
|
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
|
|
|
|
*
|
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
|
|
|
* published by the Free Software Foundation.
|
|
|
|
|
* Based on "omap4.dtsi"
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/include/ "skeleton.dtsi"
|
|
|
|
|
|
|
|
|
|
/ {
|
2013-02-12 14:27:55 +04:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
|
2012-05-10 18:16:00 +04:00
|
|
|
compatible = "ti,omap5";
|
|
|
|
|
interrupt-parent = <&gic>;
|
|
|
|
|
|
|
|
|
|
aliases {
|
|
|
|
|
serial0 = &uart1;
|
|
|
|
|
serial1 = &uart2;
|
|
|
|
|
serial2 = &uart3;
|
|
|
|
|
serial3 = &uart4;
|
|
|
|
|
serial4 = &uart5;
|
|
|
|
|
serial5 = &uart6;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
cpus {
|
|
|
|
|
cpu@0 {
|
|
|
|
|
compatible = "arm,cortex-a15";
|
|
|
|
|
};
|
|
|
|
|
cpu@1 {
|
|
|
|
|
compatible = "arm,cortex-a15";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-02-10 20:10:19 +04:00
|
|
|
timer {
|
|
|
|
|
compatible = "arm,armv7-timer";
|
2013-01-18 18:23:00 +04:00
|
|
|
/* PPI secure/nonsecure IRQ, active low level-sensitive */
|
|
|
|
|
interrupts = <1 13 0x308>,
|
2013-02-19 15:59:24 +04:00
|
|
|
<1 14 0x308>,
|
|
|
|
|
<1 11 0x308>,
|
|
|
|
|
<1 10 0x308>;
|
2013-02-10 20:10:19 +04:00
|
|
|
clock-frequency = <6144000>;
|
|
|
|
|
};
|
|
|
|
|
|
2013-02-12 14:27:55 +04:00
|
|
|
gic: interrupt-controller@48211000 {
|
|
|
|
|
compatible = "arm,cortex-a15-gic";
|
|
|
|
|
interrupt-controller;
|
|
|
|
|
#interrupt-cells = <3>;
|
|
|
|
|
reg = <0x48211000 0x1000>,
|
2013-02-19 15:59:24 +04:00
|
|
|
<0x48212000 0x1000>,
|
|
|
|
|
<0x48214000 0x2000>,
|
|
|
|
|
<0x48216000 0x2000>;
|
2013-02-12 14:27:55 +04:00
|
|
|
};
|
|
|
|
|
|
2012-05-10 18:16:00 +04:00
|
|
|
/*
|
|
|
|
|
* The soc node represents the soc top level view. It is uses for IPs
|
|
|
|
|
* that are not memory mapped in the MPU view or for the MPU itself.
|
|
|
|
|
*/
|
|
|
|
|
soc {
|
|
|
|
|
compatible = "ti,omap-infra";
|
|
|
|
|
mpu {
|
|
|
|
|
compatible = "ti,omap5-mpu";
|
|
|
|
|
ti,hwmods = "mpu";
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* XXX: Use a flat representation of the OMAP3 interconnect.
|
|
|
|
|
* The real OMAP interconnect network is quite complex.
|
|
|
|
|
* Since that will not bring real advantage to represent that in DT for
|
|
|
|
|
* the moment, just use a fake OCP bus entry to represent the whole bus
|
|
|
|
|
* hierarchy.
|
|
|
|
|
*/
|
|
|
|
|
ocp {
|
|
|
|
|
compatible = "ti,omap4-l3-noc", "simple-bus";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges;
|
|
|
|
|
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
2013-02-26 16:06:14 +04:00
|
|
|
reg = <0x44000000 0x2000>,
|
|
|
|
|
<0x44800000 0x3000>,
|
|
|
|
|
<0x45000000 0x4000>;
|
|
|
|
|
interrupts = <0 9 0x4>,
|
|
|
|
|
<0 10 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
|
2012-11-01 18:12:23 +04:00
|
|
|
counter32k: counter@4ae04000 {
|
|
|
|
|
compatible = "ti,omap-counter32k";
|
|
|
|
|
reg = <0x4ae04000 0x40>;
|
|
|
|
|
ti,hwmods = "counter_32k";
|
|
|
|
|
};
|
|
|
|
|
|
2012-10-04 15:57:27 +04:00
|
|
|
omap5_pmx_core: pinmux@4a002840 {
|
|
|
|
|
compatible = "ti,omap4-padconf", "pinctrl-single";
|
|
|
|
|
reg = <0x4a002840 0x01b6>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
pinctrl-single,register-width = <16>;
|
|
|
|
|
pinctrl-single,function-mask = <0x7fff>;
|
|
|
|
|
};
|
|
|
|
|
omap5_pmx_wkup: pinmux@4ae0c840 {
|
|
|
|
|
compatible = "ti,omap4-padconf", "pinctrl-single";
|
|
|
|
|
reg = <0x4ae0c840 0x0038>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
pinctrl-single,register-width = <16>;
|
|
|
|
|
pinctrl-single,function-mask = <0x7fff>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-04-26 22:47:59 +04:00
|
|
|
sdma: dma-controller@4a056000 {
|
|
|
|
|
compatible = "ti,omap4430-sdma";
|
|
|
|
|
reg = <0x4a056000 0x1000>;
|
|
|
|
|
interrupts = <0 12 0x4>,
|
|
|
|
|
<0 13 0x4>,
|
|
|
|
|
<0 14 0x4>,
|
|
|
|
|
<0 15 0x4>;
|
|
|
|
|
#dma-cells = <1>;
|
|
|
|
|
#dma-channels = <32>;
|
|
|
|
|
#dma-requests = <127>;
|
|
|
|
|
};
|
|
|
|
|
|
2012-05-10 18:16:00 +04:00
|
|
|
gpio1: gpio@4ae10000 {
|
|
|
|
|
compatible = "ti,omap4-gpio";
|
2012-10-23 12:37:09 +04:00
|
|
|
reg = <0x4ae10000 0x200>;
|
|
|
|
|
interrupts = <0 29 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
ti,hwmods = "gpio1";
|
2013-04-05 00:16:16 +04:00
|
|
|
ti,gpio-always-on;
|
2012-05-10 18:16:00 +04:00
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
2013-03-08 01:44:39 +04:00
|
|
|
#interrupt-cells = <2>;
|
2012-05-10 18:16:00 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio2: gpio@48055000 {
|
|
|
|
|
compatible = "ti,omap4-gpio";
|
2012-10-23 12:37:09 +04:00
|
|
|
reg = <0x48055000 0x200>;
|
|
|
|
|
interrupts = <0 30 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
ti,hwmods = "gpio2";
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
2013-03-08 01:44:39 +04:00
|
|
|
#interrupt-cells = <2>;
|
2012-05-10 18:16:00 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio3: gpio@48057000 {
|
|
|
|
|
compatible = "ti,omap4-gpio";
|
2012-10-23 12:37:09 +04:00
|
|
|
reg = <0x48057000 0x200>;
|
|
|
|
|
interrupts = <0 31 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
ti,hwmods = "gpio3";
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
2013-03-08 01:44:39 +04:00
|
|
|
#interrupt-cells = <2>;
|
2012-05-10 18:16:00 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio4: gpio@48059000 {
|
|
|
|
|
compatible = "ti,omap4-gpio";
|
2012-10-23 12:37:09 +04:00
|
|
|
reg = <0x48059000 0x200>;
|
|
|
|
|
interrupts = <0 32 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
ti,hwmods = "gpio4";
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
2013-03-08 01:44:39 +04:00
|
|
|
#interrupt-cells = <2>;
|
2012-05-10 18:16:00 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio5: gpio@4805b000 {
|
|
|
|
|
compatible = "ti,omap4-gpio";
|
2012-10-23 12:37:09 +04:00
|
|
|
reg = <0x4805b000 0x200>;
|
|
|
|
|
interrupts = <0 33 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
ti,hwmods = "gpio5";
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
2013-03-08 01:44:39 +04:00
|
|
|
#interrupt-cells = <2>;
|
2012-05-10 18:16:00 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio6: gpio@4805d000 {
|
|
|
|
|
compatible = "ti,omap4-gpio";
|
2012-10-23 12:37:09 +04:00
|
|
|
reg = <0x4805d000 0x200>;
|
|
|
|
|
interrupts = <0 34 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
ti,hwmods = "gpio6";
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
2013-03-08 01:44:39 +04:00
|
|
|
#interrupt-cells = <2>;
|
2012-05-10 18:16:00 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio7: gpio@48051000 {
|
|
|
|
|
compatible = "ti,omap4-gpio";
|
2012-10-23 12:37:09 +04:00
|
|
|
reg = <0x48051000 0x200>;
|
|
|
|
|
interrupts = <0 35 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
ti,hwmods = "gpio7";
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
2013-03-08 01:44:39 +04:00
|
|
|
#interrupt-cells = <2>;
|
2012-05-10 18:16:00 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
gpio8: gpio@48053000 {
|
|
|
|
|
compatible = "ti,omap4-gpio";
|
2012-10-23 12:37:09 +04:00
|
|
|
reg = <0x48053000 0x200>;
|
|
|
|
|
interrupts = <0 121 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
ti,hwmods = "gpio8";
|
|
|
|
|
gpio-controller;
|
|
|
|
|
#gpio-cells = <2>;
|
|
|
|
|
interrupt-controller;
|
2013-03-08 01:44:39 +04:00
|
|
|
#interrupt-cells = <2>;
|
2012-05-10 18:16:00 +04:00
|
|
|
};
|
|
|
|
|
|
2013-02-23 01:33:31 +04:00
|
|
|
gpmc: gpmc@50000000 {
|
|
|
|
|
compatible = "ti,omap4430-gpmc";
|
|
|
|
|
reg = <0x50000000 0x1000>;
|
|
|
|
|
#address-cells = <2>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
interrupts = <0 20 0x4>;
|
|
|
|
|
gpmc,num-cs = <8>;
|
|
|
|
|
gpmc,num-waitpins = <4>;
|
|
|
|
|
ti,hwmods = "gpmc";
|
|
|
|
|
};
|
|
|
|
|
|
2012-07-25 09:27:58 +04:00
|
|
|
i2c1: i2c@48070000 {
|
|
|
|
|
compatible = "ti,omap4-i2c";
|
2012-10-23 12:37:10 +04:00
|
|
|
reg = <0x48070000 0x100>;
|
|
|
|
|
interrupts = <0 56 0x4>;
|
2012-07-25 09:27:58 +04:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "i2c1";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c2: i2c@48072000 {
|
|
|
|
|
compatible = "ti,omap4-i2c";
|
2012-10-23 12:37:10 +04:00
|
|
|
reg = <0x48072000 0x100>;
|
|
|
|
|
interrupts = <0 57 0x4>;
|
2012-07-25 09:27:58 +04:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "i2c2";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
i2c3: i2c@48060000 {
|
|
|
|
|
compatible = "ti,omap4-i2c";
|
2012-10-23 12:37:10 +04:00
|
|
|
reg = <0x48060000 0x100>;
|
|
|
|
|
interrupts = <0 61 0x4>;
|
2012-07-25 09:27:58 +04:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "i2c3";
|
|
|
|
|
};
|
|
|
|
|
|
2012-10-23 12:37:10 +04:00
|
|
|
i2c4: i2c@4807a000 {
|
2012-07-25 09:27:58 +04:00
|
|
|
compatible = "ti,omap4-i2c";
|
2012-10-23 12:37:10 +04:00
|
|
|
reg = <0x4807a000 0x100>;
|
|
|
|
|
interrupts = <0 62 0x4>;
|
2012-07-25 09:27:58 +04:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "i2c4";
|
|
|
|
|
};
|
|
|
|
|
|
2012-10-23 12:37:10 +04:00
|
|
|
i2c5: i2c@4807c000 {
|
2012-07-25 09:27:58 +04:00
|
|
|
compatible = "ti,omap4-i2c";
|
2012-10-23 12:37:10 +04:00
|
|
|
reg = <0x4807c000 0x100>;
|
|
|
|
|
interrupts = <0 60 0x4>;
|
2012-07-25 09:27:58 +04:00
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "i2c5";
|
|
|
|
|
};
|
|
|
|
|
|
2013-02-13 13:28:36 +04:00
|
|
|
mcspi1: spi@48098000 {
|
|
|
|
|
compatible = "ti,omap4-mcspi";
|
|
|
|
|
reg = <0x48098000 0x200>;
|
|
|
|
|
interrupts = <0 65 0x4>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "mcspi1";
|
|
|
|
|
ti,spi-num-cs = <4>;
|
2012-04-26 22:47:59 +04:00
|
|
|
dmas = <&sdma 35>,
|
|
|
|
|
<&sdma 36>,
|
|
|
|
|
<&sdma 37>,
|
|
|
|
|
<&sdma 38>,
|
|
|
|
|
<&sdma 39>,
|
|
|
|
|
<&sdma 40>,
|
|
|
|
|
<&sdma 41>,
|
|
|
|
|
<&sdma 42>;
|
|
|
|
|
dma-names = "tx0", "rx0", "tx1", "rx1",
|
|
|
|
|
"tx2", "rx2", "tx3", "rx3";
|
2013-02-13 13:28:36 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcspi2: spi@4809a000 {
|
|
|
|
|
compatible = "ti,omap4-mcspi";
|
|
|
|
|
reg = <0x4809a000 0x200>;
|
|
|
|
|
interrupts = <0 66 0x4>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "mcspi2";
|
|
|
|
|
ti,spi-num-cs = <2>;
|
2012-04-26 22:47:59 +04:00
|
|
|
dmas = <&sdma 43>,
|
|
|
|
|
<&sdma 44>,
|
|
|
|
|
<&sdma 45>,
|
|
|
|
|
<&sdma 46>;
|
|
|
|
|
dma-names = "tx0", "rx0", "tx1", "rx1";
|
2013-02-13 13:28:36 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcspi3: spi@480b8000 {
|
|
|
|
|
compatible = "ti,omap4-mcspi";
|
|
|
|
|
reg = <0x480b8000 0x200>;
|
|
|
|
|
interrupts = <0 91 0x4>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "mcspi3";
|
|
|
|
|
ti,spi-num-cs = <2>;
|
2012-04-26 22:47:59 +04:00
|
|
|
dmas = <&sdma 15>, <&sdma 16>;
|
|
|
|
|
dma-names = "tx0", "rx0";
|
2013-02-13 13:28:36 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcspi4: spi@480ba000 {
|
|
|
|
|
compatible = "ti,omap4-mcspi";
|
|
|
|
|
reg = <0x480ba000 0x200>;
|
|
|
|
|
interrupts = <0 48 0x4>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <0>;
|
|
|
|
|
ti,hwmods = "mcspi4";
|
|
|
|
|
ti,spi-num-cs = <1>;
|
2012-04-26 22:47:59 +04:00
|
|
|
dmas = <&sdma 70>, <&sdma 71>;
|
|
|
|
|
dma-names = "tx0", "rx0";
|
2013-02-13 13:28:36 +04:00
|
|
|
};
|
|
|
|
|
|
2012-05-10 18:16:00 +04:00
|
|
|
uart1: serial@4806a000 {
|
|
|
|
|
compatible = "ti,omap4-uart";
|
2012-10-23 12:37:11 +04:00
|
|
|
reg = <0x4806a000 0x100>;
|
|
|
|
|
interrupts = <0 72 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
ti,hwmods = "uart1";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart2: serial@4806c000 {
|
|
|
|
|
compatible = "ti,omap4-uart";
|
2012-10-23 12:37:11 +04:00
|
|
|
reg = <0x4806c000 0x100>;
|
|
|
|
|
interrupts = <0 73 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
ti,hwmods = "uart2";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart3: serial@48020000 {
|
|
|
|
|
compatible = "ti,omap4-uart";
|
2012-10-23 12:37:11 +04:00
|
|
|
reg = <0x48020000 0x100>;
|
|
|
|
|
interrupts = <0 74 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
ti,hwmods = "uart3";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart4: serial@4806e000 {
|
|
|
|
|
compatible = "ti,omap4-uart";
|
2012-10-23 12:37:11 +04:00
|
|
|
reg = <0x4806e000 0x100>;
|
|
|
|
|
interrupts = <0 70 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
ti,hwmods = "uart4";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart5: serial@48066000 {
|
2012-10-23 12:37:11 +04:00
|
|
|
compatible = "ti,omap4-uart";
|
|
|
|
|
reg = <0x48066000 0x100>;
|
|
|
|
|
interrupts = <0 105 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
ti,hwmods = "uart5";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
uart6: serial@48068000 {
|
2012-10-23 12:37:11 +04:00
|
|
|
compatible = "ti,omap4-uart";
|
|
|
|
|
reg = <0x48068000 0x100>;
|
|
|
|
|
interrupts = <0 106 0x4>;
|
2012-05-10 18:16:00 +04:00
|
|
|
ti,hwmods = "uart6";
|
|
|
|
|
clock-frequency = <48000000>;
|
|
|
|
|
};
|
2012-08-07 11:18:21 +04:00
|
|
|
|
|
|
|
|
mmc1: mmc@4809c000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 12:37:12 +04:00
|
|
|
reg = <0x4809c000 0x400>;
|
|
|
|
|
interrupts = <0 83 0x4>;
|
2012-08-07 11:18:21 +04:00
|
|
|
ti,hwmods = "mmc1";
|
|
|
|
|
ti,dual-volt;
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 22:47:59 +04:00
|
|
|
dmas = <&sdma 61>, <&sdma 62>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-07 11:18:21 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc2: mmc@480b4000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 12:37:12 +04:00
|
|
|
reg = <0x480b4000 0x400>;
|
|
|
|
|
interrupts = <0 86 0x4>;
|
2012-08-07 11:18:21 +04:00
|
|
|
ti,hwmods = "mmc2";
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 22:47:59 +04:00
|
|
|
dmas = <&sdma 47>, <&sdma 48>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-07 11:18:21 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc3: mmc@480ad000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 12:37:12 +04:00
|
|
|
reg = <0x480ad000 0x400>;
|
|
|
|
|
interrupts = <0 94 0x4>;
|
2012-08-07 11:18:21 +04:00
|
|
|
ti,hwmods = "mmc3";
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 22:47:59 +04:00
|
|
|
dmas = <&sdma 77>, <&sdma 78>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-07 11:18:21 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc4: mmc@480d1000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 12:37:12 +04:00
|
|
|
reg = <0x480d1000 0x400>;
|
|
|
|
|
interrupts = <0 96 0x4>;
|
2012-08-07 11:18:21 +04:00
|
|
|
ti,hwmods = "mmc4";
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 22:47:59 +04:00
|
|
|
dmas = <&sdma 57>, <&sdma 58>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-07 11:18:21 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mmc5: mmc@480d5000 {
|
|
|
|
|
compatible = "ti,omap4-hsmmc";
|
2012-10-23 12:37:12 +04:00
|
|
|
reg = <0x480d5000 0x400>;
|
|
|
|
|
interrupts = <0 59 0x4>;
|
2012-08-07 11:18:21 +04:00
|
|
|
ti,hwmods = "mmc5";
|
|
|
|
|
ti,needs-special-reset;
|
2012-04-26 22:47:59 +04:00
|
|
|
dmas = <&sdma 59>, <&sdma 60>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-07 11:18:21 +04:00
|
|
|
};
|
2012-07-25 09:33:27 +04:00
|
|
|
|
|
|
|
|
keypad: keypad@4ae1c000 {
|
|
|
|
|
compatible = "ti,omap4-keypad";
|
2013-01-23 18:23:30 +04:00
|
|
|
reg = <0x4ae1c000 0x400>;
|
2012-07-25 09:33:27 +04:00
|
|
|
ti,hwmods = "kbd";
|
|
|
|
|
};
|
2012-08-29 17:31:04 +04:00
|
|
|
|
2012-08-29 17:31:07 +04:00
|
|
|
mcpdm: mcpdm@40132000 {
|
|
|
|
|
compatible = "ti,omap4-mcpdm";
|
|
|
|
|
reg = <0x40132000 0x7f>, /* MPU private access */
|
|
|
|
|
<0x49032000 0x7f>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
|
|
|
|
interrupts = <0 112 0x4>;
|
|
|
|
|
ti,hwmods = "mcpdm";
|
2013-03-11 11:50:21 +04:00
|
|
|
dmas = <&sdma 65>,
|
|
|
|
|
<&sdma 66>;
|
|
|
|
|
dma-names = "up_link", "dn_link";
|
2012-08-29 17:31:07 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
dmic: dmic@4012e000 {
|
|
|
|
|
compatible = "ti,omap4-dmic";
|
|
|
|
|
reg = <0x4012e000 0x7f>, /* MPU private access */
|
|
|
|
|
<0x4902e000 0x7f>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
|
|
|
|
interrupts = <0 114 0x4>;
|
|
|
|
|
ti,hwmods = "dmic";
|
2013-03-11 11:50:21 +04:00
|
|
|
dmas = <&sdma 67>;
|
|
|
|
|
dma-names = "up_link";
|
2012-08-29 17:31:07 +04:00
|
|
|
};
|
|
|
|
|
|
2012-08-29 17:31:04 +04:00
|
|
|
mcbsp1: mcbsp@40122000 {
|
|
|
|
|
compatible = "ti,omap4-mcbsp";
|
|
|
|
|
reg = <0x40122000 0xff>, /* MPU private access */
|
|
|
|
|
<0x49022000 0xff>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
|
|
|
|
interrupts = <0 17 0x4>;
|
|
|
|
|
interrupt-names = "common";
|
|
|
|
|
ti,buffer-size = <128>;
|
|
|
|
|
ti,hwmods = "mcbsp1";
|
2013-03-11 11:50:21 +04:00
|
|
|
dmas = <&sdma 33>,
|
|
|
|
|
<&sdma 34>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-29 17:31:04 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcbsp2: mcbsp@40124000 {
|
|
|
|
|
compatible = "ti,omap4-mcbsp";
|
|
|
|
|
reg = <0x40124000 0xff>, /* MPU private access */
|
|
|
|
|
<0x49024000 0xff>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
|
|
|
|
interrupts = <0 22 0x4>;
|
|
|
|
|
interrupt-names = "common";
|
|
|
|
|
ti,buffer-size = <128>;
|
|
|
|
|
ti,hwmods = "mcbsp2";
|
2013-03-11 11:50:21 +04:00
|
|
|
dmas = <&sdma 17>,
|
|
|
|
|
<&sdma 18>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-29 17:31:04 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
mcbsp3: mcbsp@40126000 {
|
|
|
|
|
compatible = "ti,omap4-mcbsp";
|
|
|
|
|
reg = <0x40126000 0xff>, /* MPU private access */
|
|
|
|
|
<0x49026000 0xff>; /* L3 Interconnect */
|
|
|
|
|
reg-names = "mpu", "dma";
|
|
|
|
|
interrupts = <0 23 0x4>;
|
|
|
|
|
interrupt-names = "common";
|
|
|
|
|
ti,buffer-size = <128>;
|
|
|
|
|
ti,hwmods = "mcbsp3";
|
2013-03-11 11:50:21 +04:00
|
|
|
dmas = <&sdma 19>,
|
|
|
|
|
<&sdma 20>;
|
|
|
|
|
dma-names = "tx", "rx";
|
2012-08-29 17:31:04 +04:00
|
|
|
};
|
2012-11-01 18:09:51 +04:00
|
|
|
|
|
|
|
|
timer1: timer@4ae18000 {
|
2013-03-19 21:38:18 +04:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 18:09:51 +04:00
|
|
|
reg = <0x4ae18000 0x80>;
|
|
|
|
|
interrupts = <0 37 0x4>;
|
|
|
|
|
ti,hwmods = "timer1";
|
|
|
|
|
ti,timer-alwon;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer2: timer@48032000 {
|
2013-03-19 21:38:18 +04:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 18:09:51 +04:00
|
|
|
reg = <0x48032000 0x80>;
|
|
|
|
|
interrupts = <0 38 0x4>;
|
|
|
|
|
ti,hwmods = "timer2";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer3: timer@48034000 {
|
2013-03-19 21:38:18 +04:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 18:09:51 +04:00
|
|
|
reg = <0x48034000 0x80>;
|
|
|
|
|
interrupts = <0 39 0x4>;
|
|
|
|
|
ti,hwmods = "timer3";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer4: timer@48036000 {
|
2013-03-19 21:38:18 +04:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 18:09:51 +04:00
|
|
|
reg = <0x48036000 0x80>;
|
|
|
|
|
interrupts = <0 40 0x4>;
|
|
|
|
|
ti,hwmods = "timer4";
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer5: timer@40138000 {
|
2013-03-19 21:38:18 +04:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 18:09:51 +04:00
|
|
|
reg = <0x40138000 0x80>,
|
|
|
|
|
<0x49038000 0x80>;
|
|
|
|
|
interrupts = <0 41 0x4>;
|
|
|
|
|
ti,hwmods = "timer5";
|
|
|
|
|
ti,timer-dsp;
|
2013-04-18 03:23:15 +04:00
|
|
|
ti,timer-pwm;
|
2012-11-01 18:09:51 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer6: timer@4013a000 {
|
2013-03-19 21:38:18 +04:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 18:09:51 +04:00
|
|
|
reg = <0x4013a000 0x80>,
|
|
|
|
|
<0x4903a000 0x80>;
|
|
|
|
|
interrupts = <0 42 0x4>;
|
|
|
|
|
ti,hwmods = "timer6";
|
|
|
|
|
ti,timer-dsp;
|
|
|
|
|
ti,timer-pwm;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer7: timer@4013c000 {
|
2013-03-19 21:38:18 +04:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 18:09:51 +04:00
|
|
|
reg = <0x4013c000 0x80>,
|
|
|
|
|
<0x4903c000 0x80>;
|
|
|
|
|
interrupts = <0 43 0x4>;
|
|
|
|
|
ti,hwmods = "timer7";
|
|
|
|
|
ti,timer-dsp;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer8: timer@4013e000 {
|
2013-03-19 21:38:18 +04:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 18:09:51 +04:00
|
|
|
reg = <0x4013e000 0x80>,
|
|
|
|
|
<0x4903e000 0x80>;
|
|
|
|
|
interrupts = <0 44 0x4>;
|
|
|
|
|
ti,hwmods = "timer8";
|
|
|
|
|
ti,timer-dsp;
|
|
|
|
|
ti,timer-pwm;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer9: timer@4803e000 {
|
2013-03-19 21:38:18 +04:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 18:09:51 +04:00
|
|
|
reg = <0x4803e000 0x80>;
|
|
|
|
|
interrupts = <0 45 0x4>;
|
|
|
|
|
ti,hwmods = "timer9";
|
2013-04-18 03:23:15 +04:00
|
|
|
ti,timer-pwm;
|
2012-11-01 18:09:51 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer10: timer@48086000 {
|
2013-03-19 21:38:18 +04:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 18:09:51 +04:00
|
|
|
reg = <0x48086000 0x80>;
|
|
|
|
|
interrupts = <0 46 0x4>;
|
|
|
|
|
ti,hwmods = "timer10";
|
2013-04-18 03:23:15 +04:00
|
|
|
ti,timer-pwm;
|
2012-11-01 18:09:51 +04:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
timer11: timer@48088000 {
|
2013-03-19 21:38:18 +04:00
|
|
|
compatible = "ti,omap5430-timer";
|
2012-11-01 18:09:51 +04:00
|
|
|
reg = <0x48088000 0x80>;
|
|
|
|
|
interrupts = <0 47 0x4>;
|
|
|
|
|
ti,hwmods = "timer11";
|
|
|
|
|
ti,timer-pwm;
|
|
|
|
|
};
|
2012-11-05 16:52:51 +04:00
|
|
|
|
2013-02-27 10:24:45 +04:00
|
|
|
wdt2: wdt@4ae14000 {
|
|
|
|
|
compatible = "ti,omap5-wdt", "ti,omap3-wdt";
|
|
|
|
|
reg = <0x4ae14000 0x80>;
|
|
|
|
|
interrupts = <0 80 0x4>;
|
|
|
|
|
ti,hwmods = "wd_timer2";
|
|
|
|
|
};
|
|
|
|
|
|
2012-11-05 16:52:51 +04:00
|
|
|
emif1: emif@0x4c000000 {
|
|
|
|
|
compatible = "ti,emif-4d5";
|
|
|
|
|
ti,hwmods = "emif1";
|
|
|
|
|
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
|
|
|
|
reg = <0x4c000000 0x400>;
|
|
|
|
|
interrupts = <0 110 0x4>;
|
|
|
|
|
hw-caps-read-idle-ctrl;
|
|
|
|
|
hw-caps-ll-interface;
|
|
|
|
|
hw-caps-temp-alert;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
emif2: emif@0x4d000000 {
|
|
|
|
|
compatible = "ti,emif-4d5";
|
|
|
|
|
ti,hwmods = "emif2";
|
|
|
|
|
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
|
|
|
|
reg = <0x4d000000 0x400>;
|
|
|
|
|
interrupts = <0 111 0x4>;
|
|
|
|
|
hw-caps-read-idle-ctrl;
|
|
|
|
|
hw-caps-ll-interface;
|
|
|
|
|
hw-caps-temp-alert;
|
|
|
|
|
};
|
2013-03-07 17:35:17 +04:00
|
|
|
|
|
|
|
|
omap_control_usb: omap-control-usb@4a002300 {
|
|
|
|
|
compatible = "ti,omap-control-usb";
|
|
|
|
|
reg = <0x4a002300 0x4>,
|
|
|
|
|
<0x4a002370 0x4>;
|
|
|
|
|
reg-names = "control_dev_conf", "phy_power_usb";
|
|
|
|
|
ti,type = <2>;
|
|
|
|
|
};
|
2013-03-07 17:35:18 +04:00
|
|
|
|
2013-03-07 17:35:20 +04:00
|
|
|
omap_dwc3@4a020000 {
|
|
|
|
|
compatible = "ti,dwc3";
|
|
|
|
|
ti,hwmods = "usb_otg_ss";
|
|
|
|
|
reg = <0x4a020000 0x1000>;
|
|
|
|
|
interrupts = <0 93 4>;
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
utmi-mode = <2>;
|
|
|
|
|
ranges;
|
|
|
|
|
dwc3@4a030000 {
|
|
|
|
|
compatible = "synopsys,dwc3";
|
|
|
|
|
reg = <0x4a030000 0x1000>;
|
|
|
|
|
interrupts = <0 92 4>;
|
|
|
|
|
usb-phy = <&usb2_phy>, <&usb3_phy>;
|
|
|
|
|
tx-fifo-resize;
|
|
|
|
|
};
|
|
|
|
|
};
|
|
|
|
|
|
2013-03-07 17:35:18 +04:00
|
|
|
ocp2scp {
|
|
|
|
|
compatible = "ti,omap-ocp2scp";
|
|
|
|
|
#address-cells = <1>;
|
|
|
|
|
#size-cells = <1>;
|
|
|
|
|
ranges;
|
|
|
|
|
ti,hwmods = "ocp2scp1";
|
2013-03-07 17:35:19 +04:00
|
|
|
usb2_phy: usb2phy@4a084000 {
|
|
|
|
|
compatible = "ti,omap-usb2";
|
|
|
|
|
reg = <0x4a084000 0x7c>;
|
|
|
|
|
ctrl-module = <&omap_control_usb>;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
usb3_phy: usb3phy@4a084400 {
|
|
|
|
|
compatible = "ti,omap-usb3";
|
|
|
|
|
reg = <0x4a084400 0x80>,
|
|
|
|
|
<0x4a084800 0x64>,
|
|
|
|
|
<0x4a084c00 0x40>;
|
|
|
|
|
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
|
|
|
|
|
ctrl-module = <&omap_control_usb>;
|
|
|
|
|
};
|
2013-03-07 17:35:18 +04:00
|
|
|
};
|
2012-05-10 18:16:00 +04:00
|
|
|
};
|
|
|
|
|
};
|
