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/*
* Pentium 4 / Xeon CPU on demand clock modulation / speed scaling
* ( C ) 2002 - 2003 Dominik Brodowski < linux @ brodo . de >
* ( C ) 2002 Zwane Mwaikambo < zwane @ commfireservices . com >
* ( C ) 2002 Arjan van de Ven < arjanv @ redhat . com >
* ( C ) 2002 Tora T . Engstad
* All Rights Reserved
*
* This program is free software ; you can redistribute it and / or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation ; either version
* 2 of the License , or ( at your option ) any later version .
*
* The author ( s ) of this software shall not be held liable for damages
* of any nature resulting due to the use of this software . This
* software is provided AS - IS with no warranties .
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*
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* Date Errata Description
* 20020525 N44 , O17 12.5 % or 25 % DC causes lockup
*
*/
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# define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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# include <linux/kernel.h>
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# include <linux/module.h>
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# include <linux/init.h>
# include <linux/smp.h>
# include <linux/cpufreq.h>
# include <linux/cpumask.h>
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# include <linux/timex.h>
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# include <asm/processor.h>
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# include <asm/msr.h>
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# include <asm/timer.h>
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# include <asm/cpu_device_id.h>
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# include "speedstep-lib.h"
/*
* Duty Cycle ( 3 bits ) , note DC_DISABLE is not specified in
* intel docs i just use it to mean disable
*/
enum {
DC_RESV , DC_DFLT , DC_25PT , DC_38PT , DC_50PT ,
DC_64PT , DC_75PT , DC_88PT , DC_DISABLE
} ;
# define DC_ENTRIES 8
static int has_N44_O17_errata [ NR_CPUS ] ;
static unsigned int stock_freq ;
static struct cpufreq_driver p4clockmod_driver ;
static unsigned int cpufreq_p4_get ( unsigned int cpu ) ;
static int cpufreq_p4_setdc ( unsigned int cpu , unsigned int newstate )
{
u32 l , h ;
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if ( ( newstate > DC_DISABLE ) | | ( newstate = = DC_RESV ) )
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return - EINVAL ;
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rdmsr_on_cpu ( cpu , MSR_IA32_THERM_STATUS , & l , & h ) ;
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if ( l & 0x01 )
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pr_debug ( " CPU#%d currently thermal throttled \n " , cpu ) ;
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if ( has_N44_O17_errata [ cpu ] & &
( newstate = = DC_25PT | | newstate = = DC_DFLT ) )
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newstate = DC_38PT ;
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rdmsr_on_cpu ( cpu , MSR_IA32_THERM_CONTROL , & l , & h ) ;
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if ( newstate = = DC_DISABLE ) {
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pr_debug ( " CPU#%d disabling modulation \n " , cpu ) ;
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wrmsr_on_cpu ( cpu , MSR_IA32_THERM_CONTROL , l & ~ ( 1 < < 4 ) , h ) ;
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} else {
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pr_debug ( " CPU#%d setting duty cycle to %d%% \n " ,
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cpu , ( ( 125 * newstate ) / 10 ) ) ;
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/* bits 63 - 5 : reserved
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* bit 4 : enable / disable
* bits 3 - 1 : duty cycle
* bit 0 : reserved
*/
l = ( l & ~ 14 ) ;
l = l | ( 1 < < 4 ) | ( ( newstate & 0x7 ) < < 1 ) ;
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wrmsr_on_cpu ( cpu , MSR_IA32_THERM_CONTROL , l , h ) ;
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}
return 0 ;
}
static struct cpufreq_frequency_table p4clockmod_table [ ] = {
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{ 0 , DC_RESV , CPUFREQ_ENTRY_INVALID } ,
{ 0 , DC_DFLT , 0 } ,
{ 0 , DC_25PT , 0 } ,
{ 0 , DC_38PT , 0 } ,
{ 0 , DC_50PT , 0 } ,
{ 0 , DC_64PT , 0 } ,
{ 0 , DC_75PT , 0 } ,
{ 0 , DC_88PT , 0 } ,
{ 0 , DC_DISABLE , 0 } ,
{ 0 , DC_RESV , CPUFREQ_TABLE_END } ,
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} ;
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static int cpufreq_p4_target ( struct cpufreq_policy * policy , unsigned int index )
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{
int i ;
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/* run on each logical CPU,
* see section 13.15 .3 of IA32 Intel Architecture Software
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* Developer ' s Manual , Volume 3
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*/
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for_each_cpu ( i , policy - > cpus )
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cpufreq_p4_setdc ( i , p4clockmod_table [ index ] . driver_data ) ;
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return 0 ;
}
static unsigned int cpufreq_p4_get_frequency ( struct cpuinfo_x86 * c )
{
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if ( c - > x86 = = 0x06 ) {
if ( cpu_has ( c , X86_FEATURE_EST ) )
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pr_warn_once ( " Warning: EST-capable CPU detected. The acpi-cpufreq module offers voltage scaling in addition to frequency scaling. You should use that instead of p4-clockmod, if possible. \n " ) ;
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switch ( c - > x86_model ) {
case 0x0E : /* Core */
case 0x0F : /* Core Duo */
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case 0x16 : /* Celeron Core */
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case 0x1C : /* Atom */
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p4clockmod_driver . flags | = CPUFREQ_CONST_LOOPS ;
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return speedstep_get_frequency ( SPEEDSTEP_CPU_PCORE ) ;
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case 0x0D : /* Pentium M (Dothan) */
p4clockmod_driver . flags | = CPUFREQ_CONST_LOOPS ;
/* fall through */
case 0x09 : /* Pentium M (Banias) */
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return speedstep_get_frequency ( SPEEDSTEP_CPU_PM ) ;
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}
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}
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if ( c - > x86 ! = 0xF )
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return 0 ;
/* on P-4s, the TSC runs with constant frequency independent whether
* throttling is active or not . */
p4clockmod_driver . flags | = CPUFREQ_CONST_LOOPS ;
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if ( speedstep_detect_processor ( ) = = SPEEDSTEP_CPU_P4M ) {
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pr_warn ( " Warning: Pentium 4-M detected. The speedstep-ich or acpi cpufreq modules offer voltage scaling in addition of frequency scaling. You should use either one instead of p4-clockmod, if possible. \n " ) ;
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return speedstep_get_frequency ( SPEEDSTEP_CPU_P4M ) ;
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}
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return speedstep_get_frequency ( SPEEDSTEP_CPU_P4D ) ;
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}
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static int cpufreq_p4_cpu_init ( struct cpufreq_policy * policy )
{
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struct cpuinfo_x86 * c = & cpu_data ( policy - > cpu ) ;
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int cpuid = 0 ;
unsigned int i ;
# ifdef CONFIG_SMP
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cpumask_copy ( policy - > cpus , topology_sibling_cpumask ( policy - > cpu ) ) ;
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# endif
/* Errata workaround */
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cpuid = ( c - > x86 < < 8 ) | ( c - > x86_model < < 4 ) | c - > x86_stepping ;
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switch ( cpuid ) {
case 0x0f07 :
case 0x0f0a :
case 0x0f11 :
case 0x0f12 :
has_N44_O17_errata [ policy - > cpu ] = 1 ;
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pr_debug ( " has errata -- disabling low frequencies \n " ) ;
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}
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if ( speedstep_detect_processor ( ) = = SPEEDSTEP_CPU_P4D & &
c - > x86_model < 2 ) {
/* switch to maximum frequency and measure result */
cpufreq_p4_setdc ( policy - > cpu , DC_DISABLE ) ;
recalibrate_cpu_khz ( ) ;
}
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/* get max frequency */
stock_freq = cpufreq_p4_get_frequency ( c ) ;
if ( ! stock_freq )
return - EINVAL ;
/* table init */
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for ( i = 1 ; ( p4clockmod_table [ i ] . frequency ! = CPUFREQ_TABLE_END ) ; i + + ) {
if ( ( i < 2 ) & & ( has_N44_O17_errata [ policy - > cpu ] ) )
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p4clockmod_table [ i ] . frequency = CPUFREQ_ENTRY_INVALID ;
else
p4clockmod_table [ i ] . frequency = ( stock_freq * i ) / 8 ;
}
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/* cpuinfo and default policy values */
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/* the transition latency is set to be 1 higher than the maximum
* transition latency of the ondemand governor */
policy - > cpuinfo . transition_latency = 10000001 ;
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policy - > freq_table = & p4clockmod_table [ 0 ] ;
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return 0 ;
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}
static unsigned int cpufreq_p4_get ( unsigned int cpu )
{
u32 l , h ;
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rdmsr_on_cpu ( cpu , MSR_IA32_THERM_CONTROL , & l , & h ) ;
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if ( l & 0x10 ) {
l = l > > 1 ;
l & = 0x7 ;
} else
l = DC_DISABLE ;
if ( l ! = DC_DISABLE )
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return stock_freq * l / 8 ;
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return stock_freq ;
}
static struct cpufreq_driver p4clockmod_driver = {
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. verify = cpufreq_generic_frequency_table_verify ,
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. target_index = cpufreq_p4_target ,
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. init = cpufreq_p4_cpu_init ,
. get = cpufreq_p4_get ,
. name = " p4-clockmod " ,
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. attr = cpufreq_generic_attr ,
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} ;
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static const struct x86_cpu_id cpufreq_p4_id [ ] = {
{ X86_VENDOR_INTEL , X86_FAMILY_ANY , X86_MODEL_ANY , X86_FEATURE_ACC } ,
{ }
} ;
/*
* Intentionally no MODULE_DEVICE_TABLE here : this driver should not
* be auto loaded . Please don ' t add one .
*/
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static int __init cpufreq_p4_init ( void )
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{
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int ret ;
/*
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* THERM_CONTROL is architectural for IA32 now , so
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* we can rely on the capability checks
*/
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if ( ! x86_match_cpu ( cpufreq_p4_id ) | | ! boot_cpu_has ( X86_FEATURE_ACPI ) )
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return - ENODEV ;
ret = cpufreq_register_driver ( & p4clockmod_driver ) ;
if ( ! ret )
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pr_info ( " P4/Xeon(TM) CPU On-Demand Clock Modulation available \n " ) ;
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return ret ;
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}
static void __exit cpufreq_p4_exit ( void )
{
cpufreq_unregister_driver ( & p4clockmod_driver ) ;
}
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MODULE_AUTHOR ( " Zwane Mwaikambo <zwane@commfireservices.com> " ) ;
MODULE_DESCRIPTION ( " cpufreq driver for Pentium(TM) 4/Xeon(TM) " ) ;
MODULE_LICENSE ( " GPL " ) ;
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late_initcall ( cpufreq_p4_init ) ;
module_exit ( cpufreq_p4_exit ) ;