2017-03-31 16:05:59 +03:00
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/*
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* ff.h - a part of driver for RME Fireface series
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*
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* Copyright (c) 2015-2017 Takashi Sakamoto
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*
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* Licensed under the terms of the GNU General Public License, version 2.
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*/
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#ifndef SOUND_FIREFACE_H_INCLUDED
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#define SOUND_FIREFACE_H_INCLUDED
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#include <linux/device.h>
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#include <linux/firewire.h>
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#include <linux/firewire-constants.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/mutex.h>
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#include <linux/slab.h>
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#include <linux/compat.h>
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#include <sound/core.h>
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ALSA: fireface: add an abstraction layer for model-specific protocols
As of 2016, RME discontinued its Fireface series, thus it's OK for us
to focus on released firmwares to drive known units.
As long as investigating Fireface 400 with Windows driver and comparing
the result to FFADO implementation, I can see these firmwares have
different register assignments. On the other hand, according to manuals
of each models, features relevant to packet streaming seem to be common,
because GUIs for these models have the same options. It's reasonable to
assume an abstraction layer of protocols to communicate to each models.
This commit adds the abstraction layer for the protocols. This layer
includes some functions to operate common features of models in this
series.
In IEC 61883-1/6, the sequence of packet can transfer timing information
to synchronize receivers to transmitters. Units of each node on IEEE 1394
bus can generate transmitter's timing clock by handling value of SYT field
in CIP header with high-precision clock. For audio and music units on
IEEE 1394 bus, this recovered clock is designed to used for sampling clock
to capture/generate PCM frames on DSP/ADC/DAC. (Actually, in this world,
there's no units to implement this specification as is, as long as I
know).
Fireface series doesn't use this mechanism. Besides, It doesn't use
isochronous packet with CIP header. It uses internal crystal unit as its
initial sampling clock. When detecting input signals which can be
available for sampling clock (e.g. ADAT input), drivers can configure
units to use the signals as source of sampling clock. When something goes
wrong, e.g. frequency mismatching between the signal and configured value,
units fallback to the other detected signals alternatively. When detecting
no alternatives, internal crystal unit is used as source of sampling
clock. On manual of Fireface 400, this mechanism is described as
'Autosync'.
On the units, packet streaming is controlled by write transactions to
certain registers. Format of the packet, e.g. the number of data channels
in a data block, is also configured by the same manner. For this purpose,
.begin_session and .finish_session is added.
The remarkable point of this protocol is to allow drivers to configure
arbitrary sampling transmission frequency; e.g. 12.345 Hz. As long as I
know, there's no actual DAC/ADC chips which support this kind of
capability. I think a pair of packet streaming layer and data block
processing layer is isolated from sampling data processing layer in a
point of governed clock. In short, between these parts, resampling layer
exists. Actually, for Fireface 400, write transactions to
0x'0000'8010'051c has an effect to change sampling clock frequency with
base frequencies (32.0/44.1/48.0 kHz) and its multipliers (x2/x4),
regardless of sampling transmission frequency.
For this reason, the abstraction layer doesn't handle parameters for
sampling clock. Instead, each implementation of .begin_session is
expected to configure sampling transmission frequency.
For packet streaming layer, it's enough to get current selection of
source signals for the sampling clock and its frequency. In the
abstraction layer, when internal crystal is selected, drivers can sets
arbitrary sampling frequency, else they should follow configured
frequency. For this purpose, .get_clock is added.
Drivers are allows to bank up data fetching from a pair of packet
streaming/data block processing layer and sampling data processing layer.
This feature seems to suppress noises at starting/stopping packet
streaming. For this purpose, .switch_fetching_mode is added.
As I described in the above, units have remarkable mechanism to manage
sampling clock and process sampling data. For debugging purpose,
.dump_sync_status and .dump_clock_config are added. I don't have a need
to common interface to represent the status and configuration,
developers can add actual implementation of the abstraction layer as they
like.
Unlike PCM frames, MIDI messages are transferred by asynchronous
communication over IEEE 1394 bus, thus target addresses are important for
this feature. The .midi_high_addr_reg, .midi_rx_port_0_reg and
.midi_rx_port_1_reg are for this purpose. I'll describe them in following
commit.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 16:06:02 +03:00
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#include <sound/info.h>
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ALSA: fireface: add transaction support
As long as investigating Fireface 400, MIDI messages are transferred by
asynchronous communication over IEEE 1394 bus.
Fireface 400 receives MIDI messages by write transactions to two addresses;
0x'0000'0801'8000 and 0x'0000'0801'9000. Each of two seems to correspond to
MIDI port 1 and 2.
Fireface 400 transfers MIDI messages by write transactions to certain
addresses which configured by drivers. The drivers can decide upper 4 byte
of the addresses by write transactions to 0x'0000'0801'03f4. For the rest
part of the address, drivers can select from below options:
* 0x'0000'0000
* 0x'0000'0080
* 0x'0000'0100
* 0x'0000'0180
Selected options are represented in register 0x'0000'0801'051c as bit
flags. Due to this mechanism, drivers are restricted to use addresses on
'Memory space' of IEEE 1222, even if transactions to the address have
some side effects.
This commit adds transaction support for MIDI messaging, based on my
assumption that the similar mechanism is used on the other protocols. To
receive asynchronous transactions, the driver allocates a range of address
in 'Memory space'. I apply a strategy to use 0x'0000'0000 as lower 4 byte
of the address. When getting failure from Linux FireWire subsystem, this
driver retries to allocate addresses.
Unfortunately, read transaction to address 0x'0000'0801'051c returns zero
always, however write transactions have effects to the other features such
as status of sampling clock. For this reason, this commit delegates a task
to configure this register to user space applications. The applications
should set 3rd bit in LSB in little endian order.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 16:06:03 +03:00
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#include <sound/rawmidi.h>
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2017-03-31 16:05:59 +03:00
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2017-03-31 16:06:00 +03:00
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#include "../lib.h"
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2017-03-31 16:06:01 +03:00
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#define SND_FF_STREAM_MODES 3
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ALSA: fireface: add transaction support
As long as investigating Fireface 400, MIDI messages are transferred by
asynchronous communication over IEEE 1394 bus.
Fireface 400 receives MIDI messages by write transactions to two addresses;
0x'0000'0801'8000 and 0x'0000'0801'9000. Each of two seems to correspond to
MIDI port 1 and 2.
Fireface 400 transfers MIDI messages by write transactions to certain
addresses which configured by drivers. The drivers can decide upper 4 byte
of the addresses by write transactions to 0x'0000'0801'03f4. For the rest
part of the address, drivers can select from below options:
* 0x'0000'0000
* 0x'0000'0080
* 0x'0000'0100
* 0x'0000'0180
Selected options are represented in register 0x'0000'0801'051c as bit
flags. Due to this mechanism, drivers are restricted to use addresses on
'Memory space' of IEEE 1222, even if transactions to the address have
some side effects.
This commit adds transaction support for MIDI messaging, based on my
assumption that the similar mechanism is used on the other protocols. To
receive asynchronous transactions, the driver allocates a range of address
in 'Memory space'. I apply a strategy to use 0x'0000'0000 as lower 4 byte
of the address. When getting failure from Linux FireWire subsystem, this
driver retries to allocate addresses.
Unfortunately, read transaction to address 0x'0000'0801'051c returns zero
always, however write transactions have effects to the other features such
as status of sampling clock. For this reason, this commit delegates a task
to configure this register to user space applications. The applications
should set 3rd bit in LSB in little endian order.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 16:06:03 +03:00
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#define SND_FF_MAXIMIM_MIDI_QUADS 9
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#define SND_FF_IN_MIDI_PORTS 2
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#define SND_FF_OUT_MIDI_PORTS 2
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ALSA: fireface: add an abstraction layer for model-specific protocols
As of 2016, RME discontinued its Fireface series, thus it's OK for us
to focus on released firmwares to drive known units.
As long as investigating Fireface 400 with Windows driver and comparing
the result to FFADO implementation, I can see these firmwares have
different register assignments. On the other hand, according to manuals
of each models, features relevant to packet streaming seem to be common,
because GUIs for these models have the same options. It's reasonable to
assume an abstraction layer of protocols to communicate to each models.
This commit adds the abstraction layer for the protocols. This layer
includes some functions to operate common features of models in this
series.
In IEC 61883-1/6, the sequence of packet can transfer timing information
to synchronize receivers to transmitters. Units of each node on IEEE 1394
bus can generate transmitter's timing clock by handling value of SYT field
in CIP header with high-precision clock. For audio and music units on
IEEE 1394 bus, this recovered clock is designed to used for sampling clock
to capture/generate PCM frames on DSP/ADC/DAC. (Actually, in this world,
there's no units to implement this specification as is, as long as I
know).
Fireface series doesn't use this mechanism. Besides, It doesn't use
isochronous packet with CIP header. It uses internal crystal unit as its
initial sampling clock. When detecting input signals which can be
available for sampling clock (e.g. ADAT input), drivers can configure
units to use the signals as source of sampling clock. When something goes
wrong, e.g. frequency mismatching between the signal and configured value,
units fallback to the other detected signals alternatively. When detecting
no alternatives, internal crystal unit is used as source of sampling
clock. On manual of Fireface 400, this mechanism is described as
'Autosync'.
On the units, packet streaming is controlled by write transactions to
certain registers. Format of the packet, e.g. the number of data channels
in a data block, is also configured by the same manner. For this purpose,
.begin_session and .finish_session is added.
The remarkable point of this protocol is to allow drivers to configure
arbitrary sampling transmission frequency; e.g. 12.345 Hz. As long as I
know, there's no actual DAC/ADC chips which support this kind of
capability. I think a pair of packet streaming layer and data block
processing layer is isolated from sampling data processing layer in a
point of governed clock. In short, between these parts, resampling layer
exists. Actually, for Fireface 400, write transactions to
0x'0000'8010'051c has an effect to change sampling clock frequency with
base frequencies (32.0/44.1/48.0 kHz) and its multipliers (x2/x4),
regardless of sampling transmission frequency.
For this reason, the abstraction layer doesn't handle parameters for
sampling clock. Instead, each implementation of .begin_session is
expected to configure sampling transmission frequency.
For packet streaming layer, it's enough to get current selection of
source signals for the sampling clock and its frequency. In the
abstraction layer, when internal crystal is selected, drivers can sets
arbitrary sampling frequency, else they should follow configured
frequency. For this purpose, .get_clock is added.
Drivers are allows to bank up data fetching from a pair of packet
streaming/data block processing layer and sampling data processing layer.
This feature seems to suppress noises at starting/stopping packet
streaming. For this purpose, .switch_fetching_mode is added.
As I described in the above, units have remarkable mechanism to manage
sampling clock and process sampling data. For debugging purpose,
.dump_sync_status and .dump_clock_config are added. I don't have a need
to common interface to represent the status and configuration,
developers can add actual implementation of the abstraction layer as they
like.
Unlike PCM frames, MIDI messages are transferred by asynchronous
communication over IEEE 1394 bus, thus target addresses are important for
this feature. The .midi_high_addr_reg, .midi_rx_port_0_reg and
.midi_rx_port_1_reg are for this purpose. I'll describe them in following
commit.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 16:06:02 +03:00
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struct snd_ff_protocol;
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2017-03-31 16:06:01 +03:00
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struct snd_ff_spec {
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const char *const name;
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const unsigned int pcm_capture_channels[SND_FF_STREAM_MODES];
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const unsigned int pcm_playback_channels[SND_FF_STREAM_MODES];
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unsigned int midi_in_ports;
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unsigned int midi_out_ports;
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ALSA: fireface: add an abstraction layer for model-specific protocols
As of 2016, RME discontinued its Fireface series, thus it's OK for us
to focus on released firmwares to drive known units.
As long as investigating Fireface 400 with Windows driver and comparing
the result to FFADO implementation, I can see these firmwares have
different register assignments. On the other hand, according to manuals
of each models, features relevant to packet streaming seem to be common,
because GUIs for these models have the same options. It's reasonable to
assume an abstraction layer of protocols to communicate to each models.
This commit adds the abstraction layer for the protocols. This layer
includes some functions to operate common features of models in this
series.
In IEC 61883-1/6, the sequence of packet can transfer timing information
to synchronize receivers to transmitters. Units of each node on IEEE 1394
bus can generate transmitter's timing clock by handling value of SYT field
in CIP header with high-precision clock. For audio and music units on
IEEE 1394 bus, this recovered clock is designed to used for sampling clock
to capture/generate PCM frames on DSP/ADC/DAC. (Actually, in this world,
there's no units to implement this specification as is, as long as I
know).
Fireface series doesn't use this mechanism. Besides, It doesn't use
isochronous packet with CIP header. It uses internal crystal unit as its
initial sampling clock. When detecting input signals which can be
available for sampling clock (e.g. ADAT input), drivers can configure
units to use the signals as source of sampling clock. When something goes
wrong, e.g. frequency mismatching between the signal and configured value,
units fallback to the other detected signals alternatively. When detecting
no alternatives, internal crystal unit is used as source of sampling
clock. On manual of Fireface 400, this mechanism is described as
'Autosync'.
On the units, packet streaming is controlled by write transactions to
certain registers. Format of the packet, e.g. the number of data channels
in a data block, is also configured by the same manner. For this purpose,
.begin_session and .finish_session is added.
The remarkable point of this protocol is to allow drivers to configure
arbitrary sampling transmission frequency; e.g. 12.345 Hz. As long as I
know, there's no actual DAC/ADC chips which support this kind of
capability. I think a pair of packet streaming layer and data block
processing layer is isolated from sampling data processing layer in a
point of governed clock. In short, between these parts, resampling layer
exists. Actually, for Fireface 400, write transactions to
0x'0000'8010'051c has an effect to change sampling clock frequency with
base frequencies (32.0/44.1/48.0 kHz) and its multipliers (x2/x4),
regardless of sampling transmission frequency.
For this reason, the abstraction layer doesn't handle parameters for
sampling clock. Instead, each implementation of .begin_session is
expected to configure sampling transmission frequency.
For packet streaming layer, it's enough to get current selection of
source signals for the sampling clock and its frequency. In the
abstraction layer, when internal crystal is selected, drivers can sets
arbitrary sampling frequency, else they should follow configured
frequency. For this purpose, .get_clock is added.
Drivers are allows to bank up data fetching from a pair of packet
streaming/data block processing layer and sampling data processing layer.
This feature seems to suppress noises at starting/stopping packet
streaming. For this purpose, .switch_fetching_mode is added.
As I described in the above, units have remarkable mechanism to manage
sampling clock and process sampling data. For debugging purpose,
.dump_sync_status and .dump_clock_config are added. I don't have a need
to common interface to represent the status and configuration,
developers can add actual implementation of the abstraction layer as they
like.
Unlike PCM frames, MIDI messages are transferred by asynchronous
communication over IEEE 1394 bus, thus target addresses are important for
this feature. The .midi_high_addr_reg, .midi_rx_port_0_reg and
.midi_rx_port_1_reg are for this purpose. I'll describe them in following
commit.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 16:06:02 +03:00
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struct snd_ff_protocol *protocol;
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2017-03-31 16:06:01 +03:00
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};
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2017-03-31 16:05:59 +03:00
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struct snd_ff {
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struct snd_card *card;
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struct fw_unit *unit;
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struct mutex mutex;
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2017-03-31 16:06:04 +03:00
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spinlock_t lock;
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2017-03-31 16:06:00 +03:00
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bool registered;
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struct delayed_work dwork;
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2017-03-31 16:06:01 +03:00
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const struct snd_ff_spec *spec;
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ALSA: fireface: add transaction support
As long as investigating Fireface 400, MIDI messages are transferred by
asynchronous communication over IEEE 1394 bus.
Fireface 400 receives MIDI messages by write transactions to two addresses;
0x'0000'0801'8000 and 0x'0000'0801'9000. Each of two seems to correspond to
MIDI port 1 and 2.
Fireface 400 transfers MIDI messages by write transactions to certain
addresses which configured by drivers. The drivers can decide upper 4 byte
of the addresses by write transactions to 0x'0000'0801'03f4. For the rest
part of the address, drivers can select from below options:
* 0x'0000'0000
* 0x'0000'0080
* 0x'0000'0100
* 0x'0000'0180
Selected options are represented in register 0x'0000'0801'051c as bit
flags. Due to this mechanism, drivers are restricted to use addresses on
'Memory space' of IEEE 1222, even if transactions to the address have
some side effects.
This commit adds transaction support for MIDI messaging, based on my
assumption that the similar mechanism is used on the other protocols. To
receive asynchronous transactions, the driver allocates a range of address
in 'Memory space'. I apply a strategy to use 0x'0000'0000 as lower 4 byte
of the address. When getting failure from Linux FireWire subsystem, this
driver retries to allocate addresses.
Unfortunately, read transaction to address 0x'0000'0801'051c returns zero
always, however write transactions have effects to the other features such
as status of sampling clock. For this reason, this commit delegates a task
to configure this register to user space applications. The applications
should set 3rd bit in LSB in little endian order.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 16:06:03 +03:00
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/* To handle MIDI tx. */
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struct snd_rawmidi_substream *tx_midi_substreams[SND_FF_IN_MIDI_PORTS];
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struct fw_address_handler async_handler;
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/* TO handle MIDI rx. */
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struct snd_rawmidi_substream *rx_midi_substreams[SND_FF_OUT_MIDI_PORTS];
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u8 running_status[SND_FF_OUT_MIDI_PORTS];
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__le32 msg_buf[SND_FF_OUT_MIDI_PORTS][SND_FF_MAXIMIM_MIDI_QUADS];
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struct work_struct rx_midi_work[SND_FF_OUT_MIDI_PORTS];
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struct fw_transaction transactions[SND_FF_OUT_MIDI_PORTS];
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ktime_t next_ktime[SND_FF_OUT_MIDI_PORTS];
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bool rx_midi_error[SND_FF_OUT_MIDI_PORTS];
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unsigned int rx_bytes[SND_FF_OUT_MIDI_PORTS];
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2017-03-31 16:05:59 +03:00
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};
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ALSA: fireface: add an abstraction layer for model-specific protocols
As of 2016, RME discontinued its Fireface series, thus it's OK for us
to focus on released firmwares to drive known units.
As long as investigating Fireface 400 with Windows driver and comparing
the result to FFADO implementation, I can see these firmwares have
different register assignments. On the other hand, according to manuals
of each models, features relevant to packet streaming seem to be common,
because GUIs for these models have the same options. It's reasonable to
assume an abstraction layer of protocols to communicate to each models.
This commit adds the abstraction layer for the protocols. This layer
includes some functions to operate common features of models in this
series.
In IEC 61883-1/6, the sequence of packet can transfer timing information
to synchronize receivers to transmitters. Units of each node on IEEE 1394
bus can generate transmitter's timing clock by handling value of SYT field
in CIP header with high-precision clock. For audio and music units on
IEEE 1394 bus, this recovered clock is designed to used for sampling clock
to capture/generate PCM frames on DSP/ADC/DAC. (Actually, in this world,
there's no units to implement this specification as is, as long as I
know).
Fireface series doesn't use this mechanism. Besides, It doesn't use
isochronous packet with CIP header. It uses internal crystal unit as its
initial sampling clock. When detecting input signals which can be
available for sampling clock (e.g. ADAT input), drivers can configure
units to use the signals as source of sampling clock. When something goes
wrong, e.g. frequency mismatching between the signal and configured value,
units fallback to the other detected signals alternatively. When detecting
no alternatives, internal crystal unit is used as source of sampling
clock. On manual of Fireface 400, this mechanism is described as
'Autosync'.
On the units, packet streaming is controlled by write transactions to
certain registers. Format of the packet, e.g. the number of data channels
in a data block, is also configured by the same manner. For this purpose,
.begin_session and .finish_session is added.
The remarkable point of this protocol is to allow drivers to configure
arbitrary sampling transmission frequency; e.g. 12.345 Hz. As long as I
know, there's no actual DAC/ADC chips which support this kind of
capability. I think a pair of packet streaming layer and data block
processing layer is isolated from sampling data processing layer in a
point of governed clock. In short, between these parts, resampling layer
exists. Actually, for Fireface 400, write transactions to
0x'0000'8010'051c has an effect to change sampling clock frequency with
base frequencies (32.0/44.1/48.0 kHz) and its multipliers (x2/x4),
regardless of sampling transmission frequency.
For this reason, the abstraction layer doesn't handle parameters for
sampling clock. Instead, each implementation of .begin_session is
expected to configure sampling transmission frequency.
For packet streaming layer, it's enough to get current selection of
source signals for the sampling clock and its frequency. In the
abstraction layer, when internal crystal is selected, drivers can sets
arbitrary sampling frequency, else they should follow configured
frequency. For this purpose, .get_clock is added.
Drivers are allows to bank up data fetching from a pair of packet
streaming/data block processing layer and sampling data processing layer.
This feature seems to suppress noises at starting/stopping packet
streaming. For this purpose, .switch_fetching_mode is added.
As I described in the above, units have remarkable mechanism to manage
sampling clock and process sampling data. For debugging purpose,
.dump_sync_status and .dump_clock_config are added. I don't have a need
to common interface to represent the status and configuration,
developers can add actual implementation of the abstraction layer as they
like.
Unlike PCM frames, MIDI messages are transferred by asynchronous
communication over IEEE 1394 bus, thus target addresses are important for
this feature. The .midi_high_addr_reg, .midi_rx_port_0_reg and
.midi_rx_port_1_reg are for this purpose. I'll describe them in following
commit.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 16:06:02 +03:00
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enum snd_ff_clock_src {
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SND_FF_CLOCK_SRC_INTERNAL,
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SND_FF_CLOCK_SRC_SPDIF,
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SND_FF_CLOCK_SRC_ADAT,
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SND_FF_CLOCK_SRC_WORD,
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SND_FF_CLOCK_SRC_LTC,
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/* TODO: perhaps ADAT2 and TCO exists. */
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};
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struct snd_ff_protocol {
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int (*get_clock)(struct snd_ff *ff, unsigned int *rate,
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enum snd_ff_clock_src *src);
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int (*begin_session)(struct snd_ff *ff, unsigned int rate);
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void (*finish_session)(struct snd_ff *ff);
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int (*switch_fetching_mode)(struct snd_ff *ff, bool enable);
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void (*dump_sync_status)(struct snd_ff *ff,
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struct snd_info_buffer *buffer);
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void (*dump_clock_config)(struct snd_ff *ff,
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struct snd_info_buffer *buffer);
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u64 midi_high_addr_reg;
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u64 midi_rx_port_0_reg;
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u64 midi_rx_port_1_reg;
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};
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ALSA: fireface: add transaction support
As long as investigating Fireface 400, MIDI messages are transferred by
asynchronous communication over IEEE 1394 bus.
Fireface 400 receives MIDI messages by write transactions to two addresses;
0x'0000'0801'8000 and 0x'0000'0801'9000. Each of two seems to correspond to
MIDI port 1 and 2.
Fireface 400 transfers MIDI messages by write transactions to certain
addresses which configured by drivers. The drivers can decide upper 4 byte
of the addresses by write transactions to 0x'0000'0801'03f4. For the rest
part of the address, drivers can select from below options:
* 0x'0000'0000
* 0x'0000'0080
* 0x'0000'0100
* 0x'0000'0180
Selected options are represented in register 0x'0000'0801'051c as bit
flags. Due to this mechanism, drivers are restricted to use addresses on
'Memory space' of IEEE 1222, even if transactions to the address have
some side effects.
This commit adds transaction support for MIDI messaging, based on my
assumption that the similar mechanism is used on the other protocols. To
receive asynchronous transactions, the driver allocates a range of address
in 'Memory space'. I apply a strategy to use 0x'0000'0000 as lower 4 byte
of the address. When getting failure from Linux FireWire subsystem, this
driver retries to allocate addresses.
Unfortunately, read transaction to address 0x'0000'0801'051c returns zero
always, however write transactions have effects to the other features such
as status of sampling clock. For this reason, this commit delegates a task
to configure this register to user space applications. The applications
should set 3rd bit in LSB in little endian order.
Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
2017-03-31 16:06:03 +03:00
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int snd_ff_transaction_register(struct snd_ff *ff);
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int snd_ff_transaction_reregister(struct snd_ff *ff);
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void snd_ff_transaction_unregister(struct snd_ff *ff);
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2017-03-31 16:06:04 +03:00
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int snd_ff_create_midi_devices(struct snd_ff *ff);
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2017-03-31 16:05:59 +03:00
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#endif
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