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Fourth batch of cleanup/SoC for 3.19: 

- removal of legacy board support for the last SoC having board C files: at91rm9200
 - removal or modification of some Kconfig options
 - switch to USE_OF for all the AT91 SoCs
 - removal of the old AT91-specific clocks and IRQ drivers
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Merge tag 'at91-cleanup4' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/cleanup

Pull "Fourth batch of cleanup/SoC for 3.19" from Nicolas Ferre:

- removal of legacy board support for the last SoC having board C files: at91rm9200
- removal or modification of some Kconfig options
- switch to USE_OF for all the AT91 SoCs
- removal of the old AT91-specific clocks and IRQ drivers

* tag 'at91-cleanup4' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91:
  ARM: at91: remove unused IRQ function declarations
  ARM: at91: remove legacy IRQ driver and related code
  ARM: at91: remove old at91-specific clock driver
  ARM: at91: remove clock data in at91sam9n12.c and at91sam9x5.c files
  ARM: at91: remove all !DT related configuration options
  ARM: at91/trivial: update Kconfig comment to mention SAMA5
  ARM: at91: always USE_OF from now on
  ARM: at91/Kconfig: remove ARCH_AT91RM9200 option for drivers
  ARM: at91: switch configuration option to SOC_AT91RM9200
  ARM: at91: remove at91rm9200 legacy board support
  ARM: at91: remove at91rm9200 legacy boards files

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2014-11-28 16:18:18 +01:00
Родитель e155aee2b2 4a109c50d1
Коммит 00239d9da3
35 изменённых файлов: 19 добавлений и 6403 удалений
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5
arch/arm/Kconfig
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@ -378,10 +378,11 @@ config ARCH_AT91
select IRQ_DOMAIN
select NEED_MACH_IO_H if PCCARD
select PINCTRL
select PINCTRL_AT91 if USE_OF
select PINCTRL_AT91
select USE_OF
help
This enables support for systems based on Atmel
AT91RM9200 and AT91SAM9* processors.
AT91RM9200, AT91SAM9 and SAMA5 processors.
config ARCH_CLPS711X
bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"

161
arch/arm/configs/at91rm9200_defconfig
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@ -1,161 +0,0 @@
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
CONFIG_USER_NS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
CONFIG_MODULE_UNLOAD=y
CONFIG_MODVERSIONS=y
CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91RM9200=y
CONFIG_MACH_ONEARM=y
CONFIG_MACH_AT91RM9200EK=y
CONFIG_MACH_CSB337=y
CONFIG_MACH_CSB637=y
CONFIG_MACH_CARMEVA=y
CONFIG_MACH_ATEB9200=y
CONFIG_MACH_KB9200=y
CONFIG_MACH_PICOTUX2XX=y
CONFIG_MACH_KAFA=y
CONFIG_MACH_ECBAT91=y
CONFIG_MACH_YL9200=y
CONFIG_MACH_CPUAT91=y
CONFIG_MACH_ECO920=y
CONFIG_MTD_AT91_DATAFLASH_CARD=y
CONFIG_AT91_TIMER_HZ=100
# CONFIG_ARM_THUMB is not set
CONFIG_PCCARD=y
CONFIG_AT91_CF=y
CONFIG_AEABI=y
# CONFIG_COMPACTION is not set
CONFIG_ZBOOT_ROM_TEXT=0x10000000
CONFIG_ZBOOT_ROM_BSS=0x20040000
CONFIG_KEXEC=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_FPE_NWFPE=y
CONFIG_BINFMT_MISC=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
CONFIG_IPV6=y
CONFIG_IPV6_PRIVACY=y
CONFIG_IPV6_ROUTER_PREF=y
CONFIG_IPV6_ROUTE_INFO=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_STANDALONE is not set
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PLATRAM=y
CONFIG_MTD_DATAFLASH=y
CONFIG_MTD_NAND=y
CONFIG_MTD_NAND_ATMEL=y
CONFIG_MTD_NAND_PLATFORM=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_GLUEBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_NETDEVICES=y
CONFIG_MII=y
CONFIG_ARM_AT91_ETHER=y
CONFIG_DAVICOM_PHY=y
CONFIG_SMSC_PHY=y
CONFIG_MICREL_PHY=y
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV is not set
CONFIG_INPUT_EVDEV=y
CONFIG_KEYBOARD_GPIO=y
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_ATMEL=y
CONFIG_SERIAL_ATMEL_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_GPIO=y
CONFIG_SPI=y
CONFIG_SPI_ATMEL=y
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_NOWAYOUT=y
CONFIG_AT91RM9200_WATCHDOG=y
CONFIG_FB=y
CONFIG_FB_MODE_HELPERS=y
CONFIG_FB_TILEBLITTING=y
CONFIG_FB_S1D13XXX=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FONTS=y
CONFIG_LOGO=y
CONFIG_USB=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_USB_AT91=y
CONFIG_USB_G_SERIAL=y
CONFIG_MMC=y
CONFIG_MMC_ATMELMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_GPIO=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_AT91RM9200=y
CONFIG_EXT4_FS=y
CONFIG_AUTOFS4_FS=y
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
CONFIG_NFS_FS=y
CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_CODEPAGE_850=y
CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_UTF8=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_CRYPTO_PCBC=y
CONFIG_CRYPTO_SHA1=y
CONFIG_XZ_DEC_ARMTHUMB=y

34
arch/arm/mach-at91/Kconfig
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@ -15,23 +15,10 @@ config HAVE_AT91_DBGU1
config HAVE_AT91_DBGU2
bool
config AT91_USE_OLD_CLK
bool
config COMMON_CLK_AT91
bool
default USE_OF && !AT91_USE_OLD_CLK
select COMMON_CLK
config OLD_CLK_AT91
bool
default AT91_USE_OLD_CLK
config OLD_IRQ_AT91
bool
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
config HAVE_AT91_SMD
bool
@ -40,18 +27,19 @@ config HAVE_AT91_H32MX
config SOC_AT91SAM9
bool
select ATMEL_AIC_IRQ if !OLD_IRQ_AT91
select ATMEL_AIC_IRQ
select COMMON_CLK_AT91
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select MEMORY if USE_OF
select ATMEL_SDRAMC if USE_OF
select MEMORY
select ATMEL_SDRAMC
config SOC_SAMA5
bool
select ATMEL_AIC5_IRQ
select COMMON_CLK_AT91
select CPU_V7
select GENERIC_CLOCKEVENTS
select USE_OF
select MEMORY
select ATMEL_SDRAMC
select PHYLIB if NETDEVICES
@ -109,7 +97,8 @@ endif
if SOC_SAM_V4_V5
config SOC_AT91RM9200
bool "AT91RM9200"
select ATMEL_AIC_IRQ if !OLD_IRQ_AT91
select ATMEL_AIC_IRQ
select COMMON_CLK_AT91
select CPU_ARM920T
select GENERIC_CLOCKEVENTS
select HAVE_AT91_DBGU0
@ -185,17 +174,11 @@ config SOC_AT91SAM9N12
# ----------------------------------------------------------
endif # SOC_SAM_V4_V5
if SOC_SAM_V4_V5
source arch/arm/mach-at91/Kconfig.non_dt
endif
comment "Generic Board Type"
config MACH_AT91RM9200_DT
bool "Atmel AT91RM9200 Evaluation Kits with device-tree support"
depends on SOC_AT91RM9200
select USE_OF
help
Select this if you want to experiment device-tree with
an Atmel RM9200 Evaluation Kit.
@ -203,7 +186,6 @@ config MACH_AT91RM9200_DT
config MACH_AT91SAM9_DT
bool "Atmel AT91SAM Evaluation Kits with device-tree support"
depends on SOC_AT91SAM9
select USE_OF
help
Select this if you want to experiment device-tree with
an Atmel Evaluation Kit.
@ -229,7 +211,7 @@ config AT91_TIMER_HZ
int "Kernel HZ (jiffies per second)"
range 32 1024
depends on ARCH_AT91
default "128" if ARCH_AT91RM9200
default "128" if SOC_AT91RM9200
default "100"
help
On AT91rm9200 chips where you're using a system clock derived

114
arch/arm/mach-at91/Kconfig.non_dt
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@ -1,114 +0,0 @@
menu "Atmel Non-DT world"
config HAVE_AT91_DATAFLASH_CARD
bool
choice
prompt "Atmel AT91 Processor Devices for non DT boards"
config ARCH_AT91_NONE
bool "None"
config ARCH_AT91RM9200
bool "AT91RM9200"
select SOC_AT91RM9200
select AT91_USE_OLD_CLK
select OLD_IRQ_AT91
endchoice
# ----------------------------------------------------------
if ARCH_AT91RM9200
comment "AT91RM9200 Board Type"
config MACH_ONEARM
bool "Ajeco 1ARM Single Board Computer"
help
Select this if you are using Ajeco's 1ARM Single Board Computer.
<http://www.ajeco.fi/>
config MACH_AT91RM9200EK
bool "Atmel AT91RM9200-EK Evaluation Kit"
select HAVE_AT91_DATAFLASH_CARD
help
Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
<http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
config MACH_CSB337
bool "Cogent CSB337"
help
Select this if you are using Cogent's CSB337 board.
<http://www.cogcomp.com/csb_csb337.htm>
config MACH_CSB637
bool "Cogent CSB637"
help
Select this if you are using Cogent's CSB637 board.
<http://www.cogcomp.com/csb_csb637.htm>
config MACH_CARMEVA
bool "Conitec ARM&EVA"
help
Select this if you are using Conitec's AT91RM9200-MCU-Module.
<http://www.conitec.net/english/linuxboard.php>
config MACH_ATEB9200
bool "Embest ATEB9200"
help
Select this if you are using Embest's ATEB9200 board.
<http://www.embedinfo.com/english/product/ATEB9200.asp>
config MACH_KB9200
bool "KwikByte KB920x"
help
Select this if you are using KwikByte's KB920x board.
<http://www.kwikbyte.com/KB9202.html>
config MACH_PICOTUX2XX
bool "picotux 200"
help
Select this if you are using a picotux 200.
<http://www.picotux.com/>
config MACH_KAFA
bool "Sperry-Sun KAFA board"
help
Select this if you are using Sperry-Sun's KAFA board.
config MACH_ECBAT91
bool "emQbit ECB_AT91 SBC"
select HAVE_AT91_DATAFLASH_CARD
help
Select this if you are using emQbit's ECB_AT91 board.
<http://wiki.emqbit.com/free-ecb-at91>
config MACH_YL9200
bool "ucDragon YL-9200"
help
Select this if you are using the ucDragon YL-9200 board.
config MACH_CPUAT91
bool "Eukrea CPUAT91"
help
Select this if you are using the Eukrea Electromatique's
CPUAT91 board <http://www.eukrea.com/>.
config MACH_ECO920
bool "eco920"
help
Select this if you are using the eco920 board
endif
# ----------------------------------------------------------
comment "AT91 Board Options"
config MTD_AT91_DATAFLASH_CARD
bool "Enable DataFlash Card support"
depends on HAVE_AT91_DATAFLASH_CARD
help
Enable support for the DataFlash card.
endmenu

19
arch/arm/mach-at91/Makefile
Просмотреть файл

@ -4,8 +4,6 @@
obj-y := gpio.o setup.o sysirq_mask.o
obj-$(CONFIG_OLD_IRQ_AT91) += irq.o
obj-$(CONFIG_OLD_CLK_AT91) += clock.o
obj-$(CONFIG_SOC_AT91SAM9) += sam9_smc.o
# CPU-specific support
@ -20,23 +18,6 @@ obj-$(CONFIG_SOC_AT91SAM9RL) += at91sam9rl.o
obj-$(CONFIG_SOC_SAMA5D3) += sama5d3.o
obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200_devices.o
# AT91RM9200 board-specific support
obj-$(CONFIG_MACH_ONEARM) += board-1arm.o
obj-$(CONFIG_MACH_AT91RM9200EK) += board-rm9200ek.o
obj-$(CONFIG_MACH_CSB337) += board-csb337.o
obj-$(CONFIG_MACH_CSB637) += board-csb637.o
obj-$(CONFIG_MACH_CARMEVA) += board-carmeva.o
obj-$(CONFIG_MACH_KB9200) += board-kb9202.o
obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o
obj-$(CONFIG_MACH_KAFA) += board-kafa.o
obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o
obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o
obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o
obj-$(CONFIG_MACH_CPUAT91) += board-cpuat91.o
obj-$(CONFIG_MACH_ECO920) += board-eco920.o
# AT91SAM board with device-tree
obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o

99
arch/arm/mach-at91/at91_aic.h
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@ -1,99 +0,0 @@
/*
* arch/arm/mach-at91/include/mach/at91_aic.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Advanced Interrupt Controller (AIC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_AIC_H
#define AT91_AIC_H
#ifndef __ASSEMBLY__
extern void __iomem *at91_aic_base;
#define at91_aic_read(field) \
__raw_readl(at91_aic_base + field)
#define at91_aic_write(field, value) \
__raw_writel(value, at91_aic_base + field)
#else
.extern at91_aic_base
#endif
/* Number of irq lines managed by AIC */
#define NR_AIC_IRQS 32
#define NR_AIC5_IRQS 128
#define AT91_AIC5_SSR 0x0 /* Source Select Register [AIC5] */
#define AT91_AIC5_INTSEL_MSK (0x7f << 0) /* Interrupt Line Selection Mask */
#define AT91_AIC_IRQ_MIN_PRIORITY 0
#define AT91_AIC_IRQ_MAX_PRIORITY 7
#define AT91_AIC_SMR(n) ((n) * 4) /* Source Mode Registers 0-31 */
#define AT91_AIC5_SMR 0x4 /* Source Mode Register [AIC5] */
#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
#define AT91_AIC_SRCTYPE_LOW (0 << 5)
#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
#define AT91_AIC_SRCTYPE_RISING (3 << 5)
#define AT91_AIC_SVR(n) (0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
#define AT91_AIC5_SVR 0x8 /* Source Vector Register [AIC5] */
#define AT91_AIC_IVR 0x100 /* Interrupt Vector Register */
#define AT91_AIC5_IVR 0x10 /* Interrupt Vector Register [AIC5] */
#define AT91_AIC_FVR 0x104 /* Fast Interrupt Vector Register */
#define AT91_AIC5_FVR 0x14 /* Fast Interrupt Vector Register [AIC5] */
#define AT91_AIC_ISR 0x108 /* Interrupt Status Register */
#define AT91_AIC5_ISR 0x18 /* Interrupt Status Register [AIC5] */
#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
#define AT91_AIC_IPR 0x10c /* Interrupt Pending Register */
#define AT91_AIC5_IPR0 0x20 /* Interrupt Pending Register 0 [AIC5] */
#define AT91_AIC5_IPR1 0x24 /* Interrupt Pending Register 1 [AIC5] */
#define AT91_AIC5_IPR2 0x28 /* Interrupt Pending Register 2 [AIC5] */
#define AT91_AIC5_IPR3 0x2c /* Interrupt Pending Register 3 [AIC5] */
#define AT91_AIC_IMR 0x110 /* Interrupt Mask Register */
#define AT91_AIC5_IMR 0x30 /* Interrupt Mask Register [AIC5] */
#define AT91_AIC_CISR 0x114 /* Core Interrupt Status Register */
#define AT91_AIC5_CISR 0x34 /* Core Interrupt Status Register [AIC5] */
#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
#define AT91_AIC_IECR 0x120 /* Interrupt Enable Command Register */
#define AT91_AIC5_IECR 0x40 /* Interrupt Enable Command Register [AIC5] */
#define AT91_AIC_IDCR 0x124 /* Interrupt Disable Command Register */
#define AT91_AIC5_IDCR 0x44 /* Interrupt Disable Command Register [AIC5] */
#define AT91_AIC_ICCR 0x128 /* Interrupt Clear Command Register */
#define AT91_AIC5_ICCR 0x48 /* Interrupt Clear Command Register [AIC5] */
#define AT91_AIC_ISCR 0x12c /* Interrupt Set Command Register */
#define AT91_AIC5_ISCR 0x4c /* Interrupt Set Command Register [AIC5] */
#define AT91_AIC_EOICR 0x130 /* End of Interrupt Command Register */
#define AT91_AIC5_EOICR 0x38 /* End of Interrupt Command Register [AIC5] */
#define AT91_AIC_SPU 0x134 /* Spurious Interrupt Vector Register */
#define AT91_AIC5_SPU 0x3c /* Spurious Interrupt Vector Register [AIC5] */
#define AT91_AIC_DCR 0x138 /* Debug Control Register */
#define AT91_AIC5_DCR 0x6c /* Debug Control Register [AIC5] */
#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
#define AT91_AIC_FFER 0x140 /* Fast Forcing Enable Register [SAM9 only] */
#define AT91_AIC5_FFER 0x50 /* Fast Forcing Enable Register [AIC5] */
#define AT91_AIC_FFDR 0x144 /* Fast Forcing Disable Register [SAM9 only] */
#define AT91_AIC5_FFDR 0x54 /* Fast Forcing Disable Register [AIC5] */
#define AT91_AIC_FFSR 0x148 /* Fast Forcing Status Register [SAM9 only] */
#define AT91_AIC5_FFSR 0x58 /* Fast Forcing Status Register [AIC5] */
void at91_aic_handle_irq(struct pt_regs *regs);
void at91_aic5_handle_irq(struct pt_regs *regs);
#endif

341
arch/arm/mach-at91/at91rm9200.c
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@ -11,296 +11,15 @@
*/
#include <linux/module.h>
#include <linux/reboot.h>
#include <linux/clk/at91_pmc.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/system_misc.h>
#include <mach/at91rm9200.h>
#include <mach/at91_st.h>
#include <mach/cpu.h>
#include <mach/hardware.h>
#include "at91_aic.h"
#include "soc.h"
#include "generic.h"
#include "sam9_smc.h"
#include "pm.h"
#if defined(CONFIG_OLD_CLK_AT91)
#include "clock.h"
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
/*
* The peripheral clocks.
*/
static struct clk udc_clk = {
.name = "udc_clk",
.pmc_mask = 1 << AT91RM9200_ID_UDP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ohci_clk = {
.name = "ohci_clk",
.pmc_mask = 1 << AT91RM9200_ID_UHP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ether_clk = {
.name = "ether_clk",
.pmc_mask = 1 << AT91RM9200_ID_EMAC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
.name = "mci_clk",
.pmc_mask = 1 << AT91RM9200_ID_MCI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi_clk = {
.name = "twi_clk",
.pmc_mask = 1 << AT91RM9200_ID_TWI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
.name = "usart0_clk",
.pmc_mask = 1 << AT91RM9200_ID_US0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
.name = "usart1_clk",
.pmc_mask = 1 << AT91RM9200_ID_US1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
.name = "usart2_clk",
.pmc_mask = 1 << AT91RM9200_ID_US2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
.name = "usart3_clk",
.pmc_mask = 1 << AT91RM9200_ID_US3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi_clk = {
.name = "spi_clk",
.pmc_mask = 1 << AT91RM9200_ID_SPI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioA_clk = {
.name = "pioA_clk",
.pmc_mask = 1 << AT91RM9200_ID_PIOA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioB_clk = {
.name = "pioB_clk",
.pmc_mask = 1 << AT91RM9200_ID_PIOB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioC_clk = {
.name = "pioC_clk",
.pmc_mask = 1 << AT91RM9200_ID_PIOC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioD_clk = {
.name = "pioD_clk",
.pmc_mask = 1 << AT91RM9200_ID_PIOD,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc0_clk = {
.name = "ssc0_clk",
.pmc_mask = 1 << AT91RM9200_ID_SSC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc1_clk = {
.name = "ssc1_clk",
.pmc_mask = 1 << AT91RM9200_ID_SSC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc2_clk = {
.name = "ssc2_clk",
.pmc_mask = 1 << AT91RM9200_ID_SSC2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc0_clk = {
.name = "tc0_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc1_clk = {
.name = "tc1_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc2_clk = {
.name = "tc2_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc3_clk = {
.name = "tc3_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc4_clk = {
.name = "tc4_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC4,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tc5_clk = {
.name = "tc5_clk",
.pmc_mask = 1 << AT91RM9200_ID_TC5,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk *periph_clocks[] __initdata = {
&pioA_clk,
&pioB_clk,
&pioC_clk,
&pioD_clk,
&usart0_clk,
&usart1_clk,
&usart2_clk,
&usart3_clk,
&mmc_clk,
&udc_clk,
&twi_clk,
&spi_clk,
&ssc0_clk,
&ssc1_clk,
&ssc2_clk,
&tc0_clk,
&tc1_clk,
&tc2_clk,
&tc3_clk,
&tc4_clk,
&tc5_clk,
&ohci_clk,
&ether_clk,
// irq0 .. irq6
};
static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk),
CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk),
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk),
CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk),
CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk),
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk),
CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk),
CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk),
CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk),
/* fake hclk clock */
CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
CLKDEV_CON_ID("pioA", &pioA_clk),
CLKDEV_CON_ID("pioB", &pioB_clk),
CLKDEV_CON_ID("pioC", &pioC_clk),
CLKDEV_CON_ID("pioD", &pioD_clk),
/* usart lookup table for DT entries */
CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
CLKDEV_CON_DEV_ID("usart", "fffc0000.serial", &usart0_clk),
CLKDEV_CON_DEV_ID("usart", "fffc4000.serial", &usart1_clk),
CLKDEV_CON_DEV_ID("usart", "fffc8000.serial", &usart2_clk),
CLKDEV_CON_DEV_ID("usart", "fffcc000.serial", &usart3_clk),
/* tc lookup table for DT entries */
CLKDEV_CON_DEV_ID("t0_clk", "fffa0000.timer", &tc0_clk),
CLKDEV_CON_DEV_ID("t1_clk", "fffa0000.timer", &tc1_clk),
CLKDEV_CON_DEV_ID("t2_clk", "fffa0000.timer", &tc2_clk),
CLKDEV_CON_DEV_ID("t0_clk", "fffa4000.timer", &tc3_clk),
CLKDEV_CON_DEV_ID("t1_clk", "fffa4000.timer", &tc4_clk),
CLKDEV_CON_DEV_ID("t2_clk", "fffa4000.timer", &tc5_clk),
CLKDEV_CON_DEV_ID("mci_clk", "fffb4000.mmc", &mmc_clk),
CLKDEV_CON_DEV_ID("emac_clk", "fffbc000.ethernet", &ether_clk),
CLKDEV_CON_DEV_ID(NULL, "fffb8000.i2c", &twi_clk),
CLKDEV_CON_DEV_ID("hclk", "300000.ohci", &ohci_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioA_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
};
static struct clk_lookup usart_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
CLKDEV_CON_DEV_ID("usart", "atmel_usart.4", &usart3_clk),
};
/*
* The four programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 1,
};
static struct clk pck2 = {
.name = "pck2",
.pmc_mask = AT91_PMC_PCK2,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 2,
};
static struct clk pck3 = {
.name = "pck3",
.pmc_mask = AT91_PMC_PCK3,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 3,
};
static void __init at91rm9200_register_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
clkdev_add_table(periph_clocks_lookups,
ARRAY_SIZE(periph_clocks_lookups));
clkdev_add_table(usart_clocks_lookups,
ARRAY_SIZE(usart_clocks_lookups));
clk_register(&pck0);
clk_register(&pck1);
clk_register(&pck2);
clk_register(&pck3);
}
#else
#define at91rm9200_register_clocks NULL
#endif
/* --------------------------------------------------------------------
* GPIO
* -------------------------------------------------------------------- */
static struct at91_gpio_bank at91rm9200_gpio[] __initdata = {
{
.id = AT91RM9200_ID_PIOA,
.regbase = AT91RM9200_BASE_PIOA,
}, {
.id = AT91RM9200_ID_PIOB,
.regbase = AT91RM9200_BASE_PIOB,
}, {
.id = AT91RM9200_ID_PIOC,
.regbase = AT91RM9200_BASE_PIOC,
}, {
.id = AT91RM9200_ID_PIOD,
.regbase = AT91RM9200_BASE_PIOD,
}
};
static void at91rm9200_idle(void)
{
@ -329,74 +48,14 @@ static void __init at91rm9200_map_io(void)
at91_init_sram(0, AT91RM9200_SRAM_BASE, AT91RM9200_SRAM_SIZE);
}
static void __init at91rm9200_ioremap_registers(void)
{
at91rm9200_ioremap_st(AT91RM9200_BASE_ST);
at91_ioremap_ramc(0, AT91RM9200_BASE_MC, 256);
at91_pm_set_standby(at91rm9200_standby);
}
static void __init at91rm9200_initialize(void)
{
arm_pm_idle = at91rm9200_idle;
arm_pm_restart = at91rm9200_restart;
/* Initialize GPIO subsystem */
at91_gpio_init(at91rm9200_gpio,
cpu_is_at91rm9200_bga() ? AT91RM9200_BGA : AT91RM9200_PQFP);
}
/* --------------------------------------------------------------------
* Interrupt initialization
* -------------------------------------------------------------------- */
/*
* The default interrupt priority levels (0 = lowest, 7 = highest).
*/
static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {
7, /* Advanced Interrupt Controller (FIQ) */
7, /* System Peripherals */
1, /* Parallel IO Controller A */
1, /* Parallel IO Controller B */
1, /* Parallel IO Controller C */
1, /* Parallel IO Controller D */
5, /* USART 0 */
5, /* USART 1 */
5, /* USART 2 */
5, /* USART 3 */
0, /* Multimedia Card Interface */
2, /* USB Device Port */
6, /* Two-Wire Interface */
5, /* Serial Peripheral Interface */
4, /* Serial Synchronous Controller 0 */
4, /* Serial Synchronous Controller 1 */
4, /* Serial Synchronous Controller 2 */
0, /* Timer Counter 0 */
0, /* Timer Counter 1 */
0, /* Timer Counter 2 */
0, /* Timer Counter 3 */
0, /* Timer Counter 4 */
0, /* Timer Counter 5 */
2, /* USB Host port */
3, /* Ethernet MAC */
0, /* Advanced Interrupt Controller (IRQ0) */
0, /* Advanced Interrupt Controller (IRQ1) */
0, /* Advanced Interrupt Controller (IRQ2) */
0, /* Advanced Interrupt Controller (IRQ3) */
0, /* Advanced Interrupt Controller (IRQ4) */
0, /* Advanced Interrupt Controller (IRQ5) */
0 /* Advanced Interrupt Controller (IRQ6) */
};
AT91_SOC_START(at91rm9200)
.map_io = at91rm9200_map_io,
.default_irq_priority = at91rm9200_default_irq_priority,
.extern_irq = (1 << AT91RM9200_ID_IRQ0) | (1 << AT91RM9200_ID_IRQ1)
| (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3)
| (1 << AT91RM9200_ID_IRQ4) | (1 << AT91RM9200_ID_IRQ5)
| (1 << AT91RM9200_ID_IRQ6),
.ioremap_registers = at91rm9200_ioremap_registers,
.register_clocks = at91rm9200_register_clocks,
.init = at91rm9200_initialize,
AT91_SOC_END

1212
arch/arm/mach-at91/at91rm9200_devices.c
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213
arch/arm/mach-at91/at91sam9n12.c
Просмотреть файл

@ -6,219 +6,11 @@
* Licensed under GPLv2 or later.
*/
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/clk/at91_pmc.h>
#include <asm/system_misc.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9n12.h>
#include <mach/cpu.h>
#include "board.h"
#include "soc.h"
#include "generic.h"
#include "sam9_smc.h"
#if defined(CONFIG_OLD_CLK_AT91)
#include "clock.h"
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
/*
* The peripheral clocks.
*/
static struct clk pioAB_clk = {
.name = "pioAB_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_PIOAB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioCD_clk = {
.name = "pioCD_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_PIOCD,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
.name = "usart0_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_USART0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
.name = "usart1_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_USART1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
.name = "usart2_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_USART2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart3_clk = {
.name = "usart3_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_USART3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
.name = "twi0_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_TWI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
.name = "twi1_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_TWI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc_clk = {
.name = "mci_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_MCI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
.name = "spi0_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_SPI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
.name = "spi1_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_SPI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk uart0_clk = {
.name = "uart0_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_UART0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk uart1_clk = {
.name = "uart1_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_UART1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tcb_clk = {
.name = "tcb_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_TCB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
.name = "pwm_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_PWM,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk adc_clk = {
.name = "adc_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_ADC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk dma_clk = {
.name = "dma_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_DMA,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk uhp_clk = {
.name = "uhp",
.pmc_mask = 1 << AT91SAM9N12_ID_UHP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk udp_clk = {
.name = "udp_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_UDP,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk lcdc_clk = {
.name = "lcdc_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_LCDC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc_clk = {
.name = "ssc_clk",
.pmc_mask = 1 << AT91SAM9N12_ID_SSC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk *periph_clocks[] __initdata = {
&pioAB_clk,
&pioCD_clk,
&usart0_clk,
&usart1_clk,
&usart2_clk,
&usart3_clk,
&twi0_clk,
&twi1_clk,
&mmc_clk,
&spi0_clk,
&spi1_clk,
&lcdc_clk,
&uart0_clk,
&uart1_clk,
&tcb_clk,
&pwm_clk,
&adc_clk,
&dma_clk,
&uhp_clk,
&udp_clk,
&ssc_clk,
};
static struct clk_lookup periph_clocks_lookups[] = {
/* lookup table for DT entries */
CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk),
CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk),
CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk),
CLKDEV_CON_DEV_ID(NULL, "f0010000.ssc", &ssc_clk),
CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
/* additional fake clock for macb_hclk */
CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &uhp_clk),
CLKDEV_CON_DEV_ID("ohci_clk", "500000.ohci", &uhp_clk),
CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
};
/*
* The two programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 1,
};
static void __init at91sam9n12_register_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
clk_register(&pck0);
clk_register(&pck1);
clkdev_add_table(periph_clocks_lookups,
ARRAY_SIZE(periph_clocks_lookups));
}
#else
#define at91sam9n12_register_clocks NULL
#endif
/* --------------------------------------------------------------------
* AT91SAM9N12 processor initialization
@ -236,6 +28,5 @@ static void __init at91sam9n12_initialize(void)
AT91_SOC_START(at91sam9n12)
.map_io = at91sam9n12_map_io,
.register_clocks = at91sam9n12_register_clocks,
.init = at91sam9n12_initialize,
AT91_SOC_END

311
arch/arm/mach-at91/at91sam9x5.c
Просмотреть файл

@ -6,317 +6,11 @@
* Licensed under GPLv2 or later.
*/
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/clk/at91_pmc.h>
#include <asm/system_misc.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91sam9x5.h>
#include <mach/cpu.h>
#include "board.h"
#include "soc.h"
#include "generic.h"
#include "sam9_smc.h"
#if defined(CONFIG_OLD_CLK_AT91)
#include "clock.h"
/* --------------------------------------------------------------------
* Clocks
* -------------------------------------------------------------------- */
/*
* The peripheral clocks.
*/
static struct clk pioAB_clk = {
.name = "pioAB_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_PIOAB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pioCD_clk = {
.name = "pioCD_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_PIOCD,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk smd_clk = {
.name = "smd_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_SMD,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart0_clk = {
.name = "usart0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_USART0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart1_clk = {
.name = "usart1_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_USART1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk usart2_clk = {
.name = "usart2_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_USART2,
.type = CLK_TYPE_PERIPHERAL,
};
/* USART3 clock - Only for sam9g25/sam9x25 */
static struct clk usart3_clk = {
.name = "usart3_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_USART3,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi0_clk = {
.name = "twi0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_TWI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi1_clk = {
.name = "twi1_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_TWI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk twi2_clk = {
.name = "twi2_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_TWI2,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc0_clk = {
.name = "mci0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_MCI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi0_clk = {
.name = "spi0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_SPI0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk spi1_clk = {
.name = "spi1_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_SPI1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk uart0_clk = {
.name = "uart0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_UART0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk uart1_clk = {
.name = "uart1_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_UART1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk tcb0_clk = {
.name = "tcb0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_TCB,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk pwm_clk = {
.name = "pwm_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_PWM,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk adc_clk = {
.name = "adc_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_ADC,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk adc_op_clk = {
.name = "adc_op_clk",
.type = CLK_TYPE_PERIPHERAL,
.rate_hz = 5000000,
};
static struct clk dma0_clk = {
.name = "dma0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_DMA0,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk dma1_clk = {
.name = "dma1_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_DMA1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk uhphs_clk = {
.name = "uhphs",
.pmc_mask = 1 << AT91SAM9X5_ID_UHPHS,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk udphs_clk = {
.name = "udphs_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_UDPHS,
.type = CLK_TYPE_PERIPHERAL,
};
/* emac0 clock - Only for sam9g25/sam9x25/sam9g35/sam9x35 */
static struct clk macb0_clk = {
.name = "pclk",
.pmc_mask = 1 << AT91SAM9X5_ID_EMAC0,
.type = CLK_TYPE_PERIPHERAL,
};
/* lcd clock - Only for sam9g15/sam9g35/sam9x35 */
static struct clk lcdc_clk = {
.name = "lcdc_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_LCDC,
.type = CLK_TYPE_PERIPHERAL,
};
/* isi clock - Only for sam9g25 */
static struct clk isi_clk = {
.name = "isi_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_ISI,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk mmc1_clk = {
.name = "mci1_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_MCI1,
.type = CLK_TYPE_PERIPHERAL,
};
/* emac1 clock - Only for sam9x25 */
static struct clk macb1_clk = {
.name = "pclk",
.pmc_mask = 1 << AT91SAM9X5_ID_EMAC1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk ssc_clk = {
.name = "ssc_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_SSC,
.type = CLK_TYPE_PERIPHERAL,
};
/* can0 clock - Only for sam9x35 */
static struct clk can0_clk = {
.name = "can0_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_CAN0,
.type = CLK_TYPE_PERIPHERAL,
};
/* can1 clock - Only for sam9x35 */
static struct clk can1_clk = {
.name = "can1_clk",
.pmc_mask = 1 << AT91SAM9X5_ID_CAN1,
.type = CLK_TYPE_PERIPHERAL,
};
static struct clk *periph_clocks[] __initdata = {
&pioAB_clk,
&pioCD_clk,
&smd_clk,
&usart0_clk,
&usart1_clk,
&usart2_clk,
&twi0_clk,
&twi1_clk,
&twi2_clk,
&mmc0_clk,
&spi0_clk,
&spi1_clk,
&uart0_clk,
&uart1_clk,
&tcb0_clk,
&pwm_clk,
&adc_clk,
&adc_op_clk,
&dma0_clk,
&dma1_clk,
&uhphs_clk,
&udphs_clk,
&mmc1_clk,
&ssc_clk,
// irq0
};
static struct clk_lookup periph_clocks_lookups[] = {
/* lookup table for DT entries */
CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk),
CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk),
CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk),
CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk),
CLKDEV_CON_DEV_ID("usart", "f8040000.serial", &uart0_clk),
CLKDEV_CON_DEV_ID("usart", "f8044000.serial", &uart1_clk),
CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk),
CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk),
CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk),
CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk),
CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk),
CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk),
CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk),
CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk),
/* additional fake clock for macb_hclk */
CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk),
CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk),
CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk),
CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk),
CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk),
CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk),
CLKDEV_CON_DEV_ID(NULL, "f8034000.pwm", &pwm_clk),
};
/*
* The two programmable clocks.
* You must configure pin multiplexing to bring these signals out.
*/
static struct clk pck0 = {
.name = "pck0",
.pmc_mask = AT91_PMC_PCK0,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 0,
};
static struct clk pck1 = {
.name = "pck1",
.pmc_mask = AT91_PMC_PCK1,
.type = CLK_TYPE_PROGRAMMABLE,
.id = 1,
};
static void __init at91sam9x5_register_clocks(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
clk_register(periph_clocks[i]);
clkdev_add_table(periph_clocks_lookups,
ARRAY_SIZE(periph_clocks_lookups));
if (cpu_is_at91sam9g25()
|| cpu_is_at91sam9x25())
clk_register(&usart3_clk);
if (cpu_is_at91sam9g25()
|| cpu_is_at91sam9x25()
|| cpu_is_at91sam9g35()
|| cpu_is_at91sam9x35())
clk_register(&macb0_clk);
if (cpu_is_at91sam9g15()
|| cpu_is_at91sam9g35()
|| cpu_is_at91sam9x35())
clk_register(&lcdc_clk);
if (cpu_is_at91sam9g25())
clk_register(&isi_clk);
if (cpu_is_at91sam9x25())
clk_register(&macb1_clk);
if (cpu_is_at91sam9x25()
|| cpu_is_at91sam9x35()) {
clk_register(&can0_clk);
clk_register(&can1_clk);
}
clk_register(&pck0);
clk_register(&pck1);
}
#else
#define at91sam9x5_register_clocks NULL
#endif
/* --------------------------------------------------------------------
* AT91SAM9x5 processor initialization
@ -338,6 +32,5 @@ static void __init at91sam9x5_initialize(void)
AT91_SOC_START(at91sam9x5)
.map_io = at91sam9x5_map_io,
.register_clocks = at91sam9x5_register_clocks,
.init = at91sam9x5_initialize,
AT91_SOC_END

99
arch/arm/mach-at91/board-1arm.c
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@ -1,99 +0,0 @@
/*
* linux/arch/arm/mach-at91/board-1arm.c
*
* Copyright (C) 2005 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/cpu.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
#include "gpio.h"
static void __init onearm_init_early(void)
{
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
/* Initialize processor: 18.432 MHz crystal */
at91_initialize(18432000);
}
static struct macb_platform_data __initdata onearm_eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 1,
};
static struct at91_usbh_data __initdata onearm_usbh_data = {
.ports = 1,
.vbus_pin = {-EINVAL, -EINVAL},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
static struct at91_udc_data __initdata onearm_udc_data = {
.vbus_pin = AT91_PIN_PC2,
.pullup_pin = AT91_PIN_PC3,
};
static void __init onearm_board_init(void)
{
/* Serial */
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
/* USART1 on ttyS2 (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
| ATMEL_UART_RI);
at91_add_device_serial();
/* Ethernet */
at91_add_device_eth(&onearm_eth_data);
/* USB Host */
at91_add_device_usbh(&onearm_usbh_data);
/* USB Device */
at91_add_device_udc(&onearm_udc_data);
}
MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
/* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
.init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = onearm_init_early,
.init_irq = at91_init_irq_default,
.init_machine = onearm_board_init,
MACHINE_END

167
arch/arm/mach-at91/board-carmeva.c
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@ -1,167 +0,0 @@
/*
* linux/arch/arm/mach-at91/board-carmeva.c
*
* Copyright (c) 2005 Peer Georgi
* Conitec Datasystems
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
#include "gpio.h"
static void __init carmeva_init_early(void)
{
/* Initialize processor: 20.000 MHz crystal */
at91_initialize(20000000);
}
static struct macb_platform_data __initdata carmeva_eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 1,
};
static struct at91_usbh_data __initdata carmeva_usbh_data = {
.ports = 2,
.vbus_pin = {-EINVAL, -EINVAL},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
static struct at91_udc_data __initdata carmeva_udc_data = {
.vbus_pin = AT91_PIN_PD12,
.pullup_pin = AT91_PIN_PD9,
};
/* FIXME: user dependent */
// static struct at91_cf_data __initdata carmeva_cf_data = {
// .det_pin = AT91_PIN_PB0,
// .rst_pin = AT91_PIN_PC5,
// .irq_pin = -EINVAL,
// .vcc_pin = -EINVAL,
// };
static struct mci_platform_data __initdata carmeva_mci0_data = {
.slot[0] = {
.bus_width = 4,
.detect_pin = AT91_PIN_PB10,
.wp_pin = AT91_PIN_PC14,
},
};
static struct spi_board_info carmeva_spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 10 * 1000 * 1000,
},
{ /* User accessible spi - cs1 (250KHz) */
.modalias = "spi-cs1",
.chip_select = 1,
.max_speed_hz = 250 * 1000,
},
{ /* User accessible spi - cs2 (1MHz) */
.modalias = "spi-cs2",
.chip_select = 2,
.max_speed_hz = 1 * 1000 * 1000,
},
{ /* User accessible spi - cs3 (10MHz) */
.modalias = "spi-cs3",
.chip_select = 3,
.max_speed_hz = 10 * 1000 * 1000,
},
};
static struct gpio_led carmeva_leds[] = {
{ /* "user led 1", LED9 */
.name = "led9",
.gpio = AT91_PIN_PA21,
.active_low = 1,
.default_trigger = "heartbeat",
},
{ /* "user led 2", LED10 */
.name = "led10",
.gpio = AT91_PIN_PA25,
.active_low = 1,
},
{ /* "user led 3", LED11 */
.name = "led11",
.gpio = AT91_PIN_PA26,
.active_low = 1,
},
{ /* "user led 4", LED12 */
.name = "led12",
.gpio = AT91_PIN_PA18,
.active_low = 1,
}
};
static void __init carmeva_board_init(void)
{
/* Serial */
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
| ATMEL_UART_RI);
at91_add_device_serial();
/* Ethernet */
at91_add_device_eth(&carmeva_eth_data);
/* USB Host */
at91_add_device_usbh(&carmeva_usbh_data);
/* USB Device */
at91_add_device_udc(&carmeva_udc_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
/* SPI */
at91_add_device_spi(carmeva_spi_devices, ARRAY_SIZE(carmeva_spi_devices));
/* Compact Flash */
// at91_add_device_cf(&carmeva_cf_data);
/* MMC */
at91_add_device_mci(0, &carmeva_mci0_data);
/* LEDs */
at91_gpio_leds(carmeva_leds, ARRAY_SIZE(carmeva_leds));
}
MACHINE_START(CARMEVA, "Carmeva")
/* Maintainer: Conitec Datasystems */
.init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = carmeva_init_early,
.init_irq = at91_init_irq_default,
.init_machine = carmeva_board_init,
MACHINE_END

189
arch/arm/mach-at91/board-cpuat91.c
Просмотреть файл

@ -1,189 +0,0 @@
/*
* linux/arch/arm/mach-at91/board-cpuat91.c
*
* Copyright (C) 2009 Eric Benard - eric@eukrea.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/plat-ram.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
#include <mach/cpu.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
#include "gpio.h"
static struct gpio_led cpuat91_leds[] = {
{
.name = "led1",
.default_trigger = "heartbeat",
.active_low = 1,
.gpio = AT91_PIN_PC0,
},
};
static void __init cpuat91_init_early(void)
{
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
/* Initialize processor: 18.432 MHz crystal */
at91_initialize(18432000);
}
static struct macb_platform_data __initdata cpuat91_eth_data = {
.phy_irq_pin = -EINVAL,
.is_rmii = 1,
};
static struct at91_usbh_data __initdata cpuat91_usbh_data = {
.ports = 1,
.vbus_pin = {-EINVAL, -EINVAL},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
static struct at91_udc_data __initdata cpuat91_udc_data = {
.vbus_pin = AT91_PIN_PC15,
.pullup_pin = AT91_PIN_PC14,
};
static struct mci_platform_data __initdata cpuat91_mci0_data = {
.slot[0] = {
.bus_width = 4,
.detect_pin = AT91_PIN_PC2,
.wp_pin = -EINVAL,
},
};
static struct physmap_flash_data cpuat91_flash_data = {
.width = 2,
};
static struct resource cpuat91_flash_resource = {
.start = AT91_CHIPSELECT_0,
.end = AT91_CHIPSELECT_0 + SZ_16M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device cpuat91_norflash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &cpuat91_flash_data,
},
.resource = &cpuat91_flash_resource,
.num_resources = 1,
};
#ifdef CONFIG_MTD_PLATRAM
struct platdata_mtd_ram at91_sram_pdata = {
.mapname = "SRAM",
.bankwidth = 2,
};
static struct resource at91_sram_resource[] = {
[0] = {
.start = AT91RM9200_SRAM_BASE,
.end = AT91RM9200_SRAM_BASE + AT91RM9200_SRAM_SIZE - 1,
.flags = IORESOURCE_MEM,
},
};
static struct platform_device at91_sram = {
.name = "mtd-ram",
.id = 0,
.resource = at91_sram_resource,
.num_resources = ARRAY_SIZE(at91_sram_resource),
.dev = {
.platform_data = &at91_sram_pdata,
},
};
#endif /* MTD_PLATRAM */
static struct platform_device *platform_devices[] __initdata = {
&cpuat91_norflash,
#ifdef CONFIG_MTD_PLATRAM
&at91_sram,
#endif /* CONFIG_MTD_PLATRAM */
};
static void __init cpuat91_board_init(void)
{
/* Serial */
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS |
ATMEL_UART_RTS);
/* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS |
ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
ATMEL_UART_DCD | ATMEL_UART_RI);
/* USART2 on ttyS3 (Rx, Tx) */
at91_register_uart(AT91RM9200_ID_US2, 3, 0);
/* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */
at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS |
ATMEL_UART_RTS);
at91_add_device_serial();
/* LEDs. */
at91_gpio_leds(cpuat91_leds, ARRAY_SIZE(cpuat91_leds));
/* Ethernet */
at91_add_device_eth(&cpuat91_eth_data);
/* USB Host */
at91_add_device_usbh(&cpuat91_usbh_data);
/* USB Device */
at91_add_device_udc(&cpuat91_udc_data);
/* MMC */
at91_add_device_mci(0, &cpuat91_mci0_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
/* Platform devices */
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}
MACHINE_START(CPUAT91, "Eukrea")
/* Maintainer: Eric Benard - EUKREA Electromatique */
.init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = cpuat91_init_early,
.init_irq = at91_init_irq_default,
.init_machine = cpuat91_board_init,
MACHINE_END

260
arch/arm/mach-at91/board-csb337.c
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@ -1,260 +0,0 @@
/*
* linux/arch/arm/mach-at91/board-csb337.c
*
* Copyright (C) 2005 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/mtd/physmap.h>
#include <linux/input.h>
#include <linux/gpio_keys.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
#include "gpio.h"
static void __init csb337_init_early(void)
{
/* Initialize processor: 3.6864 MHz crystal */
at91_initialize(3686400);
}
static struct macb_platform_data __initdata csb337_eth_data = {
.phy_irq_pin = AT91_PIN_PC2,
.is_rmii = 0,
/* The CSB337 bootloader stores the MAC the wrong-way around */
.rev_eth_addr = 1,
};
static struct at91_usbh_data __initdata csb337_usbh_data = {
.ports = 2,
.vbus_pin = {-EINVAL, -EINVAL},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
static struct at91_udc_data __initdata csb337_udc_data = {
.pullup_pin = AT91_PIN_PA24,
.vbus_pin = -EINVAL,
};
static struct i2c_board_info __initdata csb337_i2c_devices[] = {
{
I2C_BOARD_INFO("ds1307", 0x68),
},
};
static struct at91_cf_data __initdata csb337_cf_data = {
/*
* connector P4 on the CSB 337 mates to
* connector P8 on the CSB 300CF
*/
/* CSB337 specific */
.det_pin = AT91_PIN_PC3,
/* CSB300CF specific */
.irq_pin = AT91_PIN_PA19,
.vcc_pin = AT91_PIN_PD0,
.rst_pin = AT91_PIN_PD2,
};
static struct mci_platform_data __initdata csb337_mci0_data = {
.slot[0] = {
.bus_width = 4,
.detect_pin = AT91_PIN_PD5,
.wp_pin = AT91_PIN_PD6,
},
};
static struct spi_board_info csb337_spi_devices[] = {
{ /* CAN controller */
.modalias = "sak82c900",
.chip_select = 0,
.max_speed_hz = 6 * 1000 * 1000,
},
};
#define CSB_FLASH_BASE AT91_CHIPSELECT_0
#define CSB_FLASH_SIZE SZ_8M
static struct mtd_partition csb_flash_partitions[] = {
{
.name = "uMON flash",
.offset = 0,
.size = MTDPART_SIZ_FULL,
.mask_flags = MTD_WRITEABLE, /* read only */
}
};
static struct physmap_flash_data csb_flash_data = {
.width = 2,
.parts = csb_flash_partitions,
.nr_parts = ARRAY_SIZE(csb_flash_partitions),
};
static struct resource csb_flash_resources[] = {
{
.start = CSB_FLASH_BASE,
.end = CSB_FLASH_BASE + CSB_FLASH_SIZE - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device csb_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &csb_flash_data,
},
.resource = csb_flash_resources,
.num_resources = ARRAY_SIZE(csb_flash_resources),
};
/*
* GPIO Buttons (on CSB300)
*/
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
static struct gpio_keys_button csb300_buttons[] = {
{
.gpio = AT91_PIN_PB29,
.code = BTN_0,
.desc = "sw0",
.active_low = 1,
.wakeup = 1,
},
{
.gpio = AT91_PIN_PB28,
.code = BTN_1,
.desc = "sw1",
.active_low = 1,
.wakeup = 1,
},
{
.gpio = AT91_PIN_PA21,
.code = BTN_2,
.desc = "sw2",
.active_low = 1,
.wakeup = 1,
}
};
static struct gpio_keys_platform_data csb300_button_data = {
.buttons = csb300_buttons,
.nbuttons = ARRAY_SIZE(csb300_buttons),
};
static struct platform_device csb300_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &csb300_button_data,
}
};
static void __init csb300_add_device_buttons(void)
{
at91_set_gpio_input(AT91_PIN_PB29, 1); /* sw0 */
at91_set_deglitch(AT91_PIN_PB29, 1);
at91_set_gpio_input(AT91_PIN_PB28, 1); /* sw1 */
at91_set_deglitch(AT91_PIN_PB28, 1);
at91_set_gpio_input(AT91_PIN_PA21, 1); /* sw2 */
at91_set_deglitch(AT91_PIN_PA21, 1);
platform_device_register(&csb300_button_device);
}
#else
static void __init csb300_add_device_buttons(void) {}
#endif
static struct gpio_led csb_leds[] = {
{ /* "led0", yellow */
.name = "led0",
.gpio = AT91_PIN_PB2,
.active_low = 1,
.default_trigger = "heartbeat",
},
{ /* "led1", green */
.name = "led1",
.gpio = AT91_PIN_PB1,
.active_low = 1,
.default_trigger = "mmc0",
},
{ /* "led2", yellow */
.name = "led2",
.gpio = AT91_PIN_PB0,
.active_low = 1,
.default_trigger = "ide-disk",
}
};
static void __init csb337_board_init(void)
{
/* Serial */
/* DBGU on ttyS0 */
at91_register_uart(0, 0, 0);
at91_add_device_serial();
/* Ethernet */
at91_add_device_eth(&csb337_eth_data);
/* USB Host */
at91_add_device_usbh(&csb337_usbh_data);
/* USB Device */
at91_add_device_udc(&csb337_udc_data);
/* I2C */
at91_add_device_i2c(csb337_i2c_devices, ARRAY_SIZE(csb337_i2c_devices));
/* Compact Flash */
at91_set_gpio_input(AT91_PIN_PB22, 1); /* IOIS16 */
at91_add_device_cf(&csb337_cf_data);
/* SPI */
at91_add_device_spi(csb337_spi_devices, ARRAY_SIZE(csb337_spi_devices));
/* MMC */
at91_add_device_mci(0, &csb337_mci0_data);
/* NOR flash */
platform_device_register(&csb_flash);
/* LEDs */
at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
/* Switches on CSB300 */
csb300_add_device_buttons();
}
MACHINE_START(CSB337, "Cogent CSB337")
/* Maintainer: Bill Gatliff */
.init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = csb337_init_early,
.init_irq = at91_init_irq_default,
.init_machine = csb337_board_init,
MACHINE_END

142
arch/arm/mach-at91/board-csb637.c
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@ -1,142 +0,0 @@
/*
* linux/arch/arm/mach-at91/board-csb637.c
*
* Copyright (C) 2005 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
#include "gpio.h"
static void __init csb637_init_early(void)
{
/* Initialize processor: 3.6864 MHz crystal */
at91_initialize(3686400);
}
static struct macb_platform_data __initdata csb637_eth_data = {
.phy_irq_pin = AT91_PIN_PC0,
.is_rmii = 0,
};
static struct at91_usbh_data __initdata csb637_usbh_data = {
.ports = 2,
.vbus_pin = {-EINVAL, -EINVAL},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
static struct at91_udc_data __initdata csb637_udc_data = {
.vbus_pin = AT91_PIN_PB28,
.pullup_pin = AT91_PIN_PB1,
};
#define CSB_FLASH_BASE AT91_CHIPSELECT_0
#define CSB_FLASH_SIZE SZ_16M
static struct mtd_partition csb_flash_partitions[] = {
{
.name = "uMON flash",
.offset = 0,
.size = MTDPART_SIZ_FULL,
.mask_flags = MTD_WRITEABLE, /* read only */
}
};
static struct physmap_flash_data csb_flash_data = {
.width = 2,
.parts = csb_flash_partitions,
.nr_parts = ARRAY_SIZE(csb_flash_partitions),
};
static struct resource csb_flash_resources[] = {
{
.start = CSB_FLASH_BASE,
.end = CSB_FLASH_BASE + CSB_FLASH_SIZE - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device csb_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &csb_flash_data,
},
.resource = csb_flash_resources,
.num_resources = ARRAY_SIZE(csb_flash_resources),
};
static struct gpio_led csb_leds[] = {
{ /* "d1", red */
.name = "d1",
.gpio = AT91_PIN_PB2,
.active_low = 1,
.default_trigger = "heartbeat",
},
};
static void __init csb637_board_init(void)
{
/* LED(s) */
at91_gpio_leds(csb_leds, ARRAY_SIZE(csb_leds));
/* Serial */
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
at91_add_device_serial();
/* Ethernet */
at91_add_device_eth(&csb637_eth_data);
/* USB Host */
at91_add_device_usbh(&csb637_usbh_data);
/* USB Device */
at91_add_device_udc(&csb637_udc_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
/* SPI */
at91_add_device_spi(NULL, 0);
/* NOR flash */
platform_device_register(&csb_flash);
}
MACHINE_START(CSB637, "Cogent CSB637")
/* Maintainer: Bill Gatliff */
.init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = csb637_init_early,
.init_irq = at91_init_irq_default,
.init_machine = csb637_board_init,
MACHINE_END

1
arch/arm/mach-at91/board-dt-rm9200.c
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@ -22,7 +22,6 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include "at91_aic.h"
#include "generic.h"
static void __init at91rm9200_dt_timer_init(void)

1
arch/arm/mach-at91/board-dt-sam9.c
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@ -21,7 +21,6 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"

1
arch/arm/mach-at91/board-dt-sama5.c
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@ -24,7 +24,6 @@
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include "at91_aic.h"
#include "generic.h"
static void __init sama5_dt_device_init(void)

126
arch/arm/mach-at91/board-eb9200.c
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@ -1,126 +0,0 @@
/*
* linux/arch/arm/mach-at91/board-eb9200.c
*
* Copyright (C) 2005 SAN People, adapted for ATEB9200 from Embest
* by Andrew Patrikalakis
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/device.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
#include "gpio.h"
static void __init eb9200_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91_initialize(18432000);
}
static struct macb_platform_data __initdata eb9200_eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 1,
};
static struct at91_usbh_data __initdata eb9200_usbh_data = {
.ports = 2,
.vbus_pin = {-EINVAL, -EINVAL},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
static struct at91_udc_data __initdata eb9200_udc_data = {
.vbus_pin = AT91_PIN_PD4,
.pullup_pin = AT91_PIN_PD5,
};
static struct at91_cf_data __initdata eb9200_cf_data = {
.irq_pin = -EINVAL,
.det_pin = AT91_PIN_PB0,
.vcc_pin = -EINVAL,
.rst_pin = AT91_PIN_PC5,
};
static struct mci_platform_data __initdata eb9200_mci0_data = {
.slot[0] = {
.bus_width = 4,
.detect_pin = -EINVAL,
.wp_pin = -EINVAL,
},
};
static struct i2c_board_info __initdata eb9200_i2c_devices[] = {
{
I2C_BOARD_INFO("24c512", 0x50),
},
};
static void __init eb9200_board_init(void)
{
/* Serial */
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
| ATMEL_UART_RI);
/* USART2 on ttyS2. (Rx, Tx) - IRDA */
at91_register_uart(AT91RM9200_ID_US2, 2, 0);
at91_add_device_serial();
/* Ethernet */
at91_add_device_eth(&eb9200_eth_data);
/* USB Host */
at91_add_device_usbh(&eb9200_usbh_data);
/* USB Device */
at91_add_device_udc(&eb9200_udc_data);
/* I2C */
at91_add_device_i2c(eb9200_i2c_devices, ARRAY_SIZE(eb9200_i2c_devices));
/* Compact Flash */
at91_add_device_cf(&eb9200_cf_data);
/* SPI */
at91_add_device_spi(NULL, 0);
/* MMC */
/* only supports 1 or 4 bit interface, not wired through to SPI */
at91_add_device_mci(0, &eb9200_mci0_data);
}
MACHINE_START(ATEB9200, "Embest ATEB9200")
.init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = eb9200_init_early,
.init_irq = at91_init_irq_default,
.init_machine = eb9200_board_init,
MACHINE_END

191
arch/arm/mach-at91/board-ecbat91.c
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@ -1,191 +0,0 @@
/*
* linux/arch/arm/mach-at91rm9200/board-ecbat91.c
* Copyright (C) 2007 emQbit.com.
*
* We started from board-dk.c, which is Copyright (C) 2005 SAN People.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/flash.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/cpu.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
#include "gpio.h"
static void __init ecb_at91init_early(void)
{
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
/* Initialize processor: 18.432 MHz crystal */
at91_initialize(18432000);
}
static struct macb_platform_data __initdata ecb_at91eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 0,
};
static struct at91_usbh_data __initdata ecb_at91usbh_data = {
.ports = 1,
.vbus_pin = {-EINVAL, -EINVAL},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
static struct mci_platform_data __initdata ecbat91_mci0_data = {
.slot[0] = {
.bus_width = 4,
.detect_pin = -EINVAL,
.wp_pin = -EINVAL,
},
};
#if defined(CONFIG_MTD_DATAFLASH)
static struct mtd_partition __initdata my_flash0_partitions[] =
{
{ /* 0x8400 */
.name = "Darrell-loader",
.offset = 0,
.size = 12 * 1056,
},
{
.name = "U-boot",
.offset = MTDPART_OFS_NXTBLK,
.size = 110 * 1056,
},
{ /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
.name = "UBoot-env",
.offset = MTDPART_OFS_NXTBLK,
.size = 8 * 1056,
},
{ /* 1336 (167 blocks) pages * 1056 bytes = 0x158700 bytes */
.name = "Kernel",
.offset = MTDPART_OFS_NXTBLK,
.size = 1534 * 1056,
},
{ /* 190200 - jffs2 root filesystem */
.name = "Filesystem",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL, /* 26 sectors */
}
};
static struct flash_platform_data __initdata my_flash0_platform = {
.name = "Removable flash card",
.parts = my_flash0_partitions,
.nr_parts = ARRAY_SIZE(my_flash0_partitions)
};
#endif
static struct spi_board_info __initdata ecb_at91spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 10 * 1000 * 1000,
.bus_num = 0,
#if defined(CONFIG_MTD_DATAFLASH)
.platform_data = &my_flash0_platform,
#endif
},
{ /* User accessible spi - cs1 (250KHz) */
.modalias = "spi-cs1",
.chip_select = 1,
.max_speed_hz = 250 * 1000,
},
{ /* User accessible spi - cs2 (1MHz) */
.modalias = "spi-cs2",
.chip_select = 2,
.max_speed_hz = 1 * 1000 * 1000,
},
{ /* User accessible spi - cs3 (10MHz) */
.modalias = "spi-cs3",
.chip_select = 3,
.max_speed_hz = 10 * 1000 * 1000,
},
};
/*
* LEDs
*/
static struct gpio_led ecb_leds[] = {
{ /* D1 */
.name = "led1",
.gpio = AT91_PIN_PC7,
.active_low = 1,
.default_trigger = "heartbeat",
}
};
static void __init ecb_at91board_init(void)
{
/* Serial */
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1. (Rx & Tx only) */
at91_register_uart(AT91RM9200_ID_US0, 1, 0);
at91_add_device_serial();
/* Ethernet */
at91_add_device_eth(&ecb_at91eth_data);
/* USB Host */
at91_add_device_usbh(&ecb_at91usbh_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
/* MMC */
at91_add_device_mci(0, &ecbat91_mci0_data);
/* SPI */
at91_add_device_spi(ecb_at91spi_devices, ARRAY_SIZE(ecb_at91spi_devices));
/* LEDs */
at91_gpio_leds(ecb_leds, ARRAY_SIZE(ecb_leds));
}
MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
/* Maintainer: emQbit.com */
.init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = ecb_at91init_early,
.init_irq = at91_init_irq_default,
.init_machine = ecb_at91board_init,
MACHINE_END

160
arch/arm/mach-at91/board-eco920.c
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@ -1,160 +0,0 @@
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
#include <mach/cpu.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
#include "gpio.h"
static void __init eco920_init_early(void)
{
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
at91_initialize(18432000);
}
static struct macb_platform_data __initdata eco920_eth_data = {
.phy_irq_pin = AT91_PIN_PC2,
.is_rmii = 1,
};
static struct at91_usbh_data __initdata eco920_usbh_data = {
.ports = 1,
.vbus_pin = {-EINVAL, -EINVAL},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
static struct at91_udc_data __initdata eco920_udc_data = {
.vbus_pin = AT91_PIN_PB12,
.pullup_pin = AT91_PIN_PB13,
};
static struct mci_platform_data __initdata eco920_mci0_data = {
.slot[0] = {
.bus_width = 1,
.detect_pin = -EINVAL,
.wp_pin = -EINVAL,
},
};
static struct physmap_flash_data eco920_flash_data = {
.width = 2,
};
static struct resource eco920_flash_resource = {
.start = 0x11000000,
.end = 0x11ffffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device eco920_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &eco920_flash_data,
},
.resource = &eco920_flash_resource,
.num_resources = 1,
};
static struct spi_board_info eco920_spi_devices[] = {
{ /* CAN controller */
.modalias = "tlv5638",
.chip_select = 3,
.max_speed_hz = 20 * 1000 * 1000,
.mode = SPI_CPHA,
},
};
/*
* LEDs
*/
static struct gpio_led eco920_leds[] = {
{ /* D1 */
.name = "led1",
.gpio = AT91_PIN_PB0,
.active_low = 1,
.default_trigger = "heartbeat",
},
{ /* D2 */
.name = "led2",
.gpio = AT91_PIN_PB1,
.active_low = 1,
.default_trigger = "timer",
}
};
static void __init eco920_board_init(void)
{
/* DBGU on ttyS0. (Rx & Tx only */
at91_register_uart(0, 0, 0);
at91_add_device_serial();
at91_add_device_eth(&eco920_eth_data);
at91_add_device_usbh(&eco920_usbh_data);
at91_add_device_udc(&eco920_udc_data);
at91_add_device_mci(0, &eco920_mci0_data);
platform_device_register(&eco920_flash);
at91_ramc_write(0, AT91_SMC_CSR(7), AT91_SMC_RWHOLD_(1)
| AT91_SMC_RWSETUP_(1)
| AT91_SMC_DBW_8
| AT91_SMC_WSEN
| AT91_SMC_NWS_(15));
at91_set_A_periph(AT91_PIN_PC6, 1);
at91_set_gpio_input(AT91_PIN_PA23, 0);
at91_set_deglitch(AT91_PIN_PA23, 1);
/* Initialization of the Static Memory Controller for Chip Select 3 */
at91_ramc_write(0, AT91_SMC_CSR(3),
AT91_SMC_DBW_16 | /* 16 bit */
AT91_SMC_WSEN |
AT91_SMC_NWS_(5) | /* wait states */
AT91_SMC_TDF_(1) /* float time */
);
at91_add_device_spi(eco920_spi_devices, ARRAY_SIZE(eco920_spi_devices));
/* LEDs */
at91_gpio_leds(eco920_leds, ARRAY_SIZE(eco920_leds));
}
MACHINE_START(ECO920, "eco920")
/* Maintainer: Sascha Hauer */
.init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = eco920_init_early,
.init_irq = at91_init_irq_default,
.init_machine = eco920_board_init,
MACHINE_END

113
arch/arm/mach-at91/board-kafa.c
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@ -1,113 +0,0 @@
/*
* linux/arch/arm/mach-at91/board-kafa.c
*
* Copyright (C) 2006 Sperry-Sun
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/cpu.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
#include "gpio.h"
static void __init kafa_init_early(void)
{
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
/* Initialize processor: 18.432 MHz crystal */
at91_initialize(18432000);
}
static struct macb_platform_data __initdata kafa_eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 0,
};
static struct at91_usbh_data __initdata kafa_usbh_data = {
.ports = 1,
.vbus_pin = {-EINVAL, -EINVAL},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
static struct at91_udc_data __initdata kafa_udc_data = {
.vbus_pin = AT91_PIN_PB6,
.pullup_pin = AT91_PIN_PB7,
};
/*
* LEDs
*/
static struct gpio_led kafa_leds[] = {
{ /* D1 */
.name = "led1",
.gpio = AT91_PIN_PB4,
.active_low = 1,
.default_trigger = "heartbeat",
},
};
static void __init kafa_board_init(void)
{
/* Serial */
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1 (Rx, Tx, CTS, RTS) */
at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS);
at91_add_device_serial();
/* Ethernet */
at91_add_device_eth(&kafa_eth_data);
/* USB Host */
at91_add_device_usbh(&kafa_usbh_data);
/* USB Device */
at91_add_device_udc(&kafa_udc_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
/* SPI */
at91_add_device_spi(NULL, 0);
/* LEDs */
at91_gpio_leds(kafa_leds, ARRAY_SIZE(kafa_leds));
}
MACHINE_START(KAFA, "Sperry-Sun KAFA")
/* Maintainer: Sergei Sharonov */
.init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = kafa_init_early,
.init_irq = at91_init_irq_default,
.init_machine = kafa_board_init,
MACHINE_END

159
arch/arm/mach-at91/board-kb9202.c
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@ -1,159 +0,0 @@
/*
* linux/arch/arm/mach-at91/board-kb9202.c
*
* Copyright (c) 2005 kb_admin
* KwikByte, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/cpu.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
#include "gpio.h"
static void __init kb9202_init_early(void)
{
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
/* Initialize processor: 10 MHz crystal */
at91_initialize(10000000);
}
static struct macb_platform_data __initdata kb9202_eth_data = {
.phy_irq_pin = AT91_PIN_PB29,
.is_rmii = 0,
};
static struct at91_usbh_data __initdata kb9202_usbh_data = {
.ports = 1,
.vbus_pin = {-EINVAL, -EINVAL},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
static struct at91_udc_data __initdata kb9202_udc_data = {
.vbus_pin = AT91_PIN_PB24,
.pullup_pin = AT91_PIN_PB22,
};
static struct mci_platform_data __initdata kb9202_mci0_data = {
.slot[0] = {
.bus_width = 4,
.detect_pin = AT91_PIN_PB2,
.wp_pin = -EINVAL,
},
};
static struct mtd_partition __initdata kb9202_nand_partition[] = {
{
.name = "nand_fs",
.offset = 0,
.size = MTDPART_SIZ_FULL,
},
};
static struct atmel_nand_data __initdata kb9202_nand_data = {
.ale = 22,
.cle = 21,
.det_pin = -EINVAL,
.rdy_pin = AT91_PIN_PC29,
.enable_pin = AT91_PIN_PC28,
.ecc_mode = NAND_ECC_SOFT,
.parts = kb9202_nand_partition,
.num_parts = ARRAY_SIZE(kb9202_nand_partition),
};
/*
* LEDs
*/
static struct gpio_led kb9202_leds[] = {
{ /* D1 */
.name = "led1",
.gpio = AT91_PIN_PC19,
.active_low = 1,
.default_trigger = "heartbeat",
},
{ /* D2 */
.name = "led2",
.gpio = AT91_PIN_PC18,
.active_low = 1,
.default_trigger = "timer",
}
};
static void __init kb9202_board_init(void)
{
/* Serial */
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1 (Rx & Tx only) */
at91_register_uart(AT91RM9200_ID_US0, 1, 0);
/* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */
at91_register_uart(AT91RM9200_ID_US1, 2, 0);
/* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */
at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
at91_add_device_serial();
/* Ethernet */
at91_add_device_eth(&kb9202_eth_data);
/* USB Host */
at91_add_device_usbh(&kb9202_usbh_data);
/* USB Device */
at91_add_device_udc(&kb9202_udc_data);
/* MMC */
at91_add_device_mci(0, &kb9202_mci0_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
/* SPI */
at91_add_device_spi(NULL, 0);
/* NAND */
at91_add_device_nand(&kb9202_nand_data);
/* LEDs */
at91_gpio_leds(kb9202_leds, ARRAY_SIZE(kb9202_leds));
}
MACHINE_START(KB9200, "KB920x")
/* Maintainer: KwikByte, Inc. */
.init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = kb9202_init_early,
.init_irq = at91_init_irq_default,
.init_machine = kb9202_board_init,
MACHINE_END

129
arch/arm/mach-at91/board-picotux200.c
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@ -1,129 +0,0 @@
/*
* linux/arch/arm/mach-at91/board-picotux200.c
*
* Copyright (C) 2005 SAN People
* Copyright (C) 2007 Kleinhenz Elektronik GmbH
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/mtd/physmap.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
#include "gpio.h"
static void __init picotux200_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91_initialize(18432000);
}
static struct macb_platform_data __initdata picotux200_eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 1,
};
static struct at91_usbh_data __initdata picotux200_usbh_data = {
.ports = 1,
.vbus_pin = {-EINVAL, -EINVAL},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
static struct mci_platform_data __initdata picotux200_mci0_data = {
.slot[0] = {
.bus_width = 4,
.detect_pin = AT91_PIN_PB27,
.wp_pin = AT91_PIN_PA17,
},
};
#define PICOTUX200_FLASH_BASE AT91_CHIPSELECT_0
#define PICOTUX200_FLASH_SIZE SZ_4M
static struct physmap_flash_data picotux200_flash_data = {
.width = 2,
};
static struct resource picotux200_flash_resource = {
.start = PICOTUX200_FLASH_BASE,
.end = PICOTUX200_FLASH_BASE + PICOTUX200_FLASH_SIZE - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device picotux200_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &picotux200_flash_data,
},
.resource = &picotux200_flash_resource,
.num_resources = 1,
};
static void __init picotux200_board_init(void)
{
/* Serial */
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
| ATMEL_UART_RI);
at91_add_device_serial();
/* Ethernet */
at91_add_device_eth(&picotux200_eth_data);
/* USB Host */
at91_add_device_usbh(&picotux200_usbh_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
/* MMC */
at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
at91_add_device_mci(0, &picotux200_mci0_data);
/* NOR Flash */
platform_device_register(&picotux200_flash);
}
MACHINE_START(PICOTUX2XX, "picotux 200")
/* Maintainer: Kleinhenz Elektronik GmbH */
.init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = picotux200_init_early,
.init_irq = at91_init_irq_default,
.init_machine = picotux200_board_init,
MACHINE_END

196
arch/arm/mach-at91/board-rm9200ek.c
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@ -1,196 +0,0 @@
/*
* linux/arch/arm/mach-at91/board-rm9200ek.c
*
* Copyright (C) 2005 SAN People
*
* Epson S1D framebuffer glue code is:
* Copyright (C) 2005 Thibaut VARENE <varenet@parisc-linux.org>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/mtd/physmap.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
#include "gpio.h"
static void __init ek_init_early(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91_initialize(18432000);
}
static struct macb_platform_data __initdata ek_eth_data = {
.phy_irq_pin = AT91_PIN_PC4,
.is_rmii = 1,
};
static struct at91_usbh_data __initdata ek_usbh_data = {
.ports = 2,
.vbus_pin = {-EINVAL, -EINVAL},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
static struct at91_udc_data __initdata ek_udc_data = {
.vbus_pin = AT91_PIN_PD4,
.pullup_pin = AT91_PIN_PD5,
};
#ifndef CONFIG_MTD_AT91_DATAFLASH_CARD
static struct mci_platform_data __initdata ek_mci0_data = {
.slot[0] = {
.bus_width = 4,
.detect_pin = AT91_PIN_PB27,
.wp_pin = AT91_PIN_PA17,
}
};
#endif
static struct spi_board_info ek_spi_devices[] = {
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
},
#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
{ /* DataFlash card */
.modalias = "mtd_dataflash",
.chip_select = 3,
.max_speed_hz = 15 * 1000 * 1000,
},
#endif
};
static struct i2c_board_info __initdata ek_i2c_devices[] = {
{
I2C_BOARD_INFO("ics1523", 0x26),
},
{
I2C_BOARD_INFO("dac3550", 0x4d),
}
};
#define EK_FLASH_BASE AT91_CHIPSELECT_0
#define EK_FLASH_SIZE SZ_8M
static struct physmap_flash_data ek_flash_data = {
.width = 2,
};
static struct resource ek_flash_resource = {
.start = EK_FLASH_BASE,
.end = EK_FLASH_BASE + EK_FLASH_SIZE - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device ek_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &ek_flash_data,
},
.resource = &ek_flash_resource,
.num_resources = 1,
};
static struct gpio_led ek_leds[] = {
{ /* "user led 1", DS2 */
.name = "green",
.gpio = AT91_PIN_PB0,
.active_low = 1,
.default_trigger = "mmc0",
},
{ /* "user led 2", DS4 */
.name = "yellow",
.gpio = AT91_PIN_PB1,
.active_low = 1,
.default_trigger = "heartbeat",
},
{ /* "user led 3", DS6 */
.name = "red",
.gpio = AT91_PIN_PB2,
.active_low = 1,
}
};
static void __init ek_board_init(void)
{
/* Serial */
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
| ATMEL_UART_RI);
at91_add_device_serial();
/* Ethernet */
at91_add_device_eth(&ek_eth_data);
/* USB Host */
at91_add_device_usbh(&ek_usbh_data);
/* USB Device */
at91_add_device_udc(&ek_udc_data);
at91_set_multi_drive(ek_udc_data.pullup_pin, 1); /* pullup_pin is connected to reset */
/* I2C */
at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
/* SPI */
at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
#ifdef CONFIG_MTD_AT91_DATAFLASH_CARD
/* DataFlash card */
at91_set_gpio_output(AT91_PIN_PB22, 0);
#else
/* MMC */
at91_set_gpio_output(AT91_PIN_PB22, 1); /* this MMC card slot can optionally use SPI signaling (CS3). */
at91_add_device_mci(0, &ek_mci0_data);
#endif
/* NOR Flash */
platform_device_register(&ek_flash);
/* LEDs */
at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
/* VGA */
// ek_add_device_video();
}
MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
/* Maintainer: SAN People/Atmel */
.init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = ek_init_early,
.init_irq = at91_init_irq_default,
.init_machine = ek_board_init,
MACHINE_END

597
arch/arm/mach-at91/board-yl-9200.c
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@ -1,597 +0,0 @@
/*
* linux/arch/arm/mach-at91/board-yl-9200.c
*
* Adapted from various board files in arch/arm/mach-at91
*
* Modifications for YL-9200 platform:
* Copyright (C) 2007 S. Birtles
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
#include <linux/mtd/physmap.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/at91rm9200_mc.h>
#include <mach/at91_ramc.h>
#include <mach/cpu.h>
#include "at91_aic.h"
#include "board.h"
#include "generic.h"
#include "gpio.h"
static void __init yl9200_init_early(void)
{
/* Set cpu type: PQFP */
at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
/* Initialize processor: 18.432 MHz crystal */
at91_initialize(18432000);
}
/*
* LEDs
*/
static struct gpio_led yl9200_leds[] = {
{ /* D2 */
.name = "led2",
.gpio = AT91_PIN_PB17,
.active_low = 1,
.default_trigger = "timer",
},
{ /* D3 */
.name = "led3",
.gpio = AT91_PIN_PB16,
.active_low = 1,
.default_trigger = "heartbeat",
},
{ /* D4 */
.name = "led4",
.gpio = AT91_PIN_PB15,
.active_low = 1,
},
{ /* D5 */
.name = "led5",
.gpio = AT91_PIN_PB8,
.active_low = 1,
}
};
/*
* Ethernet
*/
static struct macb_platform_data __initdata yl9200_eth_data = {
.phy_irq_pin = AT91_PIN_PB28,
.is_rmii = 1,
};
/*
* USB Host
*/
static struct at91_usbh_data __initdata yl9200_usbh_data = {
.ports = 1, /* PQFP version of AT91RM9200 */
.vbus_pin = {-EINVAL, -EINVAL},
.overcurrent_pin= {-EINVAL, -EINVAL},
};
/*
* USB Device
*/
static struct at91_udc_data __initdata yl9200_udc_data = {
.pullup_pin = AT91_PIN_PC4,
.vbus_pin = AT91_PIN_PC5,
.pullup_active_low = 1, /* Active Low due to PNP transistor (pg 7) */
};
/*
* MMC
*/
static struct mci_platform_data __initdata yl9200_mci0_data = {
.slot[0] = {
.bus_width = 4,
.detect_pin = AT91_PIN_PB9,
.wp_pin = -EINVAL,
},
};
/*
* NAND Flash
*/
static struct mtd_partition __initdata yl9200_nand_partition[] = {
{
.name = "AT91 NAND partition 1, boot",
.offset = 0,
.size = SZ_256K
},
{
.name = "AT91 NAND partition 2, kernel",
.offset = MTDPART_OFS_NXTBLK,
.size = (2 * SZ_1M) - SZ_256K
},
{
.name = "AT91 NAND partition 3, filesystem",
.offset = MTDPART_OFS_NXTBLK,
.size = 14 * SZ_1M
},
{
.name = "AT91 NAND partition 4, storage",
.offset = MTDPART_OFS_NXTBLK,
.size = SZ_16M
},
{
.name = "AT91 NAND partition 5, ext-fs",
.offset = MTDPART_OFS_NXTBLK,
.size = SZ_32M
}
};
static struct atmel_nand_data __initdata yl9200_nand_data = {
.ale = 6,
.cle = 7,
.det_pin = -EINVAL,
.rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */
.enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */
.ecc_mode = NAND_ECC_SOFT,
.parts = yl9200_nand_partition,
.num_parts = ARRAY_SIZE(yl9200_nand_partition),
};
/*
* NOR Flash
*/
#define YL9200_FLASH_BASE AT91_CHIPSELECT_0
#define YL9200_FLASH_SIZE SZ_16M
static struct mtd_partition yl9200_flash_partitions[] = {
{
.name = "Bootloader",
.offset = 0,
.size = SZ_256K,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
{
.name = "Kernel",
.offset = MTDPART_OFS_NXTBLK,
.size = (2 * SZ_1M) - SZ_256K
},
{
.name = "Filesystem",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL
}
};
static struct physmap_flash_data yl9200_flash_data = {
.width = 2,
.parts = yl9200_flash_partitions,
.nr_parts = ARRAY_SIZE(yl9200_flash_partitions),
};
static struct resource yl9200_flash_resources[] = {
{
.start = YL9200_FLASH_BASE,
.end = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
.flags = IORESOURCE_MEM,
}
};
static struct platform_device yl9200_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &yl9200_flash_data,
},
.resource = yl9200_flash_resources,
.num_resources = ARRAY_SIZE(yl9200_flash_resources),
};
/*
* I2C (TWI)
*/
static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
{ /* EEPROM */
I2C_BOARD_INFO("24c128", 0x50),
}
};
/*
* GPIO Buttons
*/
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
static struct gpio_keys_button yl9200_buttons[] = {
{
.gpio = AT91_PIN_PA24,
.code = BTN_2,
.desc = "SW2",
.active_low = 1,
.wakeup = 1,
},
{
.gpio = AT91_PIN_PB1,
.code = BTN_3,
.desc = "SW3",
.active_low = 1,
.wakeup = 1,
},
{
.gpio = AT91_PIN_PB2,
.code = BTN_4,
.desc = "SW4",
.active_low = 1,
.wakeup = 1,
},
{
.gpio = AT91_PIN_PB6,
.code = BTN_5,
.desc = "SW5",
.active_low = 1,
.wakeup = 1,
}
};
static struct gpio_keys_platform_data yl9200_button_data = {
.buttons = yl9200_buttons,
.nbuttons = ARRAY_SIZE(yl9200_buttons),
};
static struct platform_device yl9200_button_device = {
.name = "gpio-keys",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &yl9200_button_data,
}
};
static void __init yl9200_add_device_buttons(void)
{
at91_set_gpio_input(AT91_PIN_PA24, 1); /* SW2 */
at91_set_deglitch(AT91_PIN_PA24, 1);
at91_set_gpio_input(AT91_PIN_PB1, 1); /* SW3 */
at91_set_deglitch(AT91_PIN_PB1, 1);
at91_set_gpio_input(AT91_PIN_PB2, 1); /* SW4 */
at91_set_deglitch(AT91_PIN_PB2, 1);
at91_set_gpio_input(AT91_PIN_PB6, 1); /* SW5 */
at91_set_deglitch(AT91_PIN_PB6, 1);
/* Enable buttons (Sheet 5) */
at91_set_gpio_output(AT91_PIN_PB7, 1);
platform_device_register(&yl9200_button_device);
}
#else
static void __init yl9200_add_device_buttons(void) {}
#endif
/*
* Touchscreen
*/
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
static int ads7843_pendown_state(void)
{
return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
}
static struct ads7846_platform_data ads_info = {
.model = 7843,
.x_min = 150,
.x_max = 3830,
.y_min = 190,
.y_max = 3830,
.vref_delay_usecs = 100,
/* For a 8" touch-screen */
// .x_plate_ohms = 603,
// .y_plate_ohms = 332,
/* For a 10.4" touch-screen */
// .x_plate_ohms = 611,
// .y_plate_ohms = 325,
.x_plate_ohms = 576,
.y_plate_ohms = 366,
.pressure_max = 15000, /* generally nonsense on the 7843 */
.debounce_max = 1,
.debounce_rep = 0,
.debounce_tol = (~0),
.get_pendown_state = ads7843_pendown_state,
};
static void __init yl9200_add_device_ts(void)
{
at91_set_gpio_input(AT91_PIN_PB11, 1); /* Touchscreen interrupt pin */
at91_set_gpio_input(AT91_PIN_PB10, 1); /* Touchscreen BUSY signal - not used! */
}
#else
static void __init yl9200_add_device_ts(void) {}
#endif
/*
* SPI devices
*/
static struct spi_board_info yl9200_spi_devices[] = {
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
{ /* Touchscreen */
.modalias = "ads7846",
.chip_select = 0,
.max_speed_hz = 5000 * 26,
.platform_data = &ads_info,
.irq = AT91_PIN_PB11,
},
#endif
{ /* CAN */
.modalias = "mcp2510",
.chip_select = 1,
.max_speed_hz = 25000 * 26,
.irq = AT91_PIN_PC0,
}
};
/*
* LCD / VGA
*
* EPSON S1D13806 FB (discontinued chip)
* EPSON S1D13506 FB
*/
#if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
#include <video/s1d13xxxfb.h>
static void yl9200_init_video(void)
{
/* NWAIT Signal */
at91_set_A_periph(AT91_PIN_PC6, 0);
/* Initialization of the Static Memory Controller for Chip Select 2 */
at91_ramc_write(0, AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
| AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
| AT91_SMC_TDF_(0x100) /* float time */
);
}
static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
{
{S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
{S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
{S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
{S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
{S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
{S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
{S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
{S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
{S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
{S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
{S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
{S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
{S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
{S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
{S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
{S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
{S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
{S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
{S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
{S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
{S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
{S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
{S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
{S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
{S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
{S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
{S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
{S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
{S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
{S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
{S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
{S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
{S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
{S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
{S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
{S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
{S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
{S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
{S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
{S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
{S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
{S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
{S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
{S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
{S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
{S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
{S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
{S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
{S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
{S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
{S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
{S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
{S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
{S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
{S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
{S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
{S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
{S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
{S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
{S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
{S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
{S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
{S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
{S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
{S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
{S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
{S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
{S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
{S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
{S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
{S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
{S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
{S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
{S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
{S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
{S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
{S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
{S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
{S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
{S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
{S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
{S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
{S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
{S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
{S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
{S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
{S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
{S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
{S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
{S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
{S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
{S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
{S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
{S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
{S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
{S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
{S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
{S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
{S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
{S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
{S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
{S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
{S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
{S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
{S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
};
static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
.initregs = yl9200_s1dfb_initregs,
.initregssize = ARRAY_SIZE(yl9200_s1dfb_initregs),
.platform_init_video = yl9200_init_video,
};
#define YL9200_FB_REG_BASE AT91_CHIPSELECT_7
#define YL9200_FB_VMEM_BASE YL9200_FB_REG_BASE + SZ_2M
#define YL9200_FB_VMEM_SIZE SZ_2M
static struct resource yl9200_s1dfb_resource[] = {
[0] = { /* video mem */
.name = "s1d13xxxfb memory",
.start = YL9200_FB_VMEM_BASE,
.end = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1,
.flags = IORESOURCE_MEM,
},
[1] = { /* video registers */
.name = "s1d13xxxfb registers",
.start = YL9200_FB_REG_BASE,
.end = YL9200_FB_REG_BASE + SZ_512 -1,
.flags = IORESOURCE_MEM,
},
};
static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
static struct platform_device yl9200_s1dfb_device = {
.name = "s1d13806fb",
.id = -1,
.dev = {
.dma_mask = &s1dfb_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &yl9200_s1dfb_pdata,
},
.resource = yl9200_s1dfb_resource,
.num_resources = ARRAY_SIZE(yl9200_s1dfb_resource),
};
void __init yl9200_add_device_video(void)
{
platform_device_register(&yl9200_s1dfb_device);
}
#else
void __init yl9200_add_device_video(void) {}
#endif
static void __init yl9200_board_init(void)
{
/* Serial */
/* DBGU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
| ATMEL_UART_RI);
/* USART0 on ttyS2. (Rx & Tx only to JP3) */
at91_register_uart(AT91RM9200_ID_US0, 2, 0);
/* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
at91_add_device_serial();
/* Ethernet */
at91_add_device_eth(&yl9200_eth_data);
/* USB Host */
at91_add_device_usbh(&yl9200_usbh_data);
/* USB Device */
at91_add_device_udc(&yl9200_udc_data);
/* I2C */
at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
/* MMC */
at91_add_device_mci(0, &yl9200_mci0_data);
/* NAND */
at91_add_device_nand(&yl9200_nand_data);
/* NOR Flash */
platform_device_register(&yl9200_flash);
#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
/* SPI */
at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
/* Touchscreen */
yl9200_add_device_ts();
#endif
/* LEDs. */
at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
/* Push Buttons */
yl9200_add_device_buttons();
/* VGA */
yl9200_add_device_video();
}
MACHINE_START(YL9200, "uCdragon YL-9200")
/* Maintainer: S.Birtles */
.init_time = at91rm9200_timer_init,
.map_io = at91_map_io,
.handle_irq = at91_aic_handle_irq,
.init_early = yl9200_init_early,
.init_irq = at91_init_irq_default,
.init_machine = yl9200_board_init,
MACHINE_END

977
arch/arm/mach-at91/clock.c
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@ -1,977 +0,0 @@
/*
* linux/arch/arm/mach-at91/clock.c
*
* Copyright (C) 2005 David Brownell
* Copyright (C) 2005 Ivan Kokshaysky
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/fs.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of_address.h>
#include <linux/clk/at91_pmc.h>
#include <mach/hardware.h>
#include <mach/cpu.h>
#include <asm/proc-fns.h>
#include "clock.h"
#include "generic.h"
void __iomem *at91_pmc_base;
EXPORT_SYMBOL_GPL(at91_pmc_base);
/*
* There's a lot more which can be done with clocks, including cpufreq
* integration, slow clock mode support (for system suspend), letting
* PLLB be used at other rates (on boards that don't need USB), etc.
*/
#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
/*
* Chips have some kind of clocks : group them by functionality
*/
#define cpu_has_utmi() ( cpu_is_at91sam9rl() \
|| cpu_is_at91sam9g45() \
|| cpu_is_at91sam9x5() \
|| cpu_is_sama5d3())
#define cpu_has_1056M_plla() (cpu_is_sama5d3())
#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
|| cpu_is_at91sam9g45() \
|| cpu_is_at91sam9x5() \
|| cpu_is_at91sam9n12())
#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
#define cpu_has_240M_plla() (cpu_is_at91sam9261() \
|| cpu_is_at91sam9263() \
|| cpu_is_at91sam9rl())
#define cpu_has_210M_plla() (cpu_is_at91sam9260())
#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
|| cpu_is_at91sam9g45() \
|| cpu_is_at91sam9x5() \
|| cpu_is_sama5d3()))
#define cpu_has_upll() (cpu_is_at91sam9g45() \
|| cpu_is_at91sam9x5() \
|| cpu_is_sama5d3())
/* USB host HS & FS */
#define cpu_has_uhp() (!cpu_is_at91sam9rl())
/* USB device FS only */
#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
|| cpu_is_at91sam9g45() \
|| cpu_is_at91sam9x5() \
|| cpu_is_sama5d3()))
#define cpu_has_plladiv2() (cpu_is_at91sam9g45() \
|| cpu_is_at91sam9x5() \
|| cpu_is_at91sam9n12() \
|| cpu_is_sama5d3())
#define cpu_has_mdiv3() (cpu_is_at91sam9g45() \
|| cpu_is_at91sam9x5() \
|| cpu_is_at91sam9n12() \
|| cpu_is_sama5d3())
#define cpu_has_alt_prescaler() (cpu_is_at91sam9x5() \
|| cpu_is_at91sam9n12() \
|| cpu_is_sama5d3())
static LIST_HEAD(clocks);
static DEFINE_SPINLOCK(clk_lock);
static u32 at91_pllb_usb_init;
/*
* Four primary clock sources: two crystal oscillators (32K, main), and
* two PLLs. PLLA usually runs the master clock; and PLLB must run at
* 48 MHz (unless no USB function clocks are needed). The main clock and
* both PLLs are turned off to run in "slow clock mode" (system suspend).
*/
static struct clk clk32k = {
.name = "clk32k",
.rate_hz = AT91_SLOW_CLOCK,
.users = 1, /* always on */
.id = 0,
.type = CLK_TYPE_PRIMARY,
};
static struct clk main_clk = {
.name = "main",
.pmc_mask = AT91_PMC_MOSCS, /* in PMC_SR */
.id = 1,
.type = CLK_TYPE_PRIMARY,
};
static struct clk plla = {
.name = "plla",
.parent = &main_clk,
.pmc_mask = AT91_PMC_LOCKA, /* in PMC_SR */
.id = 2,
.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
};
static void pllb_mode(struct clk *clk, int is_on)
{
u32 value;
if (is_on) {
is_on = AT91_PMC_LOCKB;
value = at91_pllb_usb_init;
} else
value = 0;
// REVISIT: Add work-around for AT91RM9200 Errata #26 ?
at91_pmc_write(AT91_CKGR_PLLBR, value);
do {
cpu_relax();
} while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
}
static struct clk pllb = {
.name = "pllb",
.parent = &main_clk,
.pmc_mask = AT91_PMC_LOCKB, /* in PMC_SR */
.mode = pllb_mode,
.id = 3,
.type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
};
static void pmc_sys_mode(struct clk *clk, int is_on)
{
if (is_on)
at91_pmc_write(AT91_PMC_SCER, clk->pmc_mask);
else
at91_pmc_write(AT91_PMC_SCDR, clk->pmc_mask);
}
static void pmc_uckr_mode(struct clk *clk, int is_on)
{
unsigned int uckr = at91_pmc_read(AT91_CKGR_UCKR);
if (is_on) {
is_on = AT91_PMC_LOCKU;
at91_pmc_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
} else
at91_pmc_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
do {
cpu_relax();
} while ((at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
}
/* USB function clocks (PLLB must be 48 MHz) */
static struct clk udpck = {
.name = "udpck",
.parent = &pllb,
.mode = pmc_sys_mode,
};
struct clk utmi_clk = {
.name = "utmi_clk",
.parent = &main_clk,
.pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
.mode = pmc_uckr_mode,
.type = CLK_TYPE_PLL,
};
static struct clk uhpck = {
.name = "uhpck",
/*.parent = ... we choose parent at runtime */
.mode = pmc_sys_mode,
};
/*
* The master clock is divided from the CPU clock (by 1-4). It's used for
* memory, interfaces to on-chip peripherals, the AIC, and sometimes more
* (e.g baud rate generation). It's sourced from one of the primary clocks.
*/
struct clk mck = {
.name = "mck",
.pmc_mask = AT91_PMC_MCKRDY, /* in PMC_SR */
};
static void pmc_periph_mode(struct clk *clk, int is_on)
{
u32 regval = 0;
/*
* With sama5d3 devices, we are managing clock division so we have to
* use the Peripheral Control Register introduced from at91sam9x5
* devices.
*/
if (cpu_is_sama5d3()) {
regval |= AT91_PMC_PCR_CMD; /* write command */
regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */
regval |= AT91_PMC_PCR_DIV(clk->div);
if (is_on)
regval |= AT91_PMC_PCR_EN; /* enable clock */
at91_pmc_write(AT91_PMC_PCR, regval);
} else {
if (is_on)
at91_pmc_write(AT91_PMC_PCER, clk->pmc_mask);
else
at91_pmc_write(AT91_PMC_PCDR, clk->pmc_mask);
}
}
static struct clk __init *at91_css_to_clk(unsigned long css)
{
switch (css) {
case AT91_PMC_CSS_SLOW:
return &clk32k;
case AT91_PMC_CSS_MAIN:
return &main_clk;
case AT91_PMC_CSS_PLLA:
return &plla;
case AT91_PMC_CSS_PLLB:
if (cpu_has_upll())
/* CSS_PLLB == CSS_UPLL */
return &utmi_clk;
else if (cpu_has_pllb())
return &pllb;
break;
/* alternate PMC: can use master clock */
case AT91_PMC_CSS_MASTER:
return &mck;
}
return NULL;
}
static int pmc_prescaler_divider(u32 reg)
{
if (cpu_has_alt_prescaler()) {
return 1 << ((reg & AT91_PMC_ALT_PRES) >> PMC_ALT_PRES_OFFSET);
} else {
return 1 << ((reg & AT91_PMC_PRES) >> PMC_PRES_OFFSET);
}
}
static void __clk_enable(struct clk *clk)
{
if (clk->parent)
__clk_enable(clk->parent);
if (clk->users++ == 0 && clk->mode)
clk->mode(clk, 1);
}
int clk_enable(struct clk *clk)
{
unsigned long flags;
spin_lock_irqsave(&clk_lock, flags);
__clk_enable(clk);
spin_unlock_irqrestore(&clk_lock, flags);
return 0;
}
EXPORT_SYMBOL(clk_enable);
static void __clk_disable(struct clk *clk)
{
BUG_ON(clk->users == 0);
if (--clk->users == 0 && clk->mode)
clk->mode(clk, 0);
if (clk->parent)
__clk_disable(clk->parent);
}
void clk_disable(struct clk *clk)
{
unsigned long flags;
spin_lock_irqsave(&clk_lock, flags);
__clk_disable(clk);
spin_unlock_irqrestore(&clk_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
unsigned long flags;
unsigned long rate;
spin_lock_irqsave(&clk_lock, flags);
for (;;) {
rate = clk->rate_hz;
if (rate || !clk->parent)
break;
clk = clk->parent;
}
spin_unlock_irqrestore(&clk_lock, flags);
return rate;
}
EXPORT_SYMBOL(clk_get_rate);
/*------------------------------------------------------------------------*/
/*
* For now, only the programmable clocks support reparenting (MCK could
* do this too, with care) or rate changing (the PLLs could do this too,
* ditto MCK but that's more for cpufreq). Drivers may reparent to get
* a better rate match; we don't.
*/
long clk_round_rate(struct clk *clk, unsigned long rate)
{
unsigned long flags;
unsigned prescale;
unsigned long actual;
unsigned long prev = ULONG_MAX;
if (!clk_is_programmable(clk))
return -EINVAL;
spin_lock_irqsave(&clk_lock, flags);
actual = clk->parent->rate_hz;
for (prescale = 0; prescale < 7; prescale++) {
if (actual > rate)
prev = actual;
if (actual && actual <= rate) {
if ((prev - rate) < (rate - actual)) {
actual = prev;
prescale--;
}
break;
}
actual >>= 1;
}
spin_unlock_irqrestore(&clk_lock, flags);
return (prescale < 7) ? actual : -ENOENT;
}
EXPORT_SYMBOL(clk_round_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long flags;
unsigned prescale;
unsigned long prescale_offset, css_mask;
unsigned long actual;
if (!clk_is_programmable(clk))
return -EINVAL;
if (clk->users)
return -EBUSY;
if (cpu_has_alt_prescaler()) {
prescale_offset = PMC_ALT_PRES_OFFSET;
css_mask = AT91_PMC_ALT_PCKR_CSS;
} else {
prescale_offset = PMC_PRES_OFFSET;
css_mask = AT91_PMC_CSS;
}
spin_lock_irqsave(&clk_lock, flags);
actual = clk->parent->rate_hz;
for (prescale = 0; prescale < 7; prescale++) {
if (actual && actual <= rate) {
u32 pckr;
pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
pckr &= css_mask; /* keep clock selection */
pckr |= prescale << prescale_offset;
at91_pmc_write(AT91_PMC_PCKR(clk->id), pckr);
clk->rate_hz = actual;
break;
}
actual >>= 1;
}
spin_unlock_irqrestore(&clk_lock, flags);
return (prescale < 7) ? actual : -ENOENT;
}
EXPORT_SYMBOL(clk_set_rate);
struct clk *clk_get_parent(struct clk *clk)
{
return clk->parent;
}
EXPORT_SYMBOL(clk_get_parent);
int clk_set_parent(struct clk *clk, struct clk *parent)
{
unsigned long flags;
if (clk->users)
return -EBUSY;
if (!clk_is_primary(parent) || !clk_is_programmable(clk))
return -EINVAL;
if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
return -EINVAL;
spin_lock_irqsave(&clk_lock, flags);
clk->rate_hz = parent->rate_hz;
clk->parent = parent;
at91_pmc_write(AT91_PMC_PCKR(clk->id), parent->id);
spin_unlock_irqrestore(&clk_lock, flags);
return 0;
}
EXPORT_SYMBOL(clk_set_parent);
/* establish PCK0..PCKN parentage and rate */
static void __init init_programmable_clock(struct clk *clk)
{
struct clk *parent;
u32 pckr;
unsigned int css_mask;
if (cpu_has_alt_prescaler())
css_mask = AT91_PMC_ALT_PCKR_CSS;
else
css_mask = AT91_PMC_CSS;
pckr = at91_pmc_read(AT91_PMC_PCKR(clk->id));
parent = at91_css_to_clk(pckr & css_mask);
clk->parent = parent;
clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr);
}
/*------------------------------------------------------------------------*/
#ifdef CONFIG_DEBUG_FS
static int at91_clk_show(struct seq_file *s, void *unused)
{
u32 scsr, pcsr, pcsr1 = 0, uckr = 0, sr;
struct clk *clk;
scsr = at91_pmc_read(AT91_PMC_SCSR);
pcsr = at91_pmc_read(AT91_PMC_PCSR);
if (cpu_is_sama5d3())
pcsr1 = at91_pmc_read(AT91_PMC_PCSR1);
sr = at91_pmc_read(AT91_PMC_SR);
seq_printf(s, "SCSR = %8x\n", scsr);
seq_printf(s, "PCSR = %8x\n", pcsr);
if (cpu_is_sama5d3())
seq_printf(s, "PCSR1 = %8x\n", pcsr1);
seq_printf(s, "MOR = %8x\n", at91_pmc_read(AT91_CKGR_MOR));
seq_printf(s, "MCFR = %8x\n", at91_pmc_read(AT91_CKGR_MCFR));
seq_printf(s, "PLLA = %8x\n", at91_pmc_read(AT91_CKGR_PLLAR));
if (cpu_has_pllb())
seq_printf(s, "PLLB = %8x\n", at91_pmc_read(AT91_CKGR_PLLBR));
if (cpu_has_utmi()) {
uckr = at91_pmc_read(AT91_CKGR_UCKR);
seq_printf(s, "UCKR = %8x\n", uckr);
}
seq_printf(s, "MCKR = %8x\n", at91_pmc_read(AT91_PMC_MCKR));
if (cpu_has_upll() || cpu_is_at91sam9n12())
seq_printf(s, "USB = %8x\n", at91_pmc_read(AT91_PMC_USB));
seq_printf(s, "SR = %8x\n", sr);
seq_printf(s, "\n");
list_for_each_entry(clk, &clocks, node) {
char *state;
if (clk->mode == pmc_sys_mode) {
state = (scsr & clk->pmc_mask) ? "on" : "off";
} else if (clk->mode == pmc_periph_mode) {
if (cpu_is_sama5d3()) {
u32 pmc_mask = 1 << (clk->pid % 32);
if (clk->pid > 31)
state = (pcsr1 & pmc_mask) ? "on" : "off";
else
state = (pcsr & pmc_mask) ? "on" : "off";
} else {
state = (pcsr & clk->pmc_mask) ? "on" : "off";
}
} else if (clk->mode == pmc_uckr_mode) {
state = (uckr & clk->pmc_mask) ? "on" : "off";
} else if (clk->pmc_mask) {
state = (sr & clk->pmc_mask) ? "on" : "off";
} else if (clk == &clk32k || clk == &main_clk) {
state = "on";
} else {
state = "";
}
seq_printf(s, "%-10s users=%2d %-3s %9lu Hz %s\n",
clk->name, clk->users, state, clk_get_rate(clk),
clk->parent ? clk->parent->name : "");
}
return 0;
}
static int at91_clk_open(struct inode *inode, struct file *file)
{
return single_open(file, at91_clk_show, NULL);
}
static const struct file_operations at91_clk_operations = {
.open = at91_clk_open,
.read = seq_read,
.llseek = seq_lseek,
.release = single_release,
};
static int __init at91_clk_debugfs_init(void)
{
/* /sys/kernel/debug/at91_clk */
(void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
return 0;
}
postcore_initcall(at91_clk_debugfs_init);
#endif
/*------------------------------------------------------------------------*/
/* Register a new clock */
static void __init at91_clk_add(struct clk *clk)
{
list_add_tail(&clk->node, &clocks);
clk->cl.con_id = clk->name;
clk->cl.clk = clk;
clkdev_add(&clk->cl);
}
int __init clk_register(struct clk *clk)
{
if (clk_is_peripheral(clk)) {
if (!clk->parent)
clk->parent = &mck;
if (cpu_is_sama5d3())
clk->rate_hz = DIV_ROUND_UP(clk->parent->rate_hz,
1 << clk->div);
clk->mode = pmc_periph_mode;
}
else if (clk_is_sys(clk)) {
clk->parent = &mck;
clk->mode = pmc_sys_mode;
}
else if (clk_is_programmable(clk)) {
clk->mode = pmc_sys_mode;
init_programmable_clock(clk);
}
at91_clk_add(clk);
return 0;
}
/*------------------------------------------------------------------------*/
static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
{
unsigned mul, div;
div = reg & 0xff;
if (cpu_is_sama5d3())
mul = AT91_PMC3_MUL_GET(reg);
else
mul = AT91_PMC_MUL_GET(reg);
if (div && mul) {
freq /= div;
freq *= mul + 1;
} else
freq = 0;
return freq;
}
static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
{
if (pll == &pllb && (reg & AT91_PMC_USB96M))
return freq / 2;
else if (pll == &utmi_clk || cpu_is_at91sam9n12())
return freq / (1 + ((reg & AT91_PMC_OHCIUSBDIV) >> 8));
else
return freq;
}
static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
{
unsigned i, div = 0, mul = 0, diff = 1 << 30;
unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
/* PLL output max 240 MHz (or 180 MHz per errata) */
if (out_freq > 240000000)
goto fail;
for (i = 1; i < 256; i++) {
int diff1;
unsigned input, mul1;
/*
* PLL input between 1MHz and 32MHz per spec, but lower
* frequences seem necessary in some cases so allow 100K.
* Warning: some newer products need 2MHz min.
*/
input = main_freq / i;
if (cpu_is_at91sam9g20() && input < 2000000)
continue;
if (input < 100000)
continue;
if (input > 32000000)
continue;
mul1 = out_freq / input;
if (cpu_is_at91sam9g20() && mul > 63)
continue;
if (mul1 > 2048)
continue;
if (mul1 < 2)
goto fail;
diff1 = out_freq - input * mul1;
if (diff1 < 0)
diff1 = -diff1;
if (diff > diff1) {
diff = diff1;
div = i;
mul = mul1;
if (diff == 0)
break;
}
}
if (i == 256 && diff > (out_freq >> 5))
goto fail;
return ret | ((mul - 1) << 16) | div;
fail:
return 0;
}
static struct clk *const standard_pmc_clocks[] __initconst = {
/* four primary clocks */
&clk32k,
&main_clk,
&plla,
/* MCK */
&mck
};
/* PLLB generated USB full speed clock init */
static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
{
unsigned int reg;
/*
* USB clock init: choose 48 MHz PLLB value,
* disable 48MHz clock during usb peripheral suspend.
*
* REVISIT: assumes MCK doesn't derive from PLLB!
*/
uhpck.parent = &pllb;
reg = at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2);
pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
if (cpu_is_at91rm9200()) {
reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
uhpck.pmc_mask = AT91RM9200_PMC_UHP;
udpck.pmc_mask = AT91RM9200_PMC_UDP;
at91_pmc_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
} else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
cpu_is_at91sam9g10()) {
reg = at91_pllb_usb_init |= AT91_PMC_USB96M;
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
} else if (cpu_is_at91sam9n12()) {
/* Divider for USB clock is in USB clock register for 9n12 */
reg = AT91_PMC_USBS_PLLB;
/* For PLLB output 96M, set usb divider 2 (USBDIV + 1) */
reg |= AT91_PMC_OHCIUSBDIV_2;
at91_pmc_write(AT91_PMC_USB, reg);
/* Still setup masks */
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
udpck.pmc_mask = AT91SAM926x_PMC_UDP;
}
at91_pmc_write(AT91_CKGR_PLLBR, 0);
udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, reg);
}
/* UPLL generated USB full speed clock init */
static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
{
/*
* USB clock init: choose 480 MHz from UPLL,
*/
unsigned int usbr = AT91_PMC_USBS_UPLL;
/* Setup divider by 10 to reach 48 MHz */
usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
at91_pmc_write(AT91_PMC_USB, usbr);
/* Now set uhpck values */
uhpck.parent = &utmi_clk;
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
uhpck.rate_hz = at91_usb_rate(&utmi_clk, utmi_clk.rate_hz, usbr);
}
static int __init at91_pmc_init(unsigned long main_clock)
{
unsigned tmp, freq, mckr;
int i;
int pll_overclock = false;
/*
* When the bootloader initialized the main oscillator correctly,
* there's no problem using the cycle counter. But if it didn't,
* or when using oscillator bypass mode, we must be told the speed
* of the main clock.
*/
if (!main_clock) {
do {
tmp = at91_pmc_read(AT91_CKGR_MCFR);
} while (!(tmp & AT91_PMC_MAINRDY));
main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
}
main_clk.rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */
plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_pmc_read(AT91_CKGR_PLLAR));
if (cpu_has_1056M_plla()) {
if (plla.rate_hz > 1056000000)
pll_overclock = true;
} else if (cpu_has_800M_plla()) {
if (plla.rate_hz > 800000000)
pll_overclock = true;
} else if (cpu_has_300M_plla()) {
if (plla.rate_hz > 300000000)
pll_overclock = true;
} else if (cpu_has_240M_plla()) {
if (plla.rate_hz > 240000000)
pll_overclock = true;
} else if (cpu_has_210M_plla()) {
if (plla.rate_hz > 210000000)
pll_overclock = true;
} else {
if (plla.rate_hz > 209000000)
pll_overclock = true;
}
if (pll_overclock)
pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
if (cpu_has_plladiv2()) {
mckr = at91_pmc_read(AT91_PMC_MCKR);
plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12)); /* plla divisor by 2 */
}
if (!cpu_has_pllb() && cpu_has_upll()) {
/* setup UTMI clock as the fourth primary clock
* (instead of pllb) */
utmi_clk.type |= CLK_TYPE_PRIMARY;
utmi_clk.id = 3;
}
/*
* USB HS clock init
*/
if (cpu_has_utmi()) {
/*
* multiplier is hard-wired to 40
* (obtain the USB High Speed 480 MHz when input is 12 MHz)
*/
utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
/* UTMI bias and PLL are managed at the same time */
if (cpu_has_upll())
utmi_clk.pmc_mask |= AT91_PMC_BIASEN;
}
/*
* USB FS clock init
*/
if (cpu_has_pllb())
at91_pllb_usbfs_clock_init(main_clock);
if (cpu_has_upll())
/* assumes that we choose UPLL for USB and not PLLA */
at91_upll_usbfs_clock_init(main_clock);
/*
* MCK and CPU derive from one of those primary clocks.
* For now, assume this parentage won't change.
*/
mckr = at91_pmc_read(AT91_PMC_MCKR);
mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
freq = mck.parent->rate_hz;
freq /= pmc_prescaler_divider(mckr); /* prescale */
if (cpu_is_at91rm9200()) {
mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
} else if (cpu_is_at91sam9g20()) {
mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
if (mckr & AT91_PMC_PDIV)
freq /= 2; /* processor clock division */
} else if (cpu_has_mdiv3()) {
mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
} else {
mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
}
if (cpu_has_alt_prescaler()) {
/* Programmable clocks can use MCK */
mck.type |= CLK_TYPE_PRIMARY;
mck.id = 4;
}
/* Register the PMC's standard clocks */
for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
at91_clk_add(standard_pmc_clocks[i]);
if (cpu_has_pllb())
at91_clk_add(&pllb);
if (cpu_has_uhp())
at91_clk_add(&uhpck);
if (cpu_has_udpfs())
at91_clk_add(&udpck);
if (cpu_has_utmi())
at91_clk_add(&utmi_clk);
/* MCK and CPU clock are "always on" */
clk_enable(&mck);
printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
freq / 1000000, (unsigned) mck.rate_hz / 1000000,
(unsigned) main_clock / 1000000,
((unsigned) main_clock % 1000000) / 1000);
return 0;
}
#if defined(CONFIG_OF)
static struct of_device_id pmc_ids[] = {
{ .compatible = "atmel,at91rm9200-pmc" },
{ .compatible = "atmel,at91sam9260-pmc" },
{ .compatible = "atmel,at91sam9g45-pmc" },
{ .compatible = "atmel,at91sam9n12-pmc" },
{ .compatible = "atmel,at91sam9x5-pmc" },
{ .compatible = "atmel,sama5d3-pmc" },
{ /*sentinel*/ }
};
static struct of_device_id osc_ids[] = {
{ .compatible = "atmel,osc" },
{ /*sentinel*/ }
};
int __init at91_dt_clock_init(void)
{
struct device_node *np;
u32 main_clock = 0;
np = of_find_matching_node(NULL, pmc_ids);
if (!np)
panic("unable to find compatible pmc node in dtb\n");
at91_pmc_base = of_iomap(np, 0);
if (!at91_pmc_base)
panic("unable to map pmc cpu registers\n");
of_node_put(np);
/* retrieve the freqency of fixed clocks from device tree */
np = of_find_matching_node(NULL, osc_ids);
if (np) {
u32 rate;
if (!of_property_read_u32(np, "clock-frequency", &rate))
main_clock = rate;
}
of_node_put(np);
return at91_pmc_init(main_clock);
}
#endif
int __init at91_clock_init(unsigned long main_clock)
{
at91_pmc_base = ioremap(AT91_PMC, 256);
if (!at91_pmc_base)
panic("Impossible to ioremap AT91_PMC 0x%x\n", AT91_PMC);
return at91_pmc_init(main_clock);
}
/*
* Several unused clocks may be active. Turn them off.
*/
static int __init at91_clock_reset(void)
{
unsigned long pcdr = 0;
unsigned long pcdr1 = 0;
unsigned long scdr = 0;
struct clk *clk;
list_for_each_entry(clk, &clocks, node) {
if (clk->users > 0)
continue;
if (clk->mode == pmc_periph_mode) {
if (cpu_is_sama5d3()) {
u32 pmc_mask = 1 << (clk->pid % 32);
if (clk->pid > 31)
pcdr1 |= pmc_mask;
else
pcdr |= pmc_mask;
} else
pcdr |= clk->pmc_mask;
}
if (clk->mode == pmc_sys_mode)
scdr |= clk->pmc_mask;
pr_debug("Clocks: disable unused %s\n", clk->name);
}
at91_pmc_write(AT91_PMC_SCDR, scdr);
at91_pmc_write(AT91_PMC_PCDR, pcdr);
if (cpu_is_sama5d3())
at91_pmc_write(AT91_PMC_PCDR1, pcdr1);
return 0;
}
late_initcall(at91_clock_reset);
void at91sam9_idle(void)
{
at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
cpu_do_idle();
}

49
arch/arm/mach-at91/clock.h
Просмотреть файл

@ -1,49 +0,0 @@
/*
* linux/arch/arm/mach-at91/clock.h
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/clkdev.h>
#define CLK_TYPE_PRIMARY 0x1
#define CLK_TYPE_PLL 0x2
#define CLK_TYPE_PROGRAMMABLE 0x4
#define CLK_TYPE_PERIPHERAL 0x8
#define CLK_TYPE_SYSTEM 0x10
struct clk {
struct list_head node;
const char *name; /* unique clock name */
struct clk_lookup cl;
unsigned long rate_hz;
unsigned div; /* parent clock divider */
struct clk *parent;
unsigned pid; /* peripheral ID */
u32 pmc_mask;
void (*mode)(struct clk *, int);
unsigned id:3; /* PCK0..4, or 32k/main/a/b */
unsigned type; /* clock type */
u16 users;
};
extern int __init clk_register(struct clk *clk);
extern struct clk mck;
extern struct clk utmi_clk;
#define CLKDEV_CON_ID(_id, _clk) \
{ \
.con_id = _id, \
.clk = _clk, \
}
#define CLKDEV_CON_DEV_ID(_con_id, _dev_id, _clk) \
{ \
.con_id = _con_id, \
.dev_id = _dev_id, \
.clk = _clk, \
}

17
arch/arm/mach-at91/generic.h
Просмотреть файл

@ -11,7 +11,6 @@
#ifndef _AT91_GENERIC_H
#define _AT91_GENERIC_H
#include <linux/clkdev.h>
#include <linux/of.h>
#include <linux/reboot.h>
@ -30,12 +29,6 @@ extern void __init at91_dt_initialize(void);
/* Interrupts */
extern void __init at91_init_irq_default(void);
extern void __init at91_init_interrupts(unsigned int priority[]);
extern void __init at91_aic_init(unsigned int priority[],
unsigned int ext_irq_mask);
extern int __init at91_aic_of_init(struct device_node *node,
struct device_node *parent);
extern int __init at91_aic5_of_init(struct device_node *node,
struct device_node *parent);
extern void __init at91_sysirq_mask_rtc(u32 rtc_base);
extern void __init at91_sysirq_mask_rtt(u32 rtt_base);
@ -49,16 +42,6 @@ extern void at91rm9200_timer_init(void);
extern void at91sam926x_ioremap_pit(u32 addr);
extern void at91sam926x_pit_init(int irq);
/* Clocks */
#ifdef CONFIG_OLD_CLK_AT91
extern int __init at91_clock_init(unsigned long main_clock);
extern int __init at91_dt_clock_init(void);
#else
static int inline at91_clock_init(unsigned long main_clock) { return 0; }
static int inline at91_dt_clock_init(void) { return 0; }
#endif
struct device;
/* Power Management */
extern void at91_irq_suspend(void);
extern void at91_irq_resume(void);

296
arch/arm/mach-at91/irq.c
Просмотреть файл

@ -1,296 +0,0 @@
/*
* linux/arch/arm/mach-at91/irq.c
*
* Copyright (C) 2004 SAN People
* Copyright (C) 2004 ATMEL
* Copyright (C) Rick Bronson
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/bitmap.h>
#include <linux/types.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/irqdomain.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/exception.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include "at91_aic.h"
void __iomem *at91_aic_base;
static struct irq_domain *at91_aic_domain;
static struct device_node *at91_aic_np;
static unsigned int n_irqs = NR_AIC_IRQS;
#ifdef CONFIG_PM
static unsigned long *wakeups;
static unsigned long *backups;
#define set_backup(bit) set_bit(bit, backups)
#define clear_backup(bit) clear_bit(bit, backups)
static int at91_aic_pm_init(void)
{
backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
if (!backups)
return -ENOMEM;
wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
if (!wakeups) {
kfree(backups);
return -ENOMEM;
}
return 0;
}
static int at91_aic_set_wake(struct irq_data *d, unsigned value)
{
if (unlikely(d->hwirq >= n_irqs))
return -EINVAL;
if (value)
set_bit(d->hwirq, wakeups);
else
clear_bit(d->hwirq, wakeups);
return 0;
}
void at91_irq_suspend(void)
{
at91_aic_write(AT91_AIC_IDCR, *backups);
at91_aic_write(AT91_AIC_IECR, *wakeups);
}
void at91_irq_resume(void)
{
at91_aic_write(AT91_AIC_IDCR, *wakeups);
at91_aic_write(AT91_AIC_IECR, *backups);
}
#else
static inline int at91_aic_pm_init(void)
{
return 0;
}
#define set_backup(bit)
#define clear_backup(bit)
#define at91_aic_set_wake NULL
#endif /* CONFIG_PM */
asmlinkage void __exception_irq_entry
at91_aic_handle_irq(struct pt_regs *regs)
{
u32 irqnr;
u32 irqstat;
irqnr = at91_aic_read(AT91_AIC_IVR);
irqstat = at91_aic_read(AT91_AIC_ISR);
/*
* ISR value is 0 when there is no current interrupt or when there is
* a spurious interrupt
*/
if (!irqstat)
at91_aic_write(AT91_AIC_EOICR, 0);
else
handle_IRQ(irqnr, regs);
}
static void at91_aic_mask_irq(struct irq_data *d)
{
/* Disable interrupt on AIC */
at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
/* Update ISR cache */
clear_backup(d->hwirq);
}
static void at91_aic_unmask_irq(struct irq_data *d)
{
/* Enable interrupt on AIC */
at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
/* Update ISR cache */
set_backup(d->hwirq);
}
static void at91_aic_eoi(struct irq_data *d)
{
/*
* Mark end-of-interrupt on AIC, the controller doesn't care about
* the value written. Moreover it's a write-only register.
*/
at91_aic_write(AT91_AIC_EOICR, 0);
}
static unsigned long *at91_extern_irq;
u32 at91_get_extern_irq(void)
{
if (!at91_extern_irq)
return 0;
return *at91_extern_irq;
}
#define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
static int at91_aic_compute_srctype(struct irq_data *d, unsigned type)
{
int srctype;
switch (type) {
case IRQ_TYPE_LEVEL_HIGH:
srctype = AT91_AIC_SRCTYPE_HIGH;
break;
case IRQ_TYPE_EDGE_RISING:
srctype = AT91_AIC_SRCTYPE_RISING;
break;
case IRQ_TYPE_LEVEL_LOW:
if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
srctype = AT91_AIC_SRCTYPE_LOW;
else
srctype = -EINVAL;
break;
case IRQ_TYPE_EDGE_FALLING:
if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq)) /* only supported on external interrupts */
srctype = AT91_AIC_SRCTYPE_FALLING;
else
srctype = -EINVAL;
break;
default:
srctype = -EINVAL;
}
return srctype;
}
static int at91_aic_set_type(struct irq_data *d, unsigned type)
{
unsigned int smr;
int srctype;
srctype = at91_aic_compute_srctype(d, type);
if (srctype < 0)
return srctype;
smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
return 0;
}
static struct irq_chip at91_aic_chip = {
.name = "AIC",
.irq_mask = at91_aic_mask_irq,
.irq_unmask = at91_aic_unmask_irq,
.irq_set_type = at91_aic_set_type,
.irq_set_wake = at91_aic_set_wake,
.irq_eoi = at91_aic_eoi,
};
static void __init at91_aic_hw_init(unsigned int spu_vector)
{
int i;
/*
* Perform 8 End Of Interrupt Command to make sure AIC
* will not Lock out nIRQ
*/
for (i = 0; i < 8; i++)
at91_aic_write(AT91_AIC_EOICR, 0);
/*
* Spurious Interrupt ID in Spurious Vector Register.
* When there is no current interrupt, the IRQ Vector Register
* reads the value stored in AIC_SPU
*/
at91_aic_write(AT91_AIC_SPU, spu_vector);
/* No debugging in AIC: Debug (Protect) Control Register */
at91_aic_write(AT91_AIC_DCR, 0);
/* Disable and clear all interrupts initially */
at91_aic_write(AT91_AIC_IDCR, 0xFFFFFFFF);
at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
}
/*
* Initialize the AIC interrupt controller.
*/
void __init at91_aic_init(unsigned int *priority, unsigned int ext_irq_mask)
{
unsigned int i;
int irq_base;
at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
* sizeof(*at91_extern_irq), GFP_KERNEL);
if (at91_aic_pm_init() || at91_extern_irq == NULL)
panic("Unable to allocate bit maps\n");
*at91_extern_irq = ext_irq_mask;
at91_aic_base = ioremap(AT91_AIC, 512);
if (!at91_aic_base)
panic("Unable to ioremap AIC registers\n");
/* Add irq domain for AIC */
irq_base = irq_alloc_descs(-1, 0, n_irqs, 0);
if (irq_base < 0) {
WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
irq_base = 0;
}
at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs,
irq_base, 0,
&irq_domain_simple_ops, NULL);
if (!at91_aic_domain)
panic("Unable to add AIC irq domain\n");
irq_set_default_host(at91_aic_domain);
/*
* The IVR is used by macro get_irqnr_and_base to read and verify.
* The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
*/
for (i = 0; i < n_irqs; i++) {
/* Put hardware irq number in Source Vector Register: */
at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i);
/* Active Low interrupt, with the specified priority */
at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
at91_aic_hw_init(n_irqs);
}

22
arch/arm/mach-at91/pm.c
Просмотреть файл

@ -29,7 +29,6 @@
#include <mach/cpu.h>
#include <mach/hardware.h>
#include "at91_aic.h"
#include "generic.h"
#include "pm.h"
#include "gpio.h"
@ -136,19 +135,6 @@ static int at91_pm_enter(suspend_state_t state)
else
at91_gpio_suspend();
if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base) {
at91_irq_suspend();
pr_debug("AT91: PM - wake mask %08x, pm state %d\n",
/* remember all the always-wake irqs */
(at91_pmc_read(AT91_PMC_PCSR)
| (1 << AT91_ID_FIQ)
| (1 << AT91_ID_SYS)
| (at91_get_extern_irq()))
& at91_aic_read(AT91_AIC_IMR),
state);
}
switch (state) {
/*
* Suspend-to-RAM is like STANDBY plus slow clock mode, so
@ -212,17 +198,9 @@ static int at91_pm_enter(suspend_state_t state)
goto error;
}
if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
pr_debug("AT91: PM - wakeup %08x\n",
at91_aic_read(AT91_AIC_IPR) &
at91_aic_read(AT91_AIC_IMR));
error:
target_state = PM_SUSPEND_ON;
if (IS_ENABLED(CONFIG_OLD_IRQ_AT91) && at91_aic_base)
at91_irq_resume();
if (of_have_populated_dt())
at91_pinctrl_gpio_resume();
else

13
arch/arm/mach-at91/setup.c
Просмотреть файл

@ -49,10 +49,6 @@ void __init at91_init_irq_default(void)
void __init at91_init_interrupts(unsigned int *priority)
{
/* Initialize the AIC interrupt controller */
if (IS_ENABLED(CONFIG_OLD_IRQ_AT91))
at91_aic_init(priority, at91_boot_soc.extern_irq);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}
@ -460,9 +456,6 @@ void __init at91rm9200_dt_initialize(void)
{
at91_dt_ramc();
/* Init clock subsystem */
at91_dt_clock_init();
/* Register the processor-specific clocks */
if (at91_boot_soc.register_clocks)
at91_boot_soc.register_clocks();
@ -474,9 +467,6 @@ void __init at91_dt_initialize(void)
{
at91_dt_ramc();
/* Init clock subsystem */
at91_dt_clock_init();
/* Register the processor-specific clocks */
if (at91_boot_soc.register_clocks)
at91_boot_soc.register_clocks();
@ -490,9 +480,6 @@ void __init at91_initialize(unsigned long main_clock)
{
at91_boot_soc.ioremap_registers();
/* Init clock subsystem */
at91_clock_init(main_clock);
/* Register the processor-specific clocks */
at91_boot_soc.register_clocks();

2
drivers/net/ethernet/cadence/Kconfig
Просмотреть файл

@ -22,7 +22,7 @@ if NET_CADENCE
config ARM_AT91_ETHER
tristate "AT91RM9200 Ethernet support"
depends on HAS_DMA && (ARCH_AT91RM9200 || COMPILE_TEST)
depends on HAS_DMA && (ARCH_AT91 || COMPILE_TEST)
select MACB
---help---
If you wish to compile a kernel for the AT91RM9200 and enable

2
drivers/rtc/Kconfig
Просмотреть файл

@ -1110,7 +1110,7 @@ config RTC_DRV_AT91RM9200
config RTC_DRV_AT91SAM9
tristate "AT91SAM9x/AT91CAP9 RTT as RTC"
depends on ARCH_AT91 && !ARCH_AT91RM9200
depends on ARCH_AT91
help
RTC driver for the Atmel AT91SAM9x and AT91CAP9 internal RTT
(Real Time Timer). These timers are powered by the backup power

4
drivers/watchdog/Kconfig
Просмотреть файл

@ -154,14 +154,14 @@ config ARM_SP805_WATCHDOG
config AT91RM9200_WATCHDOG
tristate "AT91RM9200 watchdog"
depends on ARCH_AT91RM9200
depends on SOC_AT91RM9200
help
Watchdog timer embedded into AT91RM9200 chips. This will reboot your
system when the timeout is reached.
config AT91SAM9X_WATCHDOG
tristate "AT91SAM9X / AT91CAP9 watchdog"
depends on ARCH_AT91 && !ARCH_AT91RM9200
depends on ARCH_AT91
select WATCHDOG_CORE
help
Watchdog timer embedded into AT91SAM9X and AT91CAP9 chips. This will