KVM: ia64: remove
KVM for ia64 has been marked as broken not just once, but twice even, and the last patch from the maintainer is now roughly 5 years old. Time for it to rest in peace. Acked-by: Gleb Natapov <gleb@kernel.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Родитель
86619e7ba3
Коммит
003f7de625
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@ -5352,15 +5352,6 @@ S: Supported
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F: arch/powerpc/include/asm/kvm*
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F: arch/powerpc/kvm/
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KERNEL VIRTUAL MACHINE For Itanium (KVM/IA64)
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M: Xiantao Zhang <xiantao.zhang@intel.com>
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L: kvm-ia64@vger.kernel.org
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W: http://kvm.qumranet.com
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S: Supported
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F: Documentation/ia64/kvm.txt
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F: arch/ia64/include/asm/kvm*
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F: arch/ia64/kvm/
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KERNEL VIRTUAL MACHINE for s390 (KVM/s390)
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M: Christian Borntraeger <borntraeger@de.ibm.com>
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M: Cornelia Huck <cornelia.huck@de.ibm.com>
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@ -21,7 +21,6 @@ config IA64
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select HAVE_DYNAMIC_FTRACE if (!ITANIUM)
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select HAVE_FUNCTION_TRACER
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select HAVE_DMA_ATTRS
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select HAVE_KVM
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select TTY
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select HAVE_ARCH_TRACEHOOK
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select HAVE_DMA_API_DEBUG
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@ -640,8 +639,6 @@ source "security/Kconfig"
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source "crypto/Kconfig"
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source "arch/ia64/kvm/Kconfig"
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source "lib/Kconfig"
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config IOMMU_HELPER
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@ -53,7 +53,6 @@ core-$(CONFIG_IA64_HP_ZX1) += arch/ia64/dig/
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core-$(CONFIG_IA64_HP_ZX1_SWIOTLB) += arch/ia64/dig/
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core-$(CONFIG_IA64_SGI_SN2) += arch/ia64/sn/
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core-$(CONFIG_IA64_SGI_UV) += arch/ia64/uv/
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core-$(CONFIG_KVM) += arch/ia64/kvm/
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drivers-$(CONFIG_PCI) += arch/ia64/pci/
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drivers-$(CONFIG_IA64_HP_SIM) += arch/ia64/hp/sim/
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@ -1,609 +0,0 @@
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/*
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* kvm_host.h: used for kvm module, and hold ia64-specific sections.
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*
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* Copyright (C) 2007, Intel Corporation.
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*
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* Xiantao Zhang <xiantao.zhang@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#ifndef __ASM_KVM_HOST_H
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#define __ASM_KVM_HOST_H
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#define KVM_USER_MEM_SLOTS 32
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#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
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#define KVM_IRQCHIP_NUM_PINS KVM_IOAPIC_NUM_PINS
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/* define exit reasons from vmm to kvm*/
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#define EXIT_REASON_VM_PANIC 0
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#define EXIT_REASON_MMIO_INSTRUCTION 1
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#define EXIT_REASON_PAL_CALL 2
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#define EXIT_REASON_SAL_CALL 3
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#define EXIT_REASON_SWITCH_RR6 4
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#define EXIT_REASON_VM_DESTROY 5
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#define EXIT_REASON_EXTERNAL_INTERRUPT 6
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#define EXIT_REASON_IPI 7
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#define EXIT_REASON_PTC_G 8
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#define EXIT_REASON_DEBUG 20
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/*Define vmm address space and vm data space.*/
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#define KVM_VMM_SIZE (__IA64_UL_CONST(16)<<20)
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#define KVM_VMM_SHIFT 24
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#define KVM_VMM_BASE 0xD000000000000000
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#define VMM_SIZE (__IA64_UL_CONST(8)<<20)
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/*
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* Define vm_buffer, used by PAL Services, base address.
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* Note: vm_buffer is in the VMM-BLOCK, the size must be < 8M
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*/
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#define KVM_VM_BUFFER_BASE (KVM_VMM_BASE + VMM_SIZE)
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#define KVM_VM_BUFFER_SIZE (__IA64_UL_CONST(8)<<20)
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/*
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* kvm guest's data area looks as follow:
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*
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* +----------------------+ ------- KVM_VM_DATA_SIZE
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* | vcpu[n]'s data | | ___________________KVM_STK_OFFSET
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* | | | / |
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* | .......... | | /vcpu's struct&stack |
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* | .......... | | /---------------------|---- 0
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* | vcpu[5]'s data | | / vpd |
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* | vcpu[4]'s data | |/-----------------------|
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* | vcpu[3]'s data | / vtlb |
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* | vcpu[2]'s data | /|------------------------|
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* | vcpu[1]'s data |/ | vhpt |
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* | vcpu[0]'s data |____________________________|
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* +----------------------+ |
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* | memory dirty log | |
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* +----------------------+ |
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* | vm's data struct | |
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* +----------------------+ |
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* | | |
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* | | |
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* | | |
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* | | |
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* | | |
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* | | |
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* | | |
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* | vm's p2m table | |
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* | | |
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* | | |
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* | | | |
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* vm's data->| | | |
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* +----------------------+ ------- 0
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* To support large memory, needs to increase the size of p2m.
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* To support more vcpus, needs to ensure it has enough space to
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* hold vcpus' data.
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*/
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#define KVM_VM_DATA_SHIFT 26
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#define KVM_VM_DATA_SIZE (__IA64_UL_CONST(1) << KVM_VM_DATA_SHIFT)
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#define KVM_VM_DATA_BASE (KVM_VMM_BASE + KVM_VM_DATA_SIZE)
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#define KVM_P2M_BASE KVM_VM_DATA_BASE
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#define KVM_P2M_SIZE (__IA64_UL_CONST(24) << 20)
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#define VHPT_SHIFT 16
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#define VHPT_SIZE (__IA64_UL_CONST(1) << VHPT_SHIFT)
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#define VHPT_NUM_ENTRIES (__IA64_UL_CONST(1) << (VHPT_SHIFT-5))
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#define VTLB_SHIFT 16
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#define VTLB_SIZE (__IA64_UL_CONST(1) << VTLB_SHIFT)
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#define VTLB_NUM_ENTRIES (1UL << (VHPT_SHIFT-5))
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#define VPD_SHIFT 16
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#define VPD_SIZE (__IA64_UL_CONST(1) << VPD_SHIFT)
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#define VCPU_STRUCT_SHIFT 16
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#define VCPU_STRUCT_SIZE (__IA64_UL_CONST(1) << VCPU_STRUCT_SHIFT)
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/*
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* This must match KVM_IA64_VCPU_STACK_{SHIFT,SIZE} arch/ia64/include/asm/kvm.h
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*/
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#define KVM_STK_SHIFT 16
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#define KVM_STK_OFFSET (__IA64_UL_CONST(1)<< KVM_STK_SHIFT)
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#define KVM_VM_STRUCT_SHIFT 19
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#define KVM_VM_STRUCT_SIZE (__IA64_UL_CONST(1) << KVM_VM_STRUCT_SHIFT)
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#define KVM_MEM_DIRY_LOG_SHIFT 19
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#define KVM_MEM_DIRTY_LOG_SIZE (__IA64_UL_CONST(1) << KVM_MEM_DIRY_LOG_SHIFT)
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#ifndef __ASSEMBLY__
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/*Define the max vcpus and memory for Guests.*/
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#define KVM_MAX_VCPUS (KVM_VM_DATA_SIZE - KVM_P2M_SIZE - KVM_VM_STRUCT_SIZE -\
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KVM_MEM_DIRTY_LOG_SIZE) / sizeof(struct kvm_vcpu_data)
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#define KVM_MAX_MEM_SIZE (KVM_P2M_SIZE >> 3 << PAGE_SHIFT)
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#define VMM_LOG_LEN 256
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/kvm.h>
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#include <linux/kvm_para.h>
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#include <linux/kvm_types.h>
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#include <asm/pal.h>
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#include <asm/sal.h>
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#include <asm/page.h>
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struct kvm_vcpu_data {
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char vcpu_vhpt[VHPT_SIZE];
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char vcpu_vtlb[VTLB_SIZE];
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char vcpu_vpd[VPD_SIZE];
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char vcpu_struct[VCPU_STRUCT_SIZE];
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};
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struct kvm_vm_data {
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char kvm_p2m[KVM_P2M_SIZE];
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char kvm_vm_struct[KVM_VM_STRUCT_SIZE];
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char kvm_mem_dirty_log[KVM_MEM_DIRTY_LOG_SIZE];
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struct kvm_vcpu_data vcpu_data[KVM_MAX_VCPUS];
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};
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#define VCPU_BASE(n) (KVM_VM_DATA_BASE + \
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offsetof(struct kvm_vm_data, vcpu_data[n]))
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#define KVM_VM_BASE (KVM_VM_DATA_BASE + \
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offsetof(struct kvm_vm_data, kvm_vm_struct))
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#define KVM_MEM_DIRTY_LOG_BASE KVM_VM_DATA_BASE + \
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offsetof(struct kvm_vm_data, kvm_mem_dirty_log)
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#define VHPT_BASE(n) (VCPU_BASE(n) + offsetof(struct kvm_vcpu_data, vcpu_vhpt))
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#define VTLB_BASE(n) (VCPU_BASE(n) + offsetof(struct kvm_vcpu_data, vcpu_vtlb))
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#define VPD_BASE(n) (VCPU_BASE(n) + offsetof(struct kvm_vcpu_data, vcpu_vpd))
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#define VCPU_STRUCT_BASE(n) (VCPU_BASE(n) + \
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offsetof(struct kvm_vcpu_data, vcpu_struct))
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/*IO section definitions*/
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#define IOREQ_READ 1
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#define IOREQ_WRITE 0
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#define STATE_IOREQ_NONE 0
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#define STATE_IOREQ_READY 1
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#define STATE_IOREQ_INPROCESS 2
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#define STATE_IORESP_READY 3
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/*Guest Physical address layout.*/
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#define GPFN_MEM (0UL << 60) /* Guest pfn is normal mem */
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#define GPFN_FRAME_BUFFER (1UL << 60) /* VGA framebuffer */
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#define GPFN_LOW_MMIO (2UL << 60) /* Low MMIO range */
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#define GPFN_PIB (3UL << 60) /* PIB base */
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#define GPFN_IOSAPIC (4UL << 60) /* IOSAPIC base */
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#define GPFN_LEGACY_IO (5UL << 60) /* Legacy I/O base */
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#define GPFN_GFW (6UL << 60) /* Guest Firmware */
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#define GPFN_PHYS_MMIO (7UL << 60) /* Directed MMIO Range */
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#define GPFN_IO_MASK (7UL << 60) /* Guest pfn is I/O type */
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#define GPFN_INV_MASK (1UL << 63) /* Guest pfn is invalid */
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#define INVALID_MFN (~0UL)
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#define MEM_G (1UL << 30)
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#define MEM_M (1UL << 20)
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#define MMIO_START (3 * MEM_G)
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#define MMIO_SIZE (512 * MEM_M)
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#define VGA_IO_START 0xA0000UL
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#define VGA_IO_SIZE 0x20000
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#define LEGACY_IO_START (MMIO_START + MMIO_SIZE)
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#define LEGACY_IO_SIZE (64 * MEM_M)
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#define IO_SAPIC_START 0xfec00000UL
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#define IO_SAPIC_SIZE 0x100000
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#define PIB_START 0xfee00000UL
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#define PIB_SIZE 0x200000
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#define GFW_START (4 * MEM_G - 16 * MEM_M)
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#define GFW_SIZE (16 * MEM_M)
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/*Deliver mode, defined for ioapic.c*/
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#define dest_Fixed IOSAPIC_FIXED
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#define dest_LowestPrio IOSAPIC_LOWEST_PRIORITY
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#define NMI_VECTOR 2
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#define ExtINT_VECTOR 0
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#define NULL_VECTOR (-1)
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#define IA64_SPURIOUS_INT_VECTOR 0x0f
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#define VCPU_LID(v) (((u64)(v)->vcpu_id) << 24)
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/*
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*Delivery mode
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*/
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#define SAPIC_DELIV_SHIFT 8
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#define SAPIC_FIXED 0x0
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#define SAPIC_LOWEST_PRIORITY 0x1
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#define SAPIC_PMI 0x2
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#define SAPIC_NMI 0x4
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#define SAPIC_INIT 0x5
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#define SAPIC_EXTINT 0x7
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/*
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* vcpu->requests bit members for arch
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*/
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#define KVM_REQ_PTC_G 32
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#define KVM_REQ_RESUME 33
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struct kvm_mmio_req {
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uint64_t addr; /* physical address */
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uint64_t size; /* size in bytes */
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uint64_t data; /* data (or paddr of data) */
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uint8_t state:4;
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uint8_t dir:1; /* 1=read, 0=write */
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};
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/*Pal data struct */
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struct kvm_pal_call{
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/*In area*/
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uint64_t gr28;
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uint64_t gr29;
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uint64_t gr30;
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uint64_t gr31;
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/*Out area*/
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struct ia64_pal_retval ret;
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};
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/* Sal data structure */
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struct kvm_sal_call{
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/*In area*/
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uint64_t in0;
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uint64_t in1;
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uint64_t in2;
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uint64_t in3;
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uint64_t in4;
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uint64_t in5;
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uint64_t in6;
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uint64_t in7;
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struct sal_ret_values ret;
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};
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/*Guest change rr6*/
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struct kvm_switch_rr6 {
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uint64_t old_rr;
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uint64_t new_rr;
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};
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union ia64_ipi_a{
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unsigned long val;
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struct {
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unsigned long rv : 3;
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unsigned long ir : 1;
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unsigned long eid : 8;
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unsigned long id : 8;
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unsigned long ib_base : 44;
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};
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};
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union ia64_ipi_d {
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unsigned long val;
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struct {
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unsigned long vector : 8;
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unsigned long dm : 3;
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unsigned long ig : 53;
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};
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};
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/*ipi check exit data*/
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struct kvm_ipi_data{
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union ia64_ipi_a addr;
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union ia64_ipi_d data;
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};
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/*global purge data*/
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struct kvm_ptc_g {
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unsigned long vaddr;
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unsigned long rr;
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unsigned long ps;
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struct kvm_vcpu *vcpu;
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};
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/*Exit control data */
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struct exit_ctl_data{
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uint32_t exit_reason;
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uint32_t vm_status;
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union {
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struct kvm_mmio_req ioreq;
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struct kvm_pal_call pal_data;
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struct kvm_sal_call sal_data;
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struct kvm_switch_rr6 rr_data;
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struct kvm_ipi_data ipi_data;
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struct kvm_ptc_g ptc_g_data;
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} u;
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};
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union pte_flags {
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unsigned long val;
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struct {
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unsigned long p : 1; /*0 */
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unsigned long : 1; /* 1 */
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unsigned long ma : 3; /* 2-4 */
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unsigned long a : 1; /* 5 */
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unsigned long d : 1; /* 6 */
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unsigned long pl : 2; /* 7-8 */
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unsigned long ar : 3; /* 9-11 */
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unsigned long ppn : 38; /* 12-49 */
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unsigned long : 2; /* 50-51 */
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unsigned long ed : 1; /* 52 */
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};
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};
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union ia64_pta {
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unsigned long val;
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struct {
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unsigned long ve : 1;
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unsigned long reserved0 : 1;
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unsigned long size : 6;
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unsigned long vf : 1;
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unsigned long reserved1 : 6;
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unsigned long base : 49;
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};
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||||
};
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struct thash_cb {
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/* THASH base information */
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struct thash_data *hash; /* hash table pointer */
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union ia64_pta pta;
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int num;
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};
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struct kvm_vcpu_stat {
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u32 halt_wakeup;
|
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};
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struct kvm_vcpu_arch {
|
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int launched;
|
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int last_exit;
|
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int last_run_cpu;
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int vmm_tr_slot;
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int vm_tr_slot;
|
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int sn_rtc_tr_slot;
|
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#define KVM_MP_STATE_RUNNABLE 0
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#define KVM_MP_STATE_UNINITIALIZED 1
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#define KVM_MP_STATE_INIT_RECEIVED 2
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||||
#define KVM_MP_STATE_HALTED 3
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int mp_state;
|
||||
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#define MAX_PTC_G_NUM 3
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int ptc_g_count;
|
||||
struct kvm_ptc_g ptc_g_data[MAX_PTC_G_NUM];
|
||||
|
||||
/*halt timer to wake up sleepy vcpus*/
|
||||
struct hrtimer hlt_timer;
|
||||
long ht_active;
|
||||
|
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struct kvm_lapic *apic; /* kernel irqchip context */
|
||||
struct vpd *vpd;
|
||||
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||||
/* Exit data for vmm_transition*/
|
||||
struct exit_ctl_data exit_data;
|
||||
|
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cpumask_t cache_coherent_map;
|
||||
|
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unsigned long vmm_rr;
|
||||
unsigned long host_rr6;
|
||||
unsigned long psbits[8];
|
||||
unsigned long cr_iipa;
|
||||
unsigned long cr_isr;
|
||||
unsigned long vsa_base;
|
||||
unsigned long dirty_log_lock_pa;
|
||||
unsigned long __gp;
|
||||
/* TR and TC. */
|
||||
struct thash_data itrs[NITRS];
|
||||
struct thash_data dtrs[NDTRS];
|
||||
/* Bit is set if there is a tr/tc for the region. */
|
||||
unsigned char itr_regions;
|
||||
unsigned char dtr_regions;
|
||||
unsigned char tc_regions;
|
||||
/* purge all */
|
||||
unsigned long ptce_base;
|
||||
unsigned long ptce_count[2];
|
||||
unsigned long ptce_stride[2];
|
||||
/* itc/itm */
|
||||
unsigned long last_itc;
|
||||
long itc_offset;
|
||||
unsigned long itc_check;
|
||||
unsigned long timer_check;
|
||||
unsigned int timer_pending;
|
||||
unsigned int timer_fired;
|
||||
|
||||
unsigned long vrr[8];
|
||||
unsigned long ibr[8];
|
||||
unsigned long dbr[8];
|
||||
unsigned long insvc[4]; /* Interrupt in service. */
|
||||
unsigned long xtp;
|
||||
|
||||
unsigned long metaphysical_rr0; /* from kvm_arch (so is pinned) */
|
||||
unsigned long metaphysical_rr4; /* from kvm_arch (so is pinned) */
|
||||
unsigned long metaphysical_saved_rr0; /* from kvm_arch */
|
||||
unsigned long metaphysical_saved_rr4; /* from kvm_arch */
|
||||
unsigned long fp_psr; /*used for lazy float register */
|
||||
unsigned long saved_gp;
|
||||
/*for phycial emulation */
|
||||
int mode_flags;
|
||||
struct thash_cb vtlb;
|
||||
struct thash_cb vhpt;
|
||||
char irq_check;
|
||||
char irq_new_pending;
|
||||
|
||||
unsigned long opcode;
|
||||
unsigned long cause;
|
||||
char log_buf[VMM_LOG_LEN];
|
||||
union context host;
|
||||
union context guest;
|
||||
|
||||
char mmio_data[8];
|
||||
};
|
||||
|
||||
struct kvm_vm_stat {
|
||||
u64 remote_tlb_flush;
|
||||
};
|
||||
|
||||
struct kvm_sal_data {
|
||||
unsigned long boot_ip;
|
||||
unsigned long boot_gp;
|
||||
};
|
||||
|
||||
struct kvm_arch_memory_slot {
|
||||
};
|
||||
|
||||
struct kvm_arch {
|
||||
spinlock_t dirty_log_lock;
|
||||
|
||||
unsigned long vm_base;
|
||||
unsigned long metaphysical_rr0;
|
||||
unsigned long metaphysical_rr4;
|
||||
unsigned long vmm_init_rr;
|
||||
|
||||
int is_sn2;
|
||||
|
||||
struct kvm_ioapic *vioapic;
|
||||
struct kvm_vm_stat stat;
|
||||
struct kvm_sal_data rdv_sal_data;
|
||||
|
||||
struct list_head assigned_dev_head;
|
||||
struct iommu_domain *iommu_domain;
|
||||
bool iommu_noncoherent;
|
||||
|
||||
unsigned long irq_sources_bitmap;
|
||||
unsigned long irq_states[KVM_IOAPIC_NUM_PINS];
|
||||
};
|
||||
|
||||
union cpuid3_t {
|
||||
u64 value;
|
||||
struct {
|
||||
u64 number : 8;
|
||||
u64 revision : 8;
|
||||
u64 model : 8;
|
||||
u64 family : 8;
|
||||
u64 archrev : 8;
|
||||
u64 rv : 24;
|
||||
};
|
||||
};
|
||||
|
||||
struct kvm_pt_regs {
|
||||
/* The following registers are saved by SAVE_MIN: */
|
||||
unsigned long b6; /* scratch */
|
||||
unsigned long b7; /* scratch */
|
||||
|
||||
unsigned long ar_csd; /* used by cmp8xchg16 (scratch) */
|
||||
unsigned long ar_ssd; /* reserved for future use (scratch) */
|
||||
|
||||
unsigned long r8; /* scratch (return value register 0) */
|
||||
unsigned long r9; /* scratch (return value register 1) */
|
||||
unsigned long r10; /* scratch (return value register 2) */
|
||||
unsigned long r11; /* scratch (return value register 3) */
|
||||
|
||||
unsigned long cr_ipsr; /* interrupted task's psr */
|
||||
unsigned long cr_iip; /* interrupted task's instruction pointer */
|
||||
unsigned long cr_ifs; /* interrupted task's function state */
|
||||
|
||||
unsigned long ar_unat; /* interrupted task's NaT register (preserved) */
|
||||
unsigned long ar_pfs; /* prev function state */
|
||||
unsigned long ar_rsc; /* RSE configuration */
|
||||
/* The following two are valid only if cr_ipsr.cpl > 0: */
|
||||
unsigned long ar_rnat; /* RSE NaT */
|
||||
unsigned long ar_bspstore; /* RSE bspstore */
|
||||
|
||||
unsigned long pr; /* 64 predicate registers (1 bit each) */
|
||||
unsigned long b0; /* return pointer (bp) */
|
||||
unsigned long loadrs; /* size of dirty partition << 16 */
|
||||
|
||||
unsigned long r1; /* the gp pointer */
|
||||
unsigned long r12; /* interrupted task's memory stack pointer */
|
||||
unsigned long r13; /* thread pointer */
|
||||
|
||||
unsigned long ar_fpsr; /* floating point status (preserved) */
|
||||
unsigned long r15; /* scratch */
|
||||
|
||||
/* The remaining registers are NOT saved for system calls. */
|
||||
unsigned long r14; /* scratch */
|
||||
unsigned long r2; /* scratch */
|
||||
unsigned long r3; /* scratch */
|
||||
unsigned long r16; /* scratch */
|
||||
unsigned long r17; /* scratch */
|
||||
unsigned long r18; /* scratch */
|
||||
unsigned long r19; /* scratch */
|
||||
unsigned long r20; /* scratch */
|
||||
unsigned long r21; /* scratch */
|
||||
unsigned long r22; /* scratch */
|
||||
unsigned long r23; /* scratch */
|
||||
unsigned long r24; /* scratch */
|
||||
unsigned long r25; /* scratch */
|
||||
unsigned long r26; /* scratch */
|
||||
unsigned long r27; /* scratch */
|
||||
unsigned long r28; /* scratch */
|
||||
unsigned long r29; /* scratch */
|
||||
unsigned long r30; /* scratch */
|
||||
unsigned long r31; /* scratch */
|
||||
unsigned long ar_ccv; /* compare/exchange value (scratch) */
|
||||
|
||||
/*
|
||||
* Floating point registers that the kernel considers scratch:
|
||||
*/
|
||||
struct ia64_fpreg f6; /* scratch */
|
||||
struct ia64_fpreg f7; /* scratch */
|
||||
struct ia64_fpreg f8; /* scratch */
|
||||
struct ia64_fpreg f9; /* scratch */
|
||||
struct ia64_fpreg f10; /* scratch */
|
||||
struct ia64_fpreg f11; /* scratch */
|
||||
|
||||
unsigned long r4; /* preserved */
|
||||
unsigned long r5; /* preserved */
|
||||
unsigned long r6; /* preserved */
|
||||
unsigned long r7; /* preserved */
|
||||
unsigned long eml_unat; /* used for emulating instruction */
|
||||
unsigned long pad0; /* alignment pad */
|
||||
};
|
||||
|
||||
static inline struct kvm_pt_regs *vcpu_regs(struct kvm_vcpu *v)
|
||||
{
|
||||
return (struct kvm_pt_regs *) ((unsigned long) v + KVM_STK_OFFSET) - 1;
|
||||
}
|
||||
|
||||
typedef int kvm_vmm_entry(void);
|
||||
typedef void kvm_tramp_entry(union context *host, union context *guest);
|
||||
|
||||
struct kvm_vmm_info{
|
||||
struct module *module;
|
||||
kvm_vmm_entry *vmm_entry;
|
||||
kvm_tramp_entry *tramp_entry;
|
||||
unsigned long vmm_ivt;
|
||||
unsigned long patch_mov_ar;
|
||||
unsigned long patch_mov_ar_sn2;
|
||||
};
|
||||
|
||||
int kvm_highest_pending_irq(struct kvm_vcpu *vcpu);
|
||||
int kvm_emulate_halt(struct kvm_vcpu *vcpu);
|
||||
int kvm_pal_emul(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run);
|
||||
void kvm_sal_emul(struct kvm_vcpu *vcpu);
|
||||
|
||||
#define __KVM_HAVE_ARCH_VM_ALLOC 1
|
||||
struct kvm *kvm_arch_alloc_vm(void);
|
||||
void kvm_arch_free_vm(struct kvm *kvm);
|
||||
|
||||
static inline void kvm_arch_sync_events(struct kvm *kvm) {}
|
||||
static inline void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu) {}
|
||||
static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu) {}
|
||||
static inline void kvm_arch_free_memslot(struct kvm *kvm,
|
||||
struct kvm_memory_slot *free, struct kvm_memory_slot *dont) {}
|
||||
static inline void kvm_arch_memslots_updated(struct kvm *kvm) {}
|
||||
static inline void kvm_arch_commit_memory_region(struct kvm *kvm,
|
||||
struct kvm_userspace_memory_region *mem,
|
||||
const struct kvm_memory_slot *old,
|
||||
enum kvm_mr_change change) {}
|
||||
static inline void kvm_arch_hardware_unsetup(void) {}
|
||||
|
||||
#endif /* __ASSEMBLY__*/
|
||||
|
||||
#endif
|
|
@ -1,48 +0,0 @@
|
|||
/*
|
||||
* same structure to x86's
|
||||
* Hopefully asm-x86/pvclock-abi.h would be moved to somewhere more generic.
|
||||
* For now, define same duplicated definitions.
|
||||
*/
|
||||
|
||||
#ifndef _ASM_IA64__PVCLOCK_ABI_H
|
||||
#define _ASM_IA64__PVCLOCK_ABI_H
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/*
|
||||
* These structs MUST NOT be changed.
|
||||
* They are the ABI between hypervisor and guest OS.
|
||||
* KVM is using this.
|
||||
*
|
||||
* pvclock_vcpu_time_info holds the system time and the tsc timestamp
|
||||
* of the last update. So the guest can use the tsc delta to get a
|
||||
* more precise system time. There is one per virtual cpu.
|
||||
*
|
||||
* pvclock_wall_clock references the point in time when the system
|
||||
* time was zero (usually boot time), thus the guest calculates the
|
||||
* current wall clock by adding the system time.
|
||||
*
|
||||
* Protocol for the "version" fields is: hypervisor raises it (making
|
||||
* it uneven) before it starts updating the fields and raises it again
|
||||
* (making it even) when it is done. Thus the guest can make sure the
|
||||
* time values it got are consistent by checking the version before
|
||||
* and after reading them.
|
||||
*/
|
||||
|
||||
struct pvclock_vcpu_time_info {
|
||||
u32 version;
|
||||
u32 pad0;
|
||||
u64 tsc_timestamp;
|
||||
u64 system_time;
|
||||
u32 tsc_to_system_mul;
|
||||
s8 tsc_shift;
|
||||
u8 pad[3];
|
||||
} __attribute__((__packed__)); /* 32 bytes */
|
||||
|
||||
struct pvclock_wall_clock {
|
||||
u32 version;
|
||||
u32 sec;
|
||||
u32 nsec;
|
||||
} __attribute__((__packed__));
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* _ASM_IA64__PVCLOCK_ABI_H */
|
|
@ -1,268 +0,0 @@
|
|||
#ifndef __ASM_IA64_KVM_H
|
||||
#define __ASM_IA64_KVM_H
|
||||
|
||||
/*
|
||||
* kvm structure definitions for ia64
|
||||
*
|
||||
* Copyright (C) 2007 Xiantao Zhang <xiantao.zhang@intel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/ioctl.h>
|
||||
|
||||
/* Select x86 specific features in <linux/kvm.h> */
|
||||
#define __KVM_HAVE_IOAPIC
|
||||
#define __KVM_HAVE_IRQ_LINE
|
||||
|
||||
/* Architectural interrupt line count. */
|
||||
#define KVM_NR_INTERRUPTS 256
|
||||
|
||||
#define KVM_IOAPIC_NUM_PINS 48
|
||||
|
||||
struct kvm_ioapic_state {
|
||||
__u64 base_address;
|
||||
__u32 ioregsel;
|
||||
__u32 id;
|
||||
__u32 irr;
|
||||
__u32 pad;
|
||||
union {
|
||||
__u64 bits;
|
||||
struct {
|
||||
__u8 vector;
|
||||
__u8 delivery_mode:3;
|
||||
__u8 dest_mode:1;
|
||||
__u8 delivery_status:1;
|
||||
__u8 polarity:1;
|
||||
__u8 remote_irr:1;
|
||||
__u8 trig_mode:1;
|
||||
__u8 mask:1;
|
||||
__u8 reserve:7;
|
||||
__u8 reserved[4];
|
||||
__u8 dest_id;
|
||||
} fields;
|
||||
} redirtbl[KVM_IOAPIC_NUM_PINS];
|
||||
};
|
||||
|
||||
#define KVM_IRQCHIP_PIC_MASTER 0
|
||||
#define KVM_IRQCHIP_PIC_SLAVE 1
|
||||
#define KVM_IRQCHIP_IOAPIC 2
|
||||
#define KVM_NR_IRQCHIPS 3
|
||||
|
||||
#define KVM_CONTEXT_SIZE 8*1024
|
||||
|
||||
struct kvm_fpreg {
|
||||
union {
|
||||
unsigned long bits[2];
|
||||
long double __dummy; /* force 16-byte alignment */
|
||||
} u;
|
||||
};
|
||||
|
||||
union context {
|
||||
/* 8K size */
|
||||
char dummy[KVM_CONTEXT_SIZE];
|
||||
struct {
|
||||
unsigned long psr;
|
||||
unsigned long pr;
|
||||
unsigned long caller_unat;
|
||||
unsigned long pad;
|
||||
unsigned long gr[32];
|
||||
unsigned long ar[128];
|
||||
unsigned long br[8];
|
||||
unsigned long cr[128];
|
||||
unsigned long rr[8];
|
||||
unsigned long ibr[8];
|
||||
unsigned long dbr[8];
|
||||
unsigned long pkr[8];
|
||||
struct kvm_fpreg fr[128];
|
||||
};
|
||||
};
|
||||
|
||||
struct thash_data {
|
||||
union {
|
||||
struct {
|
||||
unsigned long p : 1; /* 0 */
|
||||
unsigned long rv1 : 1; /* 1 */
|
||||
unsigned long ma : 3; /* 2-4 */
|
||||
unsigned long a : 1; /* 5 */
|
||||
unsigned long d : 1; /* 6 */
|
||||
unsigned long pl : 2; /* 7-8 */
|
||||
unsigned long ar : 3; /* 9-11 */
|
||||
unsigned long ppn : 38; /* 12-49 */
|
||||
unsigned long rv2 : 2; /* 50-51 */
|
||||
unsigned long ed : 1; /* 52 */
|
||||
unsigned long ig1 : 11; /* 53-63 */
|
||||
};
|
||||
struct {
|
||||
unsigned long __rv1 : 53; /* 0-52 */
|
||||
unsigned long contiguous : 1; /*53 */
|
||||
unsigned long tc : 1; /* 54 TR or TC */
|
||||
unsigned long cl : 1;
|
||||
/* 55 I side or D side cache line */
|
||||
unsigned long len : 4; /* 56-59 */
|
||||
unsigned long io : 1; /* 60 entry is for io or not */
|
||||
unsigned long nomap : 1;
|
||||
/* 61 entry cann't be inserted into machine TLB.*/
|
||||
unsigned long checked : 1;
|
||||
/* 62 for VTLB/VHPT sanity check */
|
||||
unsigned long invalid : 1;
|
||||
/* 63 invalid entry */
|
||||
};
|
||||
unsigned long page_flags;
|
||||
}; /* same for VHPT and TLB */
|
||||
|
||||
union {
|
||||
struct {
|
||||
unsigned long rv3 : 2;
|
||||
unsigned long ps : 6;
|
||||
unsigned long key : 24;
|
||||
unsigned long rv4 : 32;
|
||||
};
|
||||
unsigned long itir;
|
||||
};
|
||||
union {
|
||||
struct {
|
||||
unsigned long ig2 : 12;
|
||||
unsigned long vpn : 49;
|
||||
unsigned long vrn : 3;
|
||||
};
|
||||
unsigned long ifa;
|
||||
unsigned long vadr;
|
||||
struct {
|
||||
unsigned long tag : 63;
|
||||
unsigned long ti : 1;
|
||||
};
|
||||
unsigned long etag;
|
||||
};
|
||||
union {
|
||||
struct thash_data *next;
|
||||
unsigned long rid;
|
||||
unsigned long gpaddr;
|
||||
};
|
||||
};
|
||||
|
||||
#define NITRS 8
|
||||
#define NDTRS 8
|
||||
|
||||
struct saved_vpd {
|
||||
unsigned long vhpi;
|
||||
unsigned long vgr[16];
|
||||
unsigned long vbgr[16];
|
||||
unsigned long vnat;
|
||||
unsigned long vbnat;
|
||||
unsigned long vcpuid[5];
|
||||
unsigned long vpsr;
|
||||
unsigned long vpr;
|
||||
union {
|
||||
unsigned long vcr[128];
|
||||
struct {
|
||||
unsigned long dcr;
|
||||
unsigned long itm;
|
||||
unsigned long iva;
|
||||
unsigned long rsv1[5];
|
||||
unsigned long pta;
|
||||
unsigned long rsv2[7];
|
||||
unsigned long ipsr;
|
||||
unsigned long isr;
|
||||
unsigned long rsv3;
|
||||
unsigned long iip;
|
||||
unsigned long ifa;
|
||||
unsigned long itir;
|
||||
unsigned long iipa;
|
||||
unsigned long ifs;
|
||||
unsigned long iim;
|
||||
unsigned long iha;
|
||||
unsigned long rsv4[38];
|
||||
unsigned long lid;
|
||||
unsigned long ivr;
|
||||
unsigned long tpr;
|
||||
unsigned long eoi;
|
||||
unsigned long irr[4];
|
||||
unsigned long itv;
|
||||
unsigned long pmv;
|
||||
unsigned long cmcv;
|
||||
unsigned long rsv5[5];
|
||||
unsigned long lrr0;
|
||||
unsigned long lrr1;
|
||||
unsigned long rsv6[46];
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
struct kvm_regs {
|
||||
struct saved_vpd vpd;
|
||||
/*Arch-regs*/
|
||||
int mp_state;
|
||||
unsigned long vmm_rr;
|
||||
/* TR and TC. */
|
||||
struct thash_data itrs[NITRS];
|
||||
struct thash_data dtrs[NDTRS];
|
||||
/* Bit is set if there is a tr/tc for the region. */
|
||||
unsigned char itr_regions;
|
||||
unsigned char dtr_regions;
|
||||
unsigned char tc_regions;
|
||||
|
||||
char irq_check;
|
||||
unsigned long saved_itc;
|
||||
unsigned long itc_check;
|
||||
unsigned long timer_check;
|
||||
unsigned long timer_pending;
|
||||
unsigned long last_itc;
|
||||
|
||||
unsigned long vrr[8];
|
||||
unsigned long ibr[8];
|
||||
unsigned long dbr[8];
|
||||
unsigned long insvc[4]; /* Interrupt in service. */
|
||||
unsigned long xtp;
|
||||
|
||||
unsigned long metaphysical_rr0; /* from kvm_arch (so is pinned) */
|
||||
unsigned long metaphysical_rr4; /* from kvm_arch (so is pinned) */
|
||||
unsigned long metaphysical_saved_rr0; /* from kvm_arch */
|
||||
unsigned long metaphysical_saved_rr4; /* from kvm_arch */
|
||||
unsigned long fp_psr; /*used for lazy float register */
|
||||
unsigned long saved_gp;
|
||||
/*for phycial emulation */
|
||||
|
||||
union context saved_guest;
|
||||
|
||||
unsigned long reserved[64]; /* for future use */
|
||||
};
|
||||
|
||||
struct kvm_sregs {
|
||||
};
|
||||
|
||||
struct kvm_fpu {
|
||||
};
|
||||
|
||||
#define KVM_IA64_VCPU_STACK_SHIFT 16
|
||||
#define KVM_IA64_VCPU_STACK_SIZE (1UL << KVM_IA64_VCPU_STACK_SHIFT)
|
||||
|
||||
struct kvm_ia64_vcpu_stack {
|
||||
unsigned char stack[KVM_IA64_VCPU_STACK_SIZE];
|
||||
};
|
||||
|
||||
struct kvm_debug_exit_arch {
|
||||
};
|
||||
|
||||
/* for KVM_SET_GUEST_DEBUG */
|
||||
struct kvm_guest_debug_arch {
|
||||
};
|
||||
|
||||
/* definition of registers in kvm_run */
|
||||
struct kvm_sync_regs {
|
||||
};
|
||||
|
||||
#endif
|
|
@ -1,66 +0,0 @@
|
|||
#
|
||||
# KVM configuration
|
||||
#
|
||||
|
||||
source "virt/kvm/Kconfig"
|
||||
|
||||
menuconfig VIRTUALIZATION
|
||||
bool "Virtualization"
|
||||
depends on HAVE_KVM || IA64
|
||||
default y
|
||||
---help---
|
||||
Say Y here to get to see options for using your Linux host to run other
|
||||
operating systems inside virtual machines (guests).
|
||||
This option alone does not add any kernel code.
|
||||
|
||||
If you say N, all options in this submenu will be skipped and disabled.
|
||||
|
||||
if VIRTUALIZATION
|
||||
|
||||
config KVM
|
||||
tristate "Kernel-based Virtual Machine (KVM) support"
|
||||
depends on BROKEN
|
||||
depends on HAVE_KVM && MODULES
|
||||
depends on BROKEN
|
||||
select PREEMPT_NOTIFIERS
|
||||
select ANON_INODES
|
||||
select HAVE_KVM_IRQCHIP
|
||||
select HAVE_KVM_IRQFD
|
||||
select HAVE_KVM_IRQ_ROUTING
|
||||
select KVM_APIC_ARCHITECTURE
|
||||
select KVM_MMIO
|
||||
---help---
|
||||
Support hosting fully virtualized guest machines using hardware
|
||||
virtualization extensions. You will need a fairly recent
|
||||
processor equipped with virtualization extensions. You will also
|
||||
need to select one or more of the processor modules below.
|
||||
|
||||
This module provides access to the hardware capabilities through
|
||||
a character device node named /dev/kvm.
|
||||
|
||||
To compile this as a module, choose M here: the module
|
||||
will be called kvm.
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
config KVM_INTEL
|
||||
tristate "KVM for Intel Itanium 2 processors support"
|
||||
depends on KVM && m
|
||||
---help---
|
||||
Provides support for KVM on Itanium 2 processors equipped with the VT
|
||||
extensions.
|
||||
|
||||
config KVM_DEVICE_ASSIGNMENT
|
||||
bool "KVM legacy PCI device assignment support"
|
||||
depends on KVM && PCI && IOMMU_API
|
||||
default y
|
||||
---help---
|
||||
Provide support for legacy PCI device assignment through KVM. The
|
||||
kernel now also supports a full featured userspace device driver
|
||||
framework through VFIO, which supersedes much of this support.
|
||||
|
||||
If unsure, say Y.
|
||||
|
||||
source drivers/vhost/Kconfig
|
||||
|
||||
endif # VIRTUALIZATION
|
|
@ -1,67 +0,0 @@
|
|||
#This Make file is to generate asm-offsets.h and build source.
|
||||
#
|
||||
|
||||
#Generate asm-offsets.h for vmm module build
|
||||
offsets-file := asm-offsets.h
|
||||
|
||||
always := $(offsets-file)
|
||||
targets := $(offsets-file)
|
||||
targets += arch/ia64/kvm/asm-offsets.s
|
||||
|
||||
# Default sed regexp - multiline due to syntax constraints
|
||||
define sed-y
|
||||
"/^->/{s:^->\([^ ]*\) [\$$#]*\([^ ]*\) \(.*\):#define \1 \2 /* \3 */:; s:->::; p;}"
|
||||
endef
|
||||
|
||||
quiet_cmd_offsets = GEN $@
|
||||
define cmd_offsets
|
||||
(set -e; \
|
||||
echo "#ifndef __ASM_KVM_OFFSETS_H__"; \
|
||||
echo "#define __ASM_KVM_OFFSETS_H__"; \
|
||||
echo "/*"; \
|
||||
echo " * DO NOT MODIFY."; \
|
||||
echo " *"; \
|
||||
echo " * This file was generated by Makefile"; \
|
||||
echo " *"; \
|
||||
echo " */"; \
|
||||
echo ""; \
|
||||
sed -ne $(sed-y) $<; \
|
||||
echo ""; \
|
||||
echo "#endif" ) > $@
|
||||
endef
|
||||
|
||||
# We use internal rules to avoid the "is up to date" message from make
|
||||
arch/ia64/kvm/asm-offsets.s: arch/ia64/kvm/asm-offsets.c \
|
||||
$(wildcard $(srctree)/arch/ia64/include/asm/*.h)\
|
||||
$(wildcard $(srctree)/include/linux/*.h)
|
||||
$(call if_changed_dep,cc_s_c)
|
||||
|
||||
$(obj)/$(offsets-file): arch/ia64/kvm/asm-offsets.s
|
||||
$(call cmd,offsets)
|
||||
|
||||
FORCE : $(obj)/$(offsets-file)
|
||||
|
||||
#
|
||||
# Makefile for Kernel-based Virtual Machine module
|
||||
#
|
||||
|
||||
ccflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
|
||||
asflags-y := -Ivirt/kvm -Iarch/ia64/kvm/
|
||||
KVM := ../../../virt/kvm
|
||||
|
||||
common-objs = $(KVM)/kvm_main.o $(KVM)/ioapic.o \
|
||||
$(KVM)/coalesced_mmio.o $(KVM)/irq_comm.o
|
||||
|
||||
ifeq ($(CONFIG_KVM_DEVICE_ASSIGNMENT),y)
|
||||
common-objs += $(KVM)/assigned-dev.o $(KVM)/iommu.o
|
||||
endif
|
||||
|
||||
kvm-objs := $(common-objs) kvm-ia64.o kvm_fw.o
|
||||
obj-$(CONFIG_KVM) += kvm.o
|
||||
|
||||
CFLAGS_vcpu.o += -mfixed-range=f2-f5,f12-f127
|
||||
kvm-intel-objs = vmm.o vmm_ivt.o trampoline.o vcpu.o optvfault.o mmio.o \
|
||||
vtlb.o process.o kvm_lib.o
|
||||
#Add link memcpy and memset to avoid possible structure assignment error
|
||||
kvm-intel-objs += memcpy.o memset.o
|
||||
obj-$(CONFIG_KVM_INTEL) += kvm-intel.o
|
|
@ -1,241 +0,0 @@
|
|||
/*
|
||||
* asm-offsets.c Generate definitions needed by assembly language modules.
|
||||
* This code generates raw asm output which is post-processed
|
||||
* to extract and format the required data.
|
||||
*
|
||||
* Anthony Xu <anthony.xu@intel.com>
|
||||
* Xiantao Zhang <xiantao.zhang@intel.com>
|
||||
* Copyright (c) 2007 Intel Corporation KVM support.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kvm_host.h>
|
||||
#include <linux/kbuild.h>
|
||||
|
||||
#include "vcpu.h"
|
||||
|
||||
void foo(void)
|
||||
{
|
||||
DEFINE(VMM_TASK_SIZE, sizeof(struct kvm_vcpu));
|
||||
DEFINE(VMM_PT_REGS_SIZE, sizeof(struct kvm_pt_regs));
|
||||
|
||||
BLANK();
|
||||
|
||||
DEFINE(VMM_VCPU_META_RR0_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.metaphysical_rr0));
|
||||
DEFINE(VMM_VCPU_META_SAVED_RR0_OFFSET,
|
||||
offsetof(struct kvm_vcpu,
|
||||
arch.metaphysical_saved_rr0));
|
||||
DEFINE(VMM_VCPU_VRR0_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.vrr[0]));
|
||||
DEFINE(VMM_VPD_IRR0_OFFSET,
|
||||
offsetof(struct vpd, irr[0]));
|
||||
DEFINE(VMM_VCPU_ITC_CHECK_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.itc_check));
|
||||
DEFINE(VMM_VCPU_IRQ_CHECK_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.irq_check));
|
||||
DEFINE(VMM_VPD_VHPI_OFFSET,
|
||||
offsetof(struct vpd, vhpi));
|
||||
DEFINE(VMM_VCPU_VSA_BASE_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.vsa_base));
|
||||
DEFINE(VMM_VCPU_VPD_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.vpd));
|
||||
DEFINE(VMM_VCPU_IRQ_CHECK,
|
||||
offsetof(struct kvm_vcpu, arch.irq_check));
|
||||
DEFINE(VMM_VCPU_TIMER_PENDING,
|
||||
offsetof(struct kvm_vcpu, arch.timer_pending));
|
||||
DEFINE(VMM_VCPU_META_SAVED_RR0_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.metaphysical_saved_rr0));
|
||||
DEFINE(VMM_VCPU_MODE_FLAGS_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.mode_flags));
|
||||
DEFINE(VMM_VCPU_ITC_OFS_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.itc_offset));
|
||||
DEFINE(VMM_VCPU_LAST_ITC_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.last_itc));
|
||||
DEFINE(VMM_VCPU_SAVED_GP_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.saved_gp));
|
||||
|
||||
BLANK();
|
||||
|
||||
DEFINE(VMM_PT_REGS_B6_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, b6));
|
||||
DEFINE(VMM_PT_REGS_B7_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, b7));
|
||||
DEFINE(VMM_PT_REGS_AR_CSD_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, ar_csd));
|
||||
DEFINE(VMM_PT_REGS_AR_SSD_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, ar_ssd));
|
||||
DEFINE(VMM_PT_REGS_R8_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r8));
|
||||
DEFINE(VMM_PT_REGS_R9_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r9));
|
||||
DEFINE(VMM_PT_REGS_R10_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r10));
|
||||
DEFINE(VMM_PT_REGS_R11_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r11));
|
||||
DEFINE(VMM_PT_REGS_CR_IPSR_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, cr_ipsr));
|
||||
DEFINE(VMM_PT_REGS_CR_IIP_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, cr_iip));
|
||||
DEFINE(VMM_PT_REGS_CR_IFS_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, cr_ifs));
|
||||
DEFINE(VMM_PT_REGS_AR_UNAT_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, ar_unat));
|
||||
DEFINE(VMM_PT_REGS_AR_PFS_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, ar_pfs));
|
||||
DEFINE(VMM_PT_REGS_AR_RSC_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, ar_rsc));
|
||||
DEFINE(VMM_PT_REGS_AR_RNAT_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, ar_rnat));
|
||||
|
||||
DEFINE(VMM_PT_REGS_AR_BSPSTORE_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, ar_bspstore));
|
||||
DEFINE(VMM_PT_REGS_PR_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, pr));
|
||||
DEFINE(VMM_PT_REGS_B0_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, b0));
|
||||
DEFINE(VMM_PT_REGS_LOADRS_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, loadrs));
|
||||
DEFINE(VMM_PT_REGS_R1_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r1));
|
||||
DEFINE(VMM_PT_REGS_R12_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r12));
|
||||
DEFINE(VMM_PT_REGS_R13_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r13));
|
||||
DEFINE(VMM_PT_REGS_AR_FPSR_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, ar_fpsr));
|
||||
DEFINE(VMM_PT_REGS_R15_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r15));
|
||||
DEFINE(VMM_PT_REGS_R14_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r14));
|
||||
DEFINE(VMM_PT_REGS_R2_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r2));
|
||||
DEFINE(VMM_PT_REGS_R3_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r3));
|
||||
DEFINE(VMM_PT_REGS_R16_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r16));
|
||||
DEFINE(VMM_PT_REGS_R17_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r17));
|
||||
DEFINE(VMM_PT_REGS_R18_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r18));
|
||||
DEFINE(VMM_PT_REGS_R19_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r19));
|
||||
DEFINE(VMM_PT_REGS_R20_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r20));
|
||||
DEFINE(VMM_PT_REGS_R21_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r21));
|
||||
DEFINE(VMM_PT_REGS_R22_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r22));
|
||||
DEFINE(VMM_PT_REGS_R23_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r23));
|
||||
DEFINE(VMM_PT_REGS_R24_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r24));
|
||||
DEFINE(VMM_PT_REGS_R25_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r25));
|
||||
DEFINE(VMM_PT_REGS_R26_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r26));
|
||||
DEFINE(VMM_PT_REGS_R27_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r27));
|
||||
DEFINE(VMM_PT_REGS_R28_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r28));
|
||||
DEFINE(VMM_PT_REGS_R29_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r29));
|
||||
DEFINE(VMM_PT_REGS_R30_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r30));
|
||||
DEFINE(VMM_PT_REGS_R31_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r31));
|
||||
DEFINE(VMM_PT_REGS_AR_CCV_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, ar_ccv));
|
||||
DEFINE(VMM_PT_REGS_F6_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, f6));
|
||||
DEFINE(VMM_PT_REGS_F7_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, f7));
|
||||
DEFINE(VMM_PT_REGS_F8_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, f8));
|
||||
DEFINE(VMM_PT_REGS_F9_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, f9));
|
||||
DEFINE(VMM_PT_REGS_F10_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, f10));
|
||||
DEFINE(VMM_PT_REGS_F11_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, f11));
|
||||
DEFINE(VMM_PT_REGS_R4_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r4));
|
||||
DEFINE(VMM_PT_REGS_R5_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r5));
|
||||
DEFINE(VMM_PT_REGS_R6_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r6));
|
||||
DEFINE(VMM_PT_REGS_R7_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, r7));
|
||||
DEFINE(VMM_PT_REGS_EML_UNAT_OFFSET,
|
||||
offsetof(struct kvm_pt_regs, eml_unat));
|
||||
DEFINE(VMM_VCPU_IIPA_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.cr_iipa));
|
||||
DEFINE(VMM_VCPU_OPCODE_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.opcode));
|
||||
DEFINE(VMM_VCPU_CAUSE_OFFSET, offsetof(struct kvm_vcpu, arch.cause));
|
||||
DEFINE(VMM_VCPU_ISR_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.cr_isr));
|
||||
DEFINE(VMM_PT_REGS_R16_SLOT,
|
||||
(((offsetof(struct kvm_pt_regs, r16)
|
||||
- sizeof(struct kvm_pt_regs)) >> 3) & 0x3f));
|
||||
DEFINE(VMM_VCPU_MODE_FLAGS_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.mode_flags));
|
||||
DEFINE(VMM_VCPU_GP_OFFSET, offsetof(struct kvm_vcpu, arch.__gp));
|
||||
BLANK();
|
||||
|
||||
DEFINE(VMM_VPD_BASE_OFFSET, offsetof(struct kvm_vcpu, arch.vpd));
|
||||
DEFINE(VMM_VPD_VIFS_OFFSET, offsetof(struct vpd, ifs));
|
||||
DEFINE(VMM_VLSAPIC_INSVC_BASE_OFFSET,
|
||||
offsetof(struct kvm_vcpu, arch.insvc[0]));
|
||||
DEFINE(VMM_VPD_VPTA_OFFSET, offsetof(struct vpd, pta));
|
||||
DEFINE(VMM_VPD_VPSR_OFFSET, offsetof(struct vpd, vpsr));
|
||||
|
||||
DEFINE(VMM_CTX_R4_OFFSET, offsetof(union context, gr[4]));
|
||||
DEFINE(VMM_CTX_R5_OFFSET, offsetof(union context, gr[5]));
|
||||
DEFINE(VMM_CTX_R12_OFFSET, offsetof(union context, gr[12]));
|
||||
DEFINE(VMM_CTX_R13_OFFSET, offsetof(union context, gr[13]));
|
||||
DEFINE(VMM_CTX_KR0_OFFSET, offsetof(union context, ar[0]));
|
||||
DEFINE(VMM_CTX_KR1_OFFSET, offsetof(union context, ar[1]));
|
||||
DEFINE(VMM_CTX_B0_OFFSET, offsetof(union context, br[0]));
|
||||
DEFINE(VMM_CTX_B1_OFFSET, offsetof(union context, br[1]));
|
||||
DEFINE(VMM_CTX_B2_OFFSET, offsetof(union context, br[2]));
|
||||
DEFINE(VMM_CTX_RR0_OFFSET, offsetof(union context, rr[0]));
|
||||
DEFINE(VMM_CTX_RSC_OFFSET, offsetof(union context, ar[16]));
|
||||
DEFINE(VMM_CTX_BSPSTORE_OFFSET, offsetof(union context, ar[18]));
|
||||
DEFINE(VMM_CTX_RNAT_OFFSET, offsetof(union context, ar[19]));
|
||||
DEFINE(VMM_CTX_FCR_OFFSET, offsetof(union context, ar[21]));
|
||||
DEFINE(VMM_CTX_EFLAG_OFFSET, offsetof(union context, ar[24]));
|
||||
DEFINE(VMM_CTX_CFLG_OFFSET, offsetof(union context, ar[27]));
|
||||
DEFINE(VMM_CTX_FSR_OFFSET, offsetof(union context, ar[28]));
|
||||
DEFINE(VMM_CTX_FIR_OFFSET, offsetof(union context, ar[29]));
|
||||
DEFINE(VMM_CTX_FDR_OFFSET, offsetof(union context, ar[30]));
|
||||
DEFINE(VMM_CTX_UNAT_OFFSET, offsetof(union context, ar[36]));
|
||||
DEFINE(VMM_CTX_FPSR_OFFSET, offsetof(union context, ar[40]));
|
||||
DEFINE(VMM_CTX_PFS_OFFSET, offsetof(union context, ar[64]));
|
||||
DEFINE(VMM_CTX_LC_OFFSET, offsetof(union context, ar[65]));
|
||||
DEFINE(VMM_CTX_DCR_OFFSET, offsetof(union context, cr[0]));
|
||||
DEFINE(VMM_CTX_IVA_OFFSET, offsetof(union context, cr[2]));
|
||||
DEFINE(VMM_CTX_PTA_OFFSET, offsetof(union context, cr[8]));
|
||||
DEFINE(VMM_CTX_IBR0_OFFSET, offsetof(union context, ibr[0]));
|
||||
DEFINE(VMM_CTX_DBR0_OFFSET, offsetof(union context, dbr[0]));
|
||||
DEFINE(VMM_CTX_F2_OFFSET, offsetof(union context, fr[2]));
|
||||
DEFINE(VMM_CTX_F3_OFFSET, offsetof(union context, fr[3]));
|
||||
DEFINE(VMM_CTX_F32_OFFSET, offsetof(union context, fr[32]));
|
||||
DEFINE(VMM_CTX_F33_OFFSET, offsetof(union context, fr[33]));
|
||||
DEFINE(VMM_CTX_PKR0_OFFSET, offsetof(union context, pkr[0]));
|
||||
DEFINE(VMM_CTX_PSR_OFFSET, offsetof(union context, psr));
|
||||
BLANK();
|
||||
}
|
|
@ -1,33 +0,0 @@
|
|||
/*
|
||||
* irq.h: In-kernel interrupt controller related definitions
|
||||
* Copyright (c) 2008, Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
||||
*
|
||||
* Authors:
|
||||
* Xiantao Zhang <xiantao.zhang@intel.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __IRQ_H
|
||||
#define __IRQ_H
|
||||
|
||||
#include "lapic.h"
|
||||
|
||||
static inline int irqchip_in_kernel(struct kvm *kvm)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
#endif
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -1,674 +0,0 @@
|
|||
/*
|
||||
* PAL/SAL call delegation
|
||||
*
|
||||
* Copyright (c) 2004 Li Susie <susie.li@intel.com>
|
||||
* Copyright (c) 2005 Yu Ke <ke.yu@intel.com>
|
||||
* Copyright (c) 2007 Xiantao Zhang <xiantao.zhang@intel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
||||
*/
|
||||
|
||||
#include <linux/kvm_host.h>
|
||||
#include <linux/smp.h>
|
||||
#include <asm/sn/addrs.h>
|
||||
#include <asm/sn/clksupport.h>
|
||||
#include <asm/sn/shub_mmr.h>
|
||||
|
||||
#include "vti.h"
|
||||
#include "misc.h"
|
||||
|
||||
#include <asm/pal.h>
|
||||
#include <asm/sal.h>
|
||||
#include <asm/tlb.h>
|
||||
|
||||
/*
|
||||
* Handy macros to make sure that the PAL return values start out
|
||||
* as something meaningful.
|
||||
*/
|
||||
#define INIT_PAL_STATUS_UNIMPLEMENTED(x) \
|
||||
{ \
|
||||
x.status = PAL_STATUS_UNIMPLEMENTED; \
|
||||
x.v0 = 0; \
|
||||
x.v1 = 0; \
|
||||
x.v2 = 0; \
|
||||
}
|
||||
|
||||
#define INIT_PAL_STATUS_SUCCESS(x) \
|
||||
{ \
|
||||
x.status = PAL_STATUS_SUCCESS; \
|
||||
x.v0 = 0; \
|
||||
x.v1 = 0; \
|
||||
x.v2 = 0; \
|
||||
}
|
||||
|
||||
static void kvm_get_pal_call_data(struct kvm_vcpu *vcpu,
|
||||
u64 *gr28, u64 *gr29, u64 *gr30, u64 *gr31) {
|
||||
struct exit_ctl_data *p;
|
||||
|
||||
if (vcpu) {
|
||||
p = &vcpu->arch.exit_data;
|
||||
if (p->exit_reason == EXIT_REASON_PAL_CALL) {
|
||||
*gr28 = p->u.pal_data.gr28;
|
||||
*gr29 = p->u.pal_data.gr29;
|
||||
*gr30 = p->u.pal_data.gr30;
|
||||
*gr31 = p->u.pal_data.gr31;
|
||||
return ;
|
||||
}
|
||||
}
|
||||
printk(KERN_DEBUG"Failed to get vcpu pal data!!!\n");
|
||||
}
|
||||
|
||||
static void set_pal_result(struct kvm_vcpu *vcpu,
|
||||
struct ia64_pal_retval result) {
|
||||
|
||||
struct exit_ctl_data *p;
|
||||
|
||||
p = kvm_get_exit_data(vcpu);
|
||||
if (p->exit_reason == EXIT_REASON_PAL_CALL) {
|
||||
p->u.pal_data.ret = result;
|
||||
return ;
|
||||
}
|
||||
INIT_PAL_STATUS_UNIMPLEMENTED(p->u.pal_data.ret);
|
||||
}
|
||||
|
||||
static void set_sal_result(struct kvm_vcpu *vcpu,
|
||||
struct sal_ret_values result) {
|
||||
struct exit_ctl_data *p;
|
||||
|
||||
p = kvm_get_exit_data(vcpu);
|
||||
if (p->exit_reason == EXIT_REASON_SAL_CALL) {
|
||||
p->u.sal_data.ret = result;
|
||||
return ;
|
||||
}
|
||||
printk(KERN_WARNING"Failed to set sal result!!\n");
|
||||
}
|
||||
|
||||
struct cache_flush_args {
|
||||
u64 cache_type;
|
||||
u64 operation;
|
||||
u64 progress;
|
||||
long status;
|
||||
};
|
||||
|
||||
cpumask_t cpu_cache_coherent_map;
|
||||
|
||||
static void remote_pal_cache_flush(void *data)
|
||||
{
|
||||
struct cache_flush_args *args = data;
|
||||
long status;
|
||||
u64 progress = args->progress;
|
||||
|
||||
status = ia64_pal_cache_flush(args->cache_type, args->operation,
|
||||
&progress, NULL);
|
||||
if (status != 0)
|
||||
args->status = status;
|
||||
}
|
||||
|
||||
static struct ia64_pal_retval pal_cache_flush(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
u64 gr28, gr29, gr30, gr31;
|
||||
struct ia64_pal_retval result = {0, 0, 0, 0};
|
||||
struct cache_flush_args args = {0, 0, 0, 0};
|
||||
long psr;
|
||||
|
||||
gr28 = gr29 = gr30 = gr31 = 0;
|
||||
kvm_get_pal_call_data(vcpu, &gr28, &gr29, &gr30, &gr31);
|
||||
|
||||
if (gr31 != 0)
|
||||
printk(KERN_ERR"vcpu:%p called cache_flush error!\n", vcpu);
|
||||
|
||||
/* Always call Host Pal in int=1 */
|
||||
gr30 &= ~PAL_CACHE_FLUSH_CHK_INTRS;
|
||||
args.cache_type = gr29;
|
||||
args.operation = gr30;
|
||||
smp_call_function(remote_pal_cache_flush,
|
||||
(void *)&args, 1);
|
||||
if (args.status != 0)
|
||||
printk(KERN_ERR"pal_cache_flush error!,"
|
||||
"status:0x%lx\n", args.status);
|
||||
/*
|
||||
* Call Host PAL cache flush
|
||||
* Clear psr.ic when call PAL_CACHE_FLUSH
|
||||
*/
|
||||
local_irq_save(psr);
|
||||
result.status = ia64_pal_cache_flush(gr29, gr30, &result.v1,
|
||||
&result.v0);
|
||||
local_irq_restore(psr);
|
||||
if (result.status != 0)
|
||||
printk(KERN_ERR"vcpu:%p crashed due to cache_flush err:%ld"
|
||||
"in1:%lx,in2:%lx\n",
|
||||
vcpu, result.status, gr29, gr30);
|
||||
|
||||
#if 0
|
||||
if (gr29 == PAL_CACHE_TYPE_COHERENT) {
|
||||
cpus_setall(vcpu->arch.cache_coherent_map);
|
||||
cpu_clear(vcpu->cpu, vcpu->arch.cache_coherent_map);
|
||||
cpus_setall(cpu_cache_coherent_map);
|
||||
cpu_clear(vcpu->cpu, cpu_cache_coherent_map);
|
||||
}
|
||||
#endif
|
||||
return result;
|
||||
}
|
||||
|
||||
struct ia64_pal_retval pal_cache_summary(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
|
||||
struct ia64_pal_retval result;
|
||||
|
||||
PAL_CALL(result, PAL_CACHE_SUMMARY, 0, 0, 0);
|
||||
return result;
|
||||
}
|
||||
|
||||
static struct ia64_pal_retval pal_freq_base(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
|
||||
struct ia64_pal_retval result;
|
||||
|
||||
PAL_CALL(result, PAL_FREQ_BASE, 0, 0, 0);
|
||||
|
||||
/*
|
||||
* PAL_FREQ_BASE may not be implemented in some platforms,
|
||||
* call SAL instead.
|
||||
*/
|
||||
if (result.v0 == 0) {
|
||||
result.status = ia64_sal_freq_base(SAL_FREQ_BASE_PLATFORM,
|
||||
&result.v0,
|
||||
&result.v1);
|
||||
result.v2 = 0;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
/*
|
||||
* On the SGI SN2, the ITC isn't stable. Emulation backed by the SN2
|
||||
* RTC is used instead. This function patches the ratios from SAL
|
||||
* to match the RTC before providing them to the guest.
|
||||
*/
|
||||
static void sn2_patch_itc_freq_ratios(struct ia64_pal_retval *result)
|
||||
{
|
||||
struct pal_freq_ratio *ratio;
|
||||
unsigned long sal_freq, sal_drift, factor;
|
||||
|
||||
result->status = ia64_sal_freq_base(SAL_FREQ_BASE_PLATFORM,
|
||||
&sal_freq, &sal_drift);
|
||||
ratio = (struct pal_freq_ratio *)&result->v2;
|
||||
factor = ((sal_freq * 3) + (sn_rtc_cycles_per_second / 2)) /
|
||||
sn_rtc_cycles_per_second;
|
||||
|
||||
ratio->num = 3;
|
||||
ratio->den = factor;
|
||||
}
|
||||
|
||||
static struct ia64_pal_retval pal_freq_ratios(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct ia64_pal_retval result;
|
||||
|
||||
PAL_CALL(result, PAL_FREQ_RATIOS, 0, 0, 0);
|
||||
|
||||
if (vcpu->kvm->arch.is_sn2)
|
||||
sn2_patch_itc_freq_ratios(&result);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static struct ia64_pal_retval pal_logical_to_physica(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct ia64_pal_retval result;
|
||||
|
||||
INIT_PAL_STATUS_UNIMPLEMENTED(result);
|
||||
return result;
|
||||
}
|
||||
|
||||
static struct ia64_pal_retval pal_platform_addr(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
|
||||
struct ia64_pal_retval result;
|
||||
|
||||
INIT_PAL_STATUS_SUCCESS(result);
|
||||
return result;
|
||||
}
|
||||
|
||||
static struct ia64_pal_retval pal_proc_get_features(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
|
||||
struct ia64_pal_retval result = {0, 0, 0, 0};
|
||||
long in0, in1, in2, in3;
|
||||
|
||||
kvm_get_pal_call_data(vcpu, &in0, &in1, &in2, &in3);
|
||||
result.status = ia64_pal_proc_get_features(&result.v0, &result.v1,
|
||||
&result.v2, in2);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static struct ia64_pal_retval pal_register_info(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
|
||||
struct ia64_pal_retval result = {0, 0, 0, 0};
|
||||
long in0, in1, in2, in3;
|
||||
|
||||
kvm_get_pal_call_data(vcpu, &in0, &in1, &in2, &in3);
|
||||
result.status = ia64_pal_register_info(in1, &result.v1, &result.v2);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static struct ia64_pal_retval pal_cache_info(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
|
||||
pal_cache_config_info_t ci;
|
||||
long status;
|
||||
unsigned long in0, in1, in2, in3, r9, r10;
|
||||
|
||||
kvm_get_pal_call_data(vcpu, &in0, &in1, &in2, &in3);
|
||||
status = ia64_pal_cache_config_info(in1, in2, &ci);
|
||||
r9 = ci.pcci_info_1.pcci1_data;
|
||||
r10 = ci.pcci_info_2.pcci2_data;
|
||||
return ((struct ia64_pal_retval){status, r9, r10, 0});
|
||||
}
|
||||
|
||||
#define GUEST_IMPL_VA_MSB 59
|
||||
#define GUEST_RID_BITS 18
|
||||
|
||||
static struct ia64_pal_retval pal_vm_summary(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
|
||||
pal_vm_info_1_u_t vminfo1;
|
||||
pal_vm_info_2_u_t vminfo2;
|
||||
struct ia64_pal_retval result;
|
||||
|
||||
PAL_CALL(result, PAL_VM_SUMMARY, 0, 0, 0);
|
||||
if (!result.status) {
|
||||
vminfo1.pvi1_val = result.v0;
|
||||
vminfo1.pal_vm_info_1_s.max_itr_entry = 8;
|
||||
vminfo1.pal_vm_info_1_s.max_dtr_entry = 8;
|
||||
result.v0 = vminfo1.pvi1_val;
|
||||
vminfo2.pal_vm_info_2_s.impl_va_msb = GUEST_IMPL_VA_MSB;
|
||||
vminfo2.pal_vm_info_2_s.rid_size = GUEST_RID_BITS;
|
||||
result.v1 = vminfo2.pvi2_val;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static struct ia64_pal_retval pal_vm_info(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct ia64_pal_retval result;
|
||||
unsigned long in0, in1, in2, in3;
|
||||
|
||||
kvm_get_pal_call_data(vcpu, &in0, &in1, &in2, &in3);
|
||||
|
||||
result.status = ia64_pal_vm_info(in1, in2,
|
||||
(pal_tc_info_u_t *)&result.v1, &result.v2);
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
static u64 kvm_get_pal_call_index(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
u64 index = 0;
|
||||
struct exit_ctl_data *p;
|
||||
|
||||
p = kvm_get_exit_data(vcpu);
|
||||
if (p->exit_reason == EXIT_REASON_PAL_CALL)
|
||||
index = p->u.pal_data.gr28;
|
||||
|
||||
return index;
|
||||
}
|
||||
|
||||
static void prepare_for_halt(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
vcpu->arch.timer_pending = 1;
|
||||
vcpu->arch.timer_fired = 0;
|
||||
}
|
||||
|
||||
static struct ia64_pal_retval pal_perf_mon_info(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
long status;
|
||||
unsigned long in0, in1, in2, in3, r9;
|
||||
unsigned long pm_buffer[16];
|
||||
|
||||
kvm_get_pal_call_data(vcpu, &in0, &in1, &in2, &in3);
|
||||
status = ia64_pal_perf_mon_info(pm_buffer,
|
||||
(pal_perf_mon_info_u_t *) &r9);
|
||||
if (status != 0) {
|
||||
printk(KERN_DEBUG"PAL_PERF_MON_INFO fails ret=%ld\n", status);
|
||||
} else {
|
||||
if (in1)
|
||||
memcpy((void *)in1, pm_buffer, sizeof(pm_buffer));
|
||||
else {
|
||||
status = PAL_STATUS_EINVAL;
|
||||
printk(KERN_WARNING"Invalid parameters "
|
||||
"for PAL call:0x%lx!\n", in0);
|
||||
}
|
||||
}
|
||||
return (struct ia64_pal_retval){status, r9, 0, 0};
|
||||
}
|
||||
|
||||
static struct ia64_pal_retval pal_halt_info(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
unsigned long in0, in1, in2, in3;
|
||||
long status;
|
||||
unsigned long res = 1000UL | (1000UL << 16) | (10UL << 32)
|
||||
| (1UL << 61) | (1UL << 60);
|
||||
|
||||
kvm_get_pal_call_data(vcpu, &in0, &in1, &in2, &in3);
|
||||
if (in1) {
|
||||
memcpy((void *)in1, &res, sizeof(res));
|
||||
status = 0;
|
||||
} else{
|
||||
status = PAL_STATUS_EINVAL;
|
||||
printk(KERN_WARNING"Invalid parameters "
|
||||
"for PAL call:0x%lx!\n", in0);
|
||||
}
|
||||
|
||||
return (struct ia64_pal_retval){status, 0, 0, 0};
|
||||
}
|
||||
|
||||
static struct ia64_pal_retval pal_mem_attrib(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
unsigned long r9;
|
||||
long status;
|
||||
|
||||
status = ia64_pal_mem_attrib(&r9);
|
||||
|
||||
return (struct ia64_pal_retval){status, r9, 0, 0};
|
||||
}
|
||||
|
||||
static void remote_pal_prefetch_visibility(void *v)
|
||||
{
|
||||
s64 trans_type = (s64)v;
|
||||
ia64_pal_prefetch_visibility(trans_type);
|
||||
}
|
||||
|
||||
static struct ia64_pal_retval pal_prefetch_visibility(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct ia64_pal_retval result = {0, 0, 0, 0};
|
||||
unsigned long in0, in1, in2, in3;
|
||||
kvm_get_pal_call_data(vcpu, &in0, &in1, &in2, &in3);
|
||||
result.status = ia64_pal_prefetch_visibility(in1);
|
||||
if (result.status == 0) {
|
||||
/* Must be performed on all remote processors
|
||||
in the coherence domain. */
|
||||
smp_call_function(remote_pal_prefetch_visibility,
|
||||
(void *)in1, 1);
|
||||
/* Unnecessary on remote processor for other vcpus!*/
|
||||
result.status = 1;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
static void remote_pal_mc_drain(void *v)
|
||||
{
|
||||
ia64_pal_mc_drain();
|
||||
}
|
||||
|
||||
static struct ia64_pal_retval pal_get_brand_info(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct ia64_pal_retval result = {0, 0, 0, 0};
|
||||
unsigned long in0, in1, in2, in3;
|
||||
|
||||
kvm_get_pal_call_data(vcpu, &in0, &in1, &in2, &in3);
|
||||
|
||||
if (in1 == 0 && in2) {
|
||||
char brand_info[128];
|
||||
result.status = ia64_pal_get_brand_info(brand_info);
|
||||
if (result.status == PAL_STATUS_SUCCESS)
|
||||
memcpy((void *)in2, brand_info, 128);
|
||||
} else {
|
||||
result.status = PAL_STATUS_REQUIRES_MEMORY;
|
||||
printk(KERN_WARNING"Invalid parameters for "
|
||||
"PAL call:0x%lx!\n", in0);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
int kvm_pal_emul(struct kvm_vcpu *vcpu, struct kvm_run *run)
|
||||
{
|
||||
|
||||
u64 gr28;
|
||||
struct ia64_pal_retval result;
|
||||
int ret = 1;
|
||||
|
||||
gr28 = kvm_get_pal_call_index(vcpu);
|
||||
switch (gr28) {
|
||||
case PAL_CACHE_FLUSH:
|
||||
result = pal_cache_flush(vcpu);
|
||||
break;
|
||||
case PAL_MEM_ATTRIB:
|
||||
result = pal_mem_attrib(vcpu);
|
||||
break;
|
||||
case PAL_CACHE_SUMMARY:
|
||||
result = pal_cache_summary(vcpu);
|
||||
break;
|
||||
case PAL_PERF_MON_INFO:
|
||||
result = pal_perf_mon_info(vcpu);
|
||||
break;
|
||||
case PAL_HALT_INFO:
|
||||
result = pal_halt_info(vcpu);
|
||||
break;
|
||||
case PAL_HALT_LIGHT:
|
||||
{
|
||||
INIT_PAL_STATUS_SUCCESS(result);
|
||||
prepare_for_halt(vcpu);
|
||||
if (kvm_highest_pending_irq(vcpu) == -1)
|
||||
ret = kvm_emulate_halt(vcpu);
|
||||
}
|
||||
break;
|
||||
|
||||
case PAL_PREFETCH_VISIBILITY:
|
||||
result = pal_prefetch_visibility(vcpu);
|
||||
break;
|
||||
case PAL_MC_DRAIN:
|
||||
result.status = ia64_pal_mc_drain();
|
||||
/* FIXME: All vcpus likely call PAL_MC_DRAIN.
|
||||
That causes the congestion. */
|
||||
smp_call_function(remote_pal_mc_drain, NULL, 1);
|
||||
break;
|
||||
|
||||
case PAL_FREQ_RATIOS:
|
||||
result = pal_freq_ratios(vcpu);
|
||||
break;
|
||||
|
||||
case PAL_FREQ_BASE:
|
||||
result = pal_freq_base(vcpu);
|
||||
break;
|
||||
|
||||
case PAL_LOGICAL_TO_PHYSICAL :
|
||||
result = pal_logical_to_physica(vcpu);
|
||||
break;
|
||||
|
||||
case PAL_VM_SUMMARY :
|
||||
result = pal_vm_summary(vcpu);
|
||||
break;
|
||||
|
||||
case PAL_VM_INFO :
|
||||
result = pal_vm_info(vcpu);
|
||||
break;
|
||||
case PAL_PLATFORM_ADDR :
|
||||
result = pal_platform_addr(vcpu);
|
||||
break;
|
||||
case PAL_CACHE_INFO:
|
||||
result = pal_cache_info(vcpu);
|
||||
break;
|
||||
case PAL_PTCE_INFO:
|
||||
INIT_PAL_STATUS_SUCCESS(result);
|
||||
result.v1 = (1L << 32) | 1L;
|
||||
break;
|
||||
case PAL_REGISTER_INFO:
|
||||
result = pal_register_info(vcpu);
|
||||
break;
|
||||
case PAL_VM_PAGE_SIZE:
|
||||
result.status = ia64_pal_vm_page_size(&result.v0,
|
||||
&result.v1);
|
||||
break;
|
||||
case PAL_RSE_INFO:
|
||||
result.status = ia64_pal_rse_info(&result.v0,
|
||||
(pal_hints_u_t *)&result.v1);
|
||||
break;
|
||||
case PAL_PROC_GET_FEATURES:
|
||||
result = pal_proc_get_features(vcpu);
|
||||
break;
|
||||
case PAL_DEBUG_INFO:
|
||||
result.status = ia64_pal_debug_info(&result.v0,
|
||||
&result.v1);
|
||||
break;
|
||||
case PAL_VERSION:
|
||||
result.status = ia64_pal_version(
|
||||
(pal_version_u_t *)&result.v0,
|
||||
(pal_version_u_t *)&result.v1);
|
||||
break;
|
||||
case PAL_FIXED_ADDR:
|
||||
result.status = PAL_STATUS_SUCCESS;
|
||||
result.v0 = vcpu->vcpu_id;
|
||||
break;
|
||||
case PAL_BRAND_INFO:
|
||||
result = pal_get_brand_info(vcpu);
|
||||
break;
|
||||
case PAL_GET_PSTATE:
|
||||
case PAL_CACHE_SHARED_INFO:
|
||||
INIT_PAL_STATUS_UNIMPLEMENTED(result);
|
||||
break;
|
||||
default:
|
||||
INIT_PAL_STATUS_UNIMPLEMENTED(result);
|
||||
printk(KERN_WARNING"kvm: Unsupported pal call,"
|
||||
" index:0x%lx\n", gr28);
|
||||
}
|
||||
set_pal_result(vcpu, result);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct sal_ret_values sal_emulator(struct kvm *kvm,
|
||||
long index, unsigned long in1,
|
||||
unsigned long in2, unsigned long in3,
|
||||
unsigned long in4, unsigned long in5,
|
||||
unsigned long in6, unsigned long in7)
|
||||
{
|
||||
unsigned long r9 = 0;
|
||||
unsigned long r10 = 0;
|
||||
long r11 = 0;
|
||||
long status;
|
||||
|
||||
status = 0;
|
||||
switch (index) {
|
||||
case SAL_FREQ_BASE:
|
||||
status = ia64_sal_freq_base(in1, &r9, &r10);
|
||||
break;
|
||||
case SAL_PCI_CONFIG_READ:
|
||||
printk(KERN_WARNING"kvm: Not allowed to call here!"
|
||||
" SAL_PCI_CONFIG_READ\n");
|
||||
break;
|
||||
case SAL_PCI_CONFIG_WRITE:
|
||||
printk(KERN_WARNING"kvm: Not allowed to call here!"
|
||||
" SAL_PCI_CONFIG_WRITE\n");
|
||||
break;
|
||||
case SAL_SET_VECTORS:
|
||||
if (in1 == SAL_VECTOR_OS_BOOT_RENDEZ) {
|
||||
if (in4 != 0 || in5 != 0 || in6 != 0 || in7 != 0) {
|
||||
status = -2;
|
||||
} else {
|
||||
kvm->arch.rdv_sal_data.boot_ip = in2;
|
||||
kvm->arch.rdv_sal_data.boot_gp = in3;
|
||||
}
|
||||
printk("Rendvous called! iip:%lx\n\n", in2);
|
||||
} else
|
||||
printk(KERN_WARNING"kvm: CALLED SAL_SET_VECTORS %lu."
|
||||
"ignored...\n", in1);
|
||||
break;
|
||||
case SAL_GET_STATE_INFO:
|
||||
/* No more info. */
|
||||
status = -5;
|
||||
r9 = 0;
|
||||
break;
|
||||
case SAL_GET_STATE_INFO_SIZE:
|
||||
/* Return a dummy size. */
|
||||
status = 0;
|
||||
r9 = 128;
|
||||
break;
|
||||
case SAL_CLEAR_STATE_INFO:
|
||||
/* Noop. */
|
||||
break;
|
||||
case SAL_MC_RENDEZ:
|
||||
printk(KERN_WARNING
|
||||
"kvm: called SAL_MC_RENDEZ. ignored...\n");
|
||||
break;
|
||||
case SAL_MC_SET_PARAMS:
|
||||
printk(KERN_WARNING
|
||||
"kvm: called SAL_MC_SET_PARAMS.ignored!\n");
|
||||
break;
|
||||
case SAL_CACHE_FLUSH:
|
||||
if (1) {
|
||||
/*Flush using SAL.
|
||||
This method is faster but has a side
|
||||
effect on other vcpu running on
|
||||
this cpu. */
|
||||
status = ia64_sal_cache_flush(in1);
|
||||
} else {
|
||||
/*Maybe need to implement the method
|
||||
without side effect!*/
|
||||
status = 0;
|
||||
}
|
||||
break;
|
||||
case SAL_CACHE_INIT:
|
||||
printk(KERN_WARNING
|
||||
"kvm: called SAL_CACHE_INIT. ignored...\n");
|
||||
break;
|
||||
case SAL_UPDATE_PAL:
|
||||
printk(KERN_WARNING
|
||||
"kvm: CALLED SAL_UPDATE_PAL. ignored...\n");
|
||||
break;
|
||||
default:
|
||||
printk(KERN_WARNING"kvm: called SAL_CALL with unknown index."
|
||||
" index:%ld\n", index);
|
||||
status = -1;
|
||||
break;
|
||||
}
|
||||
return ((struct sal_ret_values) {status, r9, r10, r11});
|
||||
}
|
||||
|
||||
static void kvm_get_sal_call_data(struct kvm_vcpu *vcpu, u64 *in0, u64 *in1,
|
||||
u64 *in2, u64 *in3, u64 *in4, u64 *in5, u64 *in6, u64 *in7){
|
||||
|
||||
struct exit_ctl_data *p;
|
||||
|
||||
p = kvm_get_exit_data(vcpu);
|
||||
|
||||
if (p->exit_reason == EXIT_REASON_SAL_CALL) {
|
||||
*in0 = p->u.sal_data.in0;
|
||||
*in1 = p->u.sal_data.in1;
|
||||
*in2 = p->u.sal_data.in2;
|
||||
*in3 = p->u.sal_data.in3;
|
||||
*in4 = p->u.sal_data.in4;
|
||||
*in5 = p->u.sal_data.in5;
|
||||
*in6 = p->u.sal_data.in6;
|
||||
*in7 = p->u.sal_data.in7;
|
||||
return ;
|
||||
}
|
||||
*in0 = 0;
|
||||
}
|
||||
|
||||
void kvm_sal_emul(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
|
||||
struct sal_ret_values result;
|
||||
u64 index, in1, in2, in3, in4, in5, in6, in7;
|
||||
|
||||
kvm_get_sal_call_data(vcpu, &index, &in1, &in2,
|
||||
&in3, &in4, &in5, &in6, &in7);
|
||||
result = sal_emulator(vcpu->kvm, index, in1, in2, in3,
|
||||
in4, in5, in6, in7);
|
||||
set_sal_result(vcpu, result);
|
||||
}
|
|
@ -1,21 +0,0 @@
|
|||
/*
|
||||
* kvm_lib.c: Compile some libraries for kvm-intel module.
|
||||
*
|
||||
* Just include kernel's library, and disable symbols export.
|
||||
* Copyright (C) 2008, Intel Corporation.
|
||||
* Xiantao Zhang (xiantao.zhang@intel.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
#undef CONFIG_MODULES
|
||||
#include <linux/module.h>
|
||||
#undef CONFIG_KALLSYMS
|
||||
#undef EXPORT_SYMBOL
|
||||
#undef EXPORT_SYMBOL_GPL
|
||||
#define EXPORT_SYMBOL(sym)
|
||||
#define EXPORT_SYMBOL_GPL(sym)
|
||||
#include "../../../lib/vsprintf.c"
|
||||
#include "../../../lib/ctype.c"
|
|
@ -1,266 +0,0 @@
|
|||
/*
|
||||
* kvm_minstate.h: min save macros
|
||||
* Copyright (c) 2007, Intel Corporation.
|
||||
*
|
||||
* Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
|
||||
* Xiantao Zhang (xiantao.zhang@intel.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#include <asm/asmmacro.h>
|
||||
#include <asm/types.h>
|
||||
#include <asm/kregs.h>
|
||||
#include <asm/kvm_host.h>
|
||||
|
||||
#include "asm-offsets.h"
|
||||
|
||||
#define KVM_MINSTATE_START_SAVE_MIN \
|
||||
mov ar.rsc = 0;/* set enforced lazy mode, pl 0, little-endian, loadrs=0 */\
|
||||
;; \
|
||||
mov.m r28 = ar.rnat; \
|
||||
addl r22 = VMM_RBS_OFFSET,r1; /* compute base of RBS */ \
|
||||
;; \
|
||||
lfetch.fault.excl.nt1 [r22]; \
|
||||
addl r1 = KVM_STK_OFFSET-VMM_PT_REGS_SIZE, r1; \
|
||||
mov r23 = ar.bspstore; /* save ar.bspstore */ \
|
||||
;; \
|
||||
mov ar.bspstore = r22; /* switch to kernel RBS */\
|
||||
;; \
|
||||
mov r18 = ar.bsp; \
|
||||
mov ar.rsc = 0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */
|
||||
|
||||
|
||||
|
||||
#define KVM_MINSTATE_END_SAVE_MIN \
|
||||
bsw.1; /* switch back to bank 1 (must be last in insn group) */\
|
||||
;;
|
||||
|
||||
|
||||
#define PAL_VSA_SYNC_READ \
|
||||
/* begin to call pal vps sync_read */ \
|
||||
{.mii; \
|
||||
add r25 = VMM_VPD_BASE_OFFSET, r21; \
|
||||
nop 0x0; \
|
||||
mov r24=ip; \
|
||||
;; \
|
||||
} \
|
||||
{.mmb \
|
||||
add r24=0x20, r24; \
|
||||
ld8 r25 = [r25]; /* read vpd base */ \
|
||||
br.cond.sptk kvm_vps_sync_read; /*call the service*/ \
|
||||
;; \
|
||||
}; \
|
||||
|
||||
|
||||
#define KVM_MINSTATE_GET_CURRENT(reg) mov reg=r21
|
||||
|
||||
/*
|
||||
* KVM_DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
|
||||
* the minimum state necessary that allows us to turn psr.ic back
|
||||
* on.
|
||||
*
|
||||
* Assumed state upon entry:
|
||||
* psr.ic: off
|
||||
* r31: contains saved predicates (pr)
|
||||
*
|
||||
* Upon exit, the state is as follows:
|
||||
* psr.ic: off
|
||||
* r2 = points to &pt_regs.r16
|
||||
* r8 = contents of ar.ccv
|
||||
* r9 = contents of ar.csd
|
||||
* r10 = contents of ar.ssd
|
||||
* r11 = FPSR_DEFAULT
|
||||
* r12 = kernel sp (kernel virtual address)
|
||||
* r13 = points to current task_struct (kernel virtual address)
|
||||
* p15 = TRUE if psr.i is set in cr.ipsr
|
||||
* predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
|
||||
* preserved
|
||||
*
|
||||
* Note that psr.ic is NOT turned on by this macro. This is so that
|
||||
* we can pass interruption state as arguments to a handler.
|
||||
*/
|
||||
|
||||
|
||||
#define PT(f) (VMM_PT_REGS_##f##_OFFSET)
|
||||
|
||||
#define KVM_DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \
|
||||
KVM_MINSTATE_GET_CURRENT(r16); /* M (or M;;I) */ \
|
||||
mov r27 = ar.rsc; /* M */ \
|
||||
mov r20 = r1; /* A */ \
|
||||
mov r25 = ar.unat; /* M */ \
|
||||
mov r29 = cr.ipsr; /* M */ \
|
||||
mov r26 = ar.pfs; /* I */ \
|
||||
mov r18 = cr.isr; \
|
||||
COVER; /* B;; (or nothing) */ \
|
||||
;; \
|
||||
tbit.z p0,p15 = r29,IA64_PSR_I_BIT; \
|
||||
mov r1 = r16; \
|
||||
/* mov r21=r16; */ \
|
||||
/* switch from user to kernel RBS: */ \
|
||||
;; \
|
||||
invala; /* M */ \
|
||||
SAVE_IFS; \
|
||||
;; \
|
||||
KVM_MINSTATE_START_SAVE_MIN \
|
||||
adds r17 = 2*L1_CACHE_BYTES,r1;/* cache-line size */ \
|
||||
adds r16 = PT(CR_IPSR),r1; \
|
||||
;; \
|
||||
lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \
|
||||
st8 [r16] = r29; /* save cr.ipsr */ \
|
||||
;; \
|
||||
lfetch.fault.excl.nt1 [r17]; \
|
||||
tbit.nz p15,p0 = r29,IA64_PSR_I_BIT; \
|
||||
mov r29 = b0 \
|
||||
;; \
|
||||
adds r16 = PT(R8),r1; /* initialize first base pointer */\
|
||||
adds r17 = PT(R9),r1; /* initialize second base pointer */\
|
||||
;; \
|
||||
.mem.offset 0,0; st8.spill [r16] = r8,16; \
|
||||
.mem.offset 8,0; st8.spill [r17] = r9,16; \
|
||||
;; \
|
||||
.mem.offset 0,0; st8.spill [r16] = r10,24; \
|
||||
.mem.offset 8,0; st8.spill [r17] = r11,24; \
|
||||
;; \
|
||||
mov r9 = cr.iip; /* M */ \
|
||||
mov r10 = ar.fpsr; /* M */ \
|
||||
;; \
|
||||
st8 [r16] = r9,16; /* save cr.iip */ \
|
||||
st8 [r17] = r30,16; /* save cr.ifs */ \
|
||||
sub r18 = r18,r22; /* r18=RSE.ndirty*8 */ \
|
||||
;; \
|
||||
st8 [r16] = r25,16; /* save ar.unat */ \
|
||||
st8 [r17] = r26,16; /* save ar.pfs */ \
|
||||
shl r18 = r18,16; /* calu ar.rsc used for "loadrs" */\
|
||||
;; \
|
||||
st8 [r16] = r27,16; /* save ar.rsc */ \
|
||||
st8 [r17] = r28,16; /* save ar.rnat */ \
|
||||
;; /* avoid RAW on r16 & r17 */ \
|
||||
st8 [r16] = r23,16; /* save ar.bspstore */ \
|
||||
st8 [r17] = r31,16; /* save predicates */ \
|
||||
;; \
|
||||
st8 [r16] = r29,16; /* save b0 */ \
|
||||
st8 [r17] = r18,16; /* save ar.rsc value for "loadrs" */\
|
||||
;; \
|
||||
.mem.offset 0,0; st8.spill [r16] = r20,16;/* save original r1 */ \
|
||||
.mem.offset 8,0; st8.spill [r17] = r12,16; \
|
||||
adds r12 = -16,r1; /* switch to kernel memory stack */ \
|
||||
;; \
|
||||
.mem.offset 0,0; st8.spill [r16] = r13,16; \
|
||||
.mem.offset 8,0; st8.spill [r17] = r10,16; /* save ar.fpsr */\
|
||||
mov r13 = r21; /* establish `current' */ \
|
||||
;; \
|
||||
.mem.offset 0,0; st8.spill [r16] = r15,16; \
|
||||
.mem.offset 8,0; st8.spill [r17] = r14,16; \
|
||||
;; \
|
||||
.mem.offset 0,0; st8.spill [r16] = r2,16; \
|
||||
.mem.offset 8,0; st8.spill [r17] = r3,16; \
|
||||
adds r2 = VMM_PT_REGS_R16_OFFSET,r1; \
|
||||
;; \
|
||||
adds r16 = VMM_VCPU_IIPA_OFFSET,r13; \
|
||||
adds r17 = VMM_VCPU_ISR_OFFSET,r13; \
|
||||
mov r26 = cr.iipa; \
|
||||
mov r27 = cr.isr; \
|
||||
;; \
|
||||
st8 [r16] = r26; \
|
||||
st8 [r17] = r27; \
|
||||
;; \
|
||||
EXTRA; \
|
||||
mov r8 = ar.ccv; \
|
||||
mov r9 = ar.csd; \
|
||||
mov r10 = ar.ssd; \
|
||||
movl r11 = FPSR_DEFAULT; /* L-unit */ \
|
||||
adds r17 = VMM_VCPU_GP_OFFSET,r13; \
|
||||
;; \
|
||||
ld8 r1 = [r17];/* establish kernel global pointer */ \
|
||||
;; \
|
||||
PAL_VSA_SYNC_READ \
|
||||
KVM_MINSTATE_END_SAVE_MIN
|
||||
|
||||
/*
|
||||
* SAVE_REST saves the remainder of pt_regs (with psr.ic on).
|
||||
*
|
||||
* Assumed state upon entry:
|
||||
* psr.ic: on
|
||||
* r2: points to &pt_regs.f6
|
||||
* r3: points to &pt_regs.f7
|
||||
* r8: contents of ar.ccv
|
||||
* r9: contents of ar.csd
|
||||
* r10: contents of ar.ssd
|
||||
* r11: FPSR_DEFAULT
|
||||
*
|
||||
* Registers r14 and r15 are guaranteed not to be touched by SAVE_REST.
|
||||
*/
|
||||
#define KVM_SAVE_REST \
|
||||
.mem.offset 0,0; st8.spill [r2] = r16,16; \
|
||||
.mem.offset 8,0; st8.spill [r3] = r17,16; \
|
||||
;; \
|
||||
.mem.offset 0,0; st8.spill [r2] = r18,16; \
|
||||
.mem.offset 8,0; st8.spill [r3] = r19,16; \
|
||||
;; \
|
||||
.mem.offset 0,0; st8.spill [r2] = r20,16; \
|
||||
.mem.offset 8,0; st8.spill [r3] = r21,16; \
|
||||
mov r18=b6; \
|
||||
;; \
|
||||
.mem.offset 0,0; st8.spill [r2] = r22,16; \
|
||||
.mem.offset 8,0; st8.spill [r3] = r23,16; \
|
||||
mov r19 = b7; \
|
||||
;; \
|
||||
.mem.offset 0,0; st8.spill [r2] = r24,16; \
|
||||
.mem.offset 8,0; st8.spill [r3] = r25,16; \
|
||||
;; \
|
||||
.mem.offset 0,0; st8.spill [r2] = r26,16; \
|
||||
.mem.offset 8,0; st8.spill [r3] = r27,16; \
|
||||
;; \
|
||||
.mem.offset 0,0; st8.spill [r2] = r28,16; \
|
||||
.mem.offset 8,0; st8.spill [r3] = r29,16; \
|
||||
;; \
|
||||
.mem.offset 0,0; st8.spill [r2] = r30,16; \
|
||||
.mem.offset 8,0; st8.spill [r3] = r31,32; \
|
||||
;; \
|
||||
mov ar.fpsr = r11; \
|
||||
st8 [r2] = r8,8; \
|
||||
adds r24 = PT(B6)-PT(F7),r3; \
|
||||
adds r25 = PT(B7)-PT(F7),r3; \
|
||||
;; \
|
||||
st8 [r24] = r18,16; /* b6 */ \
|
||||
st8 [r25] = r19,16; /* b7 */ \
|
||||
adds r2 = PT(R4)-PT(F6),r2; \
|
||||
adds r3 = PT(R5)-PT(F7),r3; \
|
||||
;; \
|
||||
st8 [r24] = r9; /* ar.csd */ \
|
||||
st8 [r25] = r10; /* ar.ssd */ \
|
||||
;; \
|
||||
mov r18 = ar.unat; \
|
||||
adds r19 = PT(EML_UNAT)-PT(R4),r2; \
|
||||
;; \
|
||||
st8 [r19] = r18; /* eml_unat */ \
|
||||
|
||||
|
||||
#define KVM_SAVE_EXTRA \
|
||||
.mem.offset 0,0; st8.spill [r2] = r4,16; \
|
||||
.mem.offset 8,0; st8.spill [r3] = r5,16; \
|
||||
;; \
|
||||
.mem.offset 0,0; st8.spill [r2] = r6,16; \
|
||||
.mem.offset 8,0; st8.spill [r3] = r7; \
|
||||
;; \
|
||||
mov r26 = ar.unat; \
|
||||
;; \
|
||||
st8 [r2] = r26;/* eml_unat */ \
|
||||
|
||||
#define KVM_SAVE_MIN_WITH_COVER KVM_DO_SAVE_MIN(cover, mov r30 = cr.ifs,)
|
||||
#define KVM_SAVE_MIN_WITH_COVER_R19 KVM_DO_SAVE_MIN(cover, mov r30 = cr.ifs, mov r15 = r19)
|
||||
#define KVM_SAVE_MIN KVM_DO_SAVE_MIN( , mov r30 = r0, )
|
|
@ -1,30 +0,0 @@
|
|||
#ifndef __KVM_IA64_LAPIC_H
|
||||
#define __KVM_IA64_LAPIC_H
|
||||
|
||||
#include <linux/kvm_host.h>
|
||||
|
||||
/*
|
||||
* vlsapic
|
||||
*/
|
||||
struct kvm_lapic{
|
||||
struct kvm_vcpu *vcpu;
|
||||
uint64_t insvc[4];
|
||||
uint64_t vhpi;
|
||||
uint8_t xtp;
|
||||
uint8_t pal_init_pending;
|
||||
uint8_t pad[2];
|
||||
};
|
||||
|
||||
int kvm_create_lapic(struct kvm_vcpu *vcpu);
|
||||
void kvm_free_lapic(struct kvm_vcpu *vcpu);
|
||||
|
||||
int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
|
||||
int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
|
||||
int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
|
||||
int short_hand, int dest, int dest_mode);
|
||||
int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2);
|
||||
int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq);
|
||||
#define kvm_apic_present(x) (true)
|
||||
#define kvm_lapic_enabled(x) (true)
|
||||
|
||||
#endif
|
|
@ -1 +0,0 @@
|
|||
#include "../lib/memcpy.S"
|
|
@ -1 +0,0 @@
|
|||
#include "../lib/memset.S"
|
|
@ -1,94 +0,0 @@
|
|||
#ifndef __KVM_IA64_MISC_H
|
||||
#define __KVM_IA64_MISC_H
|
||||
|
||||
#include <linux/kvm_host.h>
|
||||
/*
|
||||
* misc.h
|
||||
* Copyright (C) 2007, Intel Corporation.
|
||||
* Xiantao Zhang (xiantao.zhang@intel.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
*Return p2m base address at host side!
|
||||
*/
|
||||
static inline uint64_t *kvm_host_get_pmt(struct kvm *kvm)
|
||||
{
|
||||
return (uint64_t *)(kvm->arch.vm_base +
|
||||
offsetof(struct kvm_vm_data, kvm_p2m));
|
||||
}
|
||||
|
||||
static inline void kvm_set_pmt_entry(struct kvm *kvm, gfn_t gfn,
|
||||
u64 paddr, u64 mem_flags)
|
||||
{
|
||||
uint64_t *pmt_base = kvm_host_get_pmt(kvm);
|
||||
unsigned long pte;
|
||||
|
||||
pte = PAGE_ALIGN(paddr) | mem_flags;
|
||||
pmt_base[gfn] = pte;
|
||||
}
|
||||
|
||||
/*Function for translating host address to guest address*/
|
||||
|
||||
static inline void *to_guest(struct kvm *kvm, void *addr)
|
||||
{
|
||||
return (void *)((unsigned long)(addr) - kvm->arch.vm_base +
|
||||
KVM_VM_DATA_BASE);
|
||||
}
|
||||
|
||||
/*Function for translating guest address to host address*/
|
||||
|
||||
static inline void *to_host(struct kvm *kvm, void *addr)
|
||||
{
|
||||
return (void *)((unsigned long)addr - KVM_VM_DATA_BASE
|
||||
+ kvm->arch.vm_base);
|
||||
}
|
||||
|
||||
/* Get host context of the vcpu */
|
||||
static inline union context *kvm_get_host_context(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
union context *ctx = &vcpu->arch.host;
|
||||
return to_guest(vcpu->kvm, ctx);
|
||||
}
|
||||
|
||||
/* Get guest context of the vcpu */
|
||||
static inline union context *kvm_get_guest_context(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
union context *ctx = &vcpu->arch.guest;
|
||||
return to_guest(vcpu->kvm, ctx);
|
||||
}
|
||||
|
||||
/* kvm get exit data from gvmm! */
|
||||
static inline struct exit_ctl_data *kvm_get_exit_data(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return &vcpu->arch.exit_data;
|
||||
}
|
||||
|
||||
/*kvm get vcpu ioreq for kvm module!*/
|
||||
static inline struct kvm_mmio_req *kvm_get_vcpu_ioreq(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct exit_ctl_data *p_ctl_data;
|
||||
|
||||
if (vcpu) {
|
||||
p_ctl_data = kvm_get_exit_data(vcpu);
|
||||
if (p_ctl_data->exit_reason == EXIT_REASON_MMIO_INSTRUCTION)
|
||||
return &p_ctl_data->u.ioreq;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#endif
|
|
@ -1,336 +0,0 @@
|
|||
/*
|
||||
* mmio.c: MMIO emulation components.
|
||||
* Copyright (c) 2004, Intel Corporation.
|
||||
* Yaozu Dong (Eddie Dong) (Eddie.dong@intel.com)
|
||||
* Kun Tian (Kevin Tian) (Kevin.tian@intel.com)
|
||||
*
|
||||
* Copyright (c) 2007 Intel Corporation KVM support.
|
||||
* Xuefei Xu (Anthony Xu) (anthony.xu@intel.com)
|
||||
* Xiantao Zhang (xiantao.zhang@intel.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kvm_host.h>
|
||||
|
||||
#include "vcpu.h"
|
||||
|
||||
static void vlsapic_write_xtp(struct kvm_vcpu *v, uint8_t val)
|
||||
{
|
||||
VLSAPIC_XTP(v) = val;
|
||||
}
|
||||
|
||||
/*
|
||||
* LSAPIC OFFSET
|
||||
*/
|
||||
#define PIB_LOW_HALF(ofst) !(ofst & (1 << 20))
|
||||
#define PIB_OFST_INTA 0x1E0000
|
||||
#define PIB_OFST_XTP 0x1E0008
|
||||
|
||||
/*
|
||||
* execute write IPI op.
|
||||
*/
|
||||
static void vlsapic_write_ipi(struct kvm_vcpu *vcpu,
|
||||
uint64_t addr, uint64_t data)
|
||||
{
|
||||
struct exit_ctl_data *p = ¤t_vcpu->arch.exit_data;
|
||||
unsigned long psr;
|
||||
|
||||
local_irq_save(psr);
|
||||
|
||||
p->exit_reason = EXIT_REASON_IPI;
|
||||
p->u.ipi_data.addr.val = addr;
|
||||
p->u.ipi_data.data.val = data;
|
||||
vmm_transition(current_vcpu);
|
||||
|
||||
local_irq_restore(psr);
|
||||
|
||||
}
|
||||
|
||||
void lsapic_write(struct kvm_vcpu *v, unsigned long addr,
|
||||
unsigned long length, unsigned long val)
|
||||
{
|
||||
addr &= (PIB_SIZE - 1);
|
||||
|
||||
switch (addr) {
|
||||
case PIB_OFST_INTA:
|
||||
panic_vm(v, "Undefined write on PIB INTA\n");
|
||||
break;
|
||||
case PIB_OFST_XTP:
|
||||
if (length == 1) {
|
||||
vlsapic_write_xtp(v, val);
|
||||
} else {
|
||||
panic_vm(v, "Undefined write on PIB XTP\n");
|
||||
}
|
||||
break;
|
||||
default:
|
||||
if (PIB_LOW_HALF(addr)) {
|
||||
/*Lower half */
|
||||
if (length != 8)
|
||||
panic_vm(v, "Can't LHF write with size %ld!\n",
|
||||
length);
|
||||
else
|
||||
vlsapic_write_ipi(v, addr, val);
|
||||
} else { /*Upper half */
|
||||
panic_vm(v, "IPI-UHF write %lx\n", addr);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
unsigned long lsapic_read(struct kvm_vcpu *v, unsigned long addr,
|
||||
unsigned long length)
|
||||
{
|
||||
uint64_t result = 0;
|
||||
|
||||
addr &= (PIB_SIZE - 1);
|
||||
|
||||
switch (addr) {
|
||||
case PIB_OFST_INTA:
|
||||
if (length == 1) /* 1 byte load */
|
||||
; /* There is no i8259, there is no INTA access*/
|
||||
else
|
||||
panic_vm(v, "Undefined read on PIB INTA\n");
|
||||
|
||||
break;
|
||||
case PIB_OFST_XTP:
|
||||
if (length == 1) {
|
||||
result = VLSAPIC_XTP(v);
|
||||
} else {
|
||||
panic_vm(v, "Undefined read on PIB XTP\n");
|
||||
}
|
||||
break;
|
||||
default:
|
||||
panic_vm(v, "Undefined addr access for lsapic!\n");
|
||||
break;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
static void mmio_access(struct kvm_vcpu *vcpu, u64 src_pa, u64 *dest,
|
||||
u16 s, int ma, int dir)
|
||||
{
|
||||
unsigned long iot;
|
||||
struct exit_ctl_data *p = &vcpu->arch.exit_data;
|
||||
unsigned long psr;
|
||||
|
||||
iot = __gpfn_is_io(src_pa >> PAGE_SHIFT);
|
||||
|
||||
local_irq_save(psr);
|
||||
|
||||
/*Intercept the access for PIB range*/
|
||||
if (iot == GPFN_PIB) {
|
||||
if (!dir)
|
||||
lsapic_write(vcpu, src_pa, s, *dest);
|
||||
else
|
||||
*dest = lsapic_read(vcpu, src_pa, s);
|
||||
goto out;
|
||||
}
|
||||
p->exit_reason = EXIT_REASON_MMIO_INSTRUCTION;
|
||||
p->u.ioreq.addr = src_pa;
|
||||
p->u.ioreq.size = s;
|
||||
p->u.ioreq.dir = dir;
|
||||
if (dir == IOREQ_WRITE)
|
||||
p->u.ioreq.data = *dest;
|
||||
p->u.ioreq.state = STATE_IOREQ_READY;
|
||||
vmm_transition(vcpu);
|
||||
|
||||
if (p->u.ioreq.state == STATE_IORESP_READY) {
|
||||
if (dir == IOREQ_READ)
|
||||
/* it's necessary to ensure zero extending */
|
||||
*dest = p->u.ioreq.data & (~0UL >> (64-(s*8)));
|
||||
} else
|
||||
panic_vm(vcpu, "Unhandled mmio access returned!\n");
|
||||
out:
|
||||
local_irq_restore(psr);
|
||||
return ;
|
||||
}
|
||||
|
||||
/*
|
||||
dir 1: read 0:write
|
||||
inst_type 0:integer 1:floating point
|
||||
*/
|
||||
#define SL_INTEGER 0 /* store/load interger*/
|
||||
#define SL_FLOATING 1 /* store/load floating*/
|
||||
|
||||
void emulate_io_inst(struct kvm_vcpu *vcpu, u64 padr, u64 ma)
|
||||
{
|
||||
struct kvm_pt_regs *regs;
|
||||
IA64_BUNDLE bundle;
|
||||
int slot, dir = 0;
|
||||
int inst_type = -1;
|
||||
u16 size = 0;
|
||||
u64 data, slot1a, slot1b, temp, update_reg;
|
||||
s32 imm;
|
||||
INST64 inst;
|
||||
|
||||
regs = vcpu_regs(vcpu);
|
||||
|
||||
if (fetch_code(vcpu, regs->cr_iip, &bundle)) {
|
||||
/* if fetch code fail, return and try again */
|
||||
return;
|
||||
}
|
||||
slot = ((struct ia64_psr *)&(regs->cr_ipsr))->ri;
|
||||
if (!slot)
|
||||
inst.inst = bundle.slot0;
|
||||
else if (slot == 1) {
|
||||
slot1a = bundle.slot1a;
|
||||
slot1b = bundle.slot1b;
|
||||
inst.inst = slot1a + (slot1b << 18);
|
||||
} else if (slot == 2)
|
||||
inst.inst = bundle.slot2;
|
||||
|
||||
/* Integer Load/Store */
|
||||
if (inst.M1.major == 4 && inst.M1.m == 0 && inst.M1.x == 0) {
|
||||
inst_type = SL_INTEGER;
|
||||
size = (inst.M1.x6 & 0x3);
|
||||
if ((inst.M1.x6 >> 2) > 0xb) {
|
||||
/*write*/
|
||||
dir = IOREQ_WRITE;
|
||||
data = vcpu_get_gr(vcpu, inst.M4.r2);
|
||||
} else if ((inst.M1.x6 >> 2) < 0xb) {
|
||||
/*read*/
|
||||
dir = IOREQ_READ;
|
||||
}
|
||||
} else if (inst.M2.major == 4 && inst.M2.m == 1 && inst.M2.x == 0) {
|
||||
/* Integer Load + Reg update */
|
||||
inst_type = SL_INTEGER;
|
||||
dir = IOREQ_READ;
|
||||
size = (inst.M2.x6 & 0x3);
|
||||
temp = vcpu_get_gr(vcpu, inst.M2.r3);
|
||||
update_reg = vcpu_get_gr(vcpu, inst.M2.r2);
|
||||
temp += update_reg;
|
||||
vcpu_set_gr(vcpu, inst.M2.r3, temp, 0);
|
||||
} else if (inst.M3.major == 5) {
|
||||
/*Integer Load/Store + Imm update*/
|
||||
inst_type = SL_INTEGER;
|
||||
size = (inst.M3.x6&0x3);
|
||||
if ((inst.M5.x6 >> 2) > 0xb) {
|
||||
/*write*/
|
||||
dir = IOREQ_WRITE;
|
||||
data = vcpu_get_gr(vcpu, inst.M5.r2);
|
||||
temp = vcpu_get_gr(vcpu, inst.M5.r3);
|
||||
imm = (inst.M5.s << 31) | (inst.M5.i << 30) |
|
||||
(inst.M5.imm7 << 23);
|
||||
temp += imm >> 23;
|
||||
vcpu_set_gr(vcpu, inst.M5.r3, temp, 0);
|
||||
|
||||
} else if ((inst.M3.x6 >> 2) < 0xb) {
|
||||
/*read*/
|
||||
dir = IOREQ_READ;
|
||||
temp = vcpu_get_gr(vcpu, inst.M3.r3);
|
||||
imm = (inst.M3.s << 31) | (inst.M3.i << 30) |
|
||||
(inst.M3.imm7 << 23);
|
||||
temp += imm >> 23;
|
||||
vcpu_set_gr(vcpu, inst.M3.r3, temp, 0);
|
||||
|
||||
}
|
||||
} else if (inst.M9.major == 6 && inst.M9.x6 == 0x3B
|
||||
&& inst.M9.m == 0 && inst.M9.x == 0) {
|
||||
/* Floating-point spill*/
|
||||
struct ia64_fpreg v;
|
||||
|
||||
inst_type = SL_FLOATING;
|
||||
dir = IOREQ_WRITE;
|
||||
vcpu_get_fpreg(vcpu, inst.M9.f2, &v);
|
||||
/* Write high word. FIXME: this is a kludge! */
|
||||
v.u.bits[1] &= 0x3ffff;
|
||||
mmio_access(vcpu, padr + 8, (u64 *)&v.u.bits[1], 8,
|
||||
ma, IOREQ_WRITE);
|
||||
data = v.u.bits[0];
|
||||
size = 3;
|
||||
} else if (inst.M10.major == 7 && inst.M10.x6 == 0x3B) {
|
||||
/* Floating-point spill + Imm update */
|
||||
struct ia64_fpreg v;
|
||||
|
||||
inst_type = SL_FLOATING;
|
||||
dir = IOREQ_WRITE;
|
||||
vcpu_get_fpreg(vcpu, inst.M10.f2, &v);
|
||||
temp = vcpu_get_gr(vcpu, inst.M10.r3);
|
||||
imm = (inst.M10.s << 31) | (inst.M10.i << 30) |
|
||||
(inst.M10.imm7 << 23);
|
||||
temp += imm >> 23;
|
||||
vcpu_set_gr(vcpu, inst.M10.r3, temp, 0);
|
||||
|
||||
/* Write high word.FIXME: this is a kludge! */
|
||||
v.u.bits[1] &= 0x3ffff;
|
||||
mmio_access(vcpu, padr + 8, (u64 *)&v.u.bits[1],
|
||||
8, ma, IOREQ_WRITE);
|
||||
data = v.u.bits[0];
|
||||
size = 3;
|
||||
} else if (inst.M10.major == 7 && inst.M10.x6 == 0x31) {
|
||||
/* Floating-point stf8 + Imm update */
|
||||
struct ia64_fpreg v;
|
||||
inst_type = SL_FLOATING;
|
||||
dir = IOREQ_WRITE;
|
||||
size = 3;
|
||||
vcpu_get_fpreg(vcpu, inst.M10.f2, &v);
|
||||
data = v.u.bits[0]; /* Significand. */
|
||||
temp = vcpu_get_gr(vcpu, inst.M10.r3);
|
||||
imm = (inst.M10.s << 31) | (inst.M10.i << 30) |
|
||||
(inst.M10.imm7 << 23);
|
||||
temp += imm >> 23;
|
||||
vcpu_set_gr(vcpu, inst.M10.r3, temp, 0);
|
||||
} else if (inst.M15.major == 7 && inst.M15.x6 >= 0x2c
|
||||
&& inst.M15.x6 <= 0x2f) {
|
||||
temp = vcpu_get_gr(vcpu, inst.M15.r3);
|
||||
imm = (inst.M15.s << 31) | (inst.M15.i << 30) |
|
||||
(inst.M15.imm7 << 23);
|
||||
temp += imm >> 23;
|
||||
vcpu_set_gr(vcpu, inst.M15.r3, temp, 0);
|
||||
|
||||
vcpu_increment_iip(vcpu);
|
||||
return;
|
||||
} else if (inst.M12.major == 6 && inst.M12.m == 1
|
||||
&& inst.M12.x == 1 && inst.M12.x6 == 1) {
|
||||
/* Floating-point Load Pair + Imm ldfp8 M12*/
|
||||
struct ia64_fpreg v;
|
||||
|
||||
inst_type = SL_FLOATING;
|
||||
dir = IOREQ_READ;
|
||||
size = 8; /*ldfd*/
|
||||
mmio_access(vcpu, padr, &data, size, ma, dir);
|
||||
v.u.bits[0] = data;
|
||||
v.u.bits[1] = 0x1003E;
|
||||
vcpu_set_fpreg(vcpu, inst.M12.f1, &v);
|
||||
padr += 8;
|
||||
mmio_access(vcpu, padr, &data, size, ma, dir);
|
||||
v.u.bits[0] = data;
|
||||
v.u.bits[1] = 0x1003E;
|
||||
vcpu_set_fpreg(vcpu, inst.M12.f2, &v);
|
||||
padr += 8;
|
||||
vcpu_set_gr(vcpu, inst.M12.r3, padr, 0);
|
||||
vcpu_increment_iip(vcpu);
|
||||
return;
|
||||
} else {
|
||||
inst_type = -1;
|
||||
panic_vm(vcpu, "Unsupported MMIO access instruction! "
|
||||
"Bunld[0]=0x%lx, Bundle[1]=0x%lx\n",
|
||||
bundle.i64[0], bundle.i64[1]);
|
||||
}
|
||||
|
||||
size = 1 << size;
|
||||
if (dir == IOREQ_WRITE) {
|
||||
mmio_access(vcpu, padr, &data, size, ma, dir);
|
||||
} else {
|
||||
mmio_access(vcpu, padr, &data, size, ma, dir);
|
||||
if (inst_type == SL_INTEGER)
|
||||
vcpu_set_gr(vcpu, inst.M1.r1, data, 0);
|
||||
else
|
||||
panic_vm(vcpu, "Unsupported instruction type!\n");
|
||||
|
||||
}
|
||||
vcpu_increment_iip(vcpu);
|
||||
}
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
2209
arch/ia64/kvm/vcpu.c
2209
arch/ia64/kvm/vcpu.c
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -1,752 +0,0 @@
|
|||
/*
|
||||
* vcpu.h: vcpu routines
|
||||
* Copyright (c) 2005, Intel Corporation.
|
||||
* Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
|
||||
* Yaozu Dong (Eddie Dong) (Eddie.dong@intel.com)
|
||||
*
|
||||
* Copyright (c) 2007, Intel Corporation.
|
||||
* Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
|
||||
* Xiantao Zhang (xiantao.zhang@intel.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
#ifndef __KVM_VCPU_H__
|
||||
#define __KVM_VCPU_H__
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/fpu.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include "vti.h"
|
||||
|
||||
#include <linux/kvm_host.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
typedef unsigned long IA64_INST;
|
||||
|
||||
typedef union U_IA64_BUNDLE {
|
||||
unsigned long i64[2];
|
||||
struct { unsigned long template:5, slot0:41, slot1a:18,
|
||||
slot1b:23, slot2:41; };
|
||||
/* NOTE: following doesn't work because bitfields can't cross natural
|
||||
size boundaries
|
||||
struct { unsigned long template:5, slot0:41, slot1:41, slot2:41; }; */
|
||||
} IA64_BUNDLE;
|
||||
|
||||
typedef union U_INST64_A5 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, r1:7, imm7b:7, r3:2, imm5c:5,
|
||||
imm9d:9, s:1, major:4; };
|
||||
} INST64_A5;
|
||||
|
||||
typedef union U_INST64_B4 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, btype:3, un3:3, p:1, b2:3, un11:11, x6:6,
|
||||
wh:2, d:1, un1:1, major:4; };
|
||||
} INST64_B4;
|
||||
|
||||
typedef union U_INST64_B8 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, un21:21, x6:6, un4:4, major:4; };
|
||||
} INST64_B8;
|
||||
|
||||
typedef union U_INST64_B9 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, imm20:20, :1, x6:6, :3, i:1, major:4; };
|
||||
} INST64_B9;
|
||||
|
||||
typedef union U_INST64_I19 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, imm20:20, :1, x6:6, x3:3, i:1, major:4; };
|
||||
} INST64_I19;
|
||||
|
||||
typedef union U_INST64_I26 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, :7, r2:7, ar3:7, x6:6, x3:3, :1, major:4; };
|
||||
} INST64_I26;
|
||||
|
||||
typedef union U_INST64_I27 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, :7, imm:7, ar3:7, x6:6, x3:3, s:1, major:4; };
|
||||
} INST64_I27;
|
||||
|
||||
typedef union U_INST64_I28 { /* not privileged (mov from AR) */
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, r1:7, :7, ar3:7, x6:6, x3:3, :1, major:4; };
|
||||
} INST64_I28;
|
||||
|
||||
typedef union U_INST64_M28 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, :14, r3:7, x6:6, x3:3, :1, major:4; };
|
||||
} INST64_M28;
|
||||
|
||||
typedef union U_INST64_M29 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, :7, r2:7, ar3:7, x6:6, x3:3, :1, major:4; };
|
||||
} INST64_M29;
|
||||
|
||||
typedef union U_INST64_M30 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, :7, imm:7, ar3:7, x4:4, x2:2,
|
||||
x3:3, s:1, major:4; };
|
||||
} INST64_M30;
|
||||
|
||||
typedef union U_INST64_M31 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, r1:7, :7, ar3:7, x6:6, x3:3, :1, major:4; };
|
||||
} INST64_M31;
|
||||
|
||||
typedef union U_INST64_M32 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, :7, r2:7, cr3:7, x6:6, x3:3, :1, major:4; };
|
||||
} INST64_M32;
|
||||
|
||||
typedef union U_INST64_M33 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, r1:7, :7, cr3:7, x6:6, x3:3, :1, major:4; };
|
||||
} INST64_M33;
|
||||
|
||||
typedef union U_INST64_M35 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, :7, r2:7, :7, x6:6, x3:3, :1, major:4; };
|
||||
|
||||
} INST64_M35;
|
||||
|
||||
typedef union U_INST64_M36 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, r1:7, :14, x6:6, x3:3, :1, major:4; };
|
||||
} INST64_M36;
|
||||
|
||||
typedef union U_INST64_M37 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, imm20a:20, :1, x4:4, x2:2, x3:3,
|
||||
i:1, major:4; };
|
||||
} INST64_M37;
|
||||
|
||||
typedef union U_INST64_M41 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, :7, r2:7, :7, x6:6, x3:3, :1, major:4; };
|
||||
} INST64_M41;
|
||||
|
||||
typedef union U_INST64_M42 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, :7, r2:7, r3:7, x6:6, x3:3, :1, major:4; };
|
||||
} INST64_M42;
|
||||
|
||||
typedef union U_INST64_M43 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, r1:7, :7, r3:7, x6:6, x3:3, :1, major:4; };
|
||||
} INST64_M43;
|
||||
|
||||
typedef union U_INST64_M44 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, imm:21, x4:4, i2:2, x3:3, i:1, major:4; };
|
||||
} INST64_M44;
|
||||
|
||||
typedef union U_INST64_M45 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, :7, r2:7, r3:7, x6:6, x3:3, :1, major:4; };
|
||||
} INST64_M45;
|
||||
|
||||
typedef union U_INST64_M46 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, r1:7, un7:7, r3:7, x6:6,
|
||||
x3:3, un1:1, major:4; };
|
||||
} INST64_M46;
|
||||
|
||||
typedef union U_INST64_M47 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, un14:14, r3:7, x6:6, x3:3, un1:1, major:4; };
|
||||
} INST64_M47;
|
||||
|
||||
typedef union U_INST64_M1{
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, r1:7, un7:7, r3:7, x:1, hint:2,
|
||||
x6:6, m:1, major:4; };
|
||||
} INST64_M1;
|
||||
|
||||
typedef union U_INST64_M2{
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, r1:7, r2:7, r3:7, x:1, hint:2,
|
||||
x6:6, m:1, major:4; };
|
||||
} INST64_M2;
|
||||
|
||||
typedef union U_INST64_M3{
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, r1:7, imm7:7, r3:7, i:1, hint:2,
|
||||
x6:6, s:1, major:4; };
|
||||
} INST64_M3;
|
||||
|
||||
typedef union U_INST64_M4 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, un7:7, r2:7, r3:7, x:1, hint:2,
|
||||
x6:6, m:1, major:4; };
|
||||
} INST64_M4;
|
||||
|
||||
typedef union U_INST64_M5 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, imm7:7, r2:7, r3:7, i:1, hint:2,
|
||||
x6:6, s:1, major:4; };
|
||||
} INST64_M5;
|
||||
|
||||
typedef union U_INST64_M6 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, f1:7, un7:7, r3:7, x:1, hint:2,
|
||||
x6:6, m:1, major:4; };
|
||||
} INST64_M6;
|
||||
|
||||
typedef union U_INST64_M9 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, :7, f2:7, r3:7, x:1, hint:2,
|
||||
x6:6, m:1, major:4; };
|
||||
} INST64_M9;
|
||||
|
||||
typedef union U_INST64_M10 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, imm7:7, f2:7, r3:7, i:1, hint:2,
|
||||
x6:6, s:1, major:4; };
|
||||
} INST64_M10;
|
||||
|
||||
typedef union U_INST64_M12 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, f1:7, f2:7, r3:7, x:1, hint:2,
|
||||
x6:6, m:1, major:4; };
|
||||
} INST64_M12;
|
||||
|
||||
typedef union U_INST64_M15 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long qp:6, :7, imm7:7, r3:7, i:1, hint:2,
|
||||
x6:6, s:1, major:4; };
|
||||
} INST64_M15;
|
||||
|
||||
typedef union U_INST64 {
|
||||
IA64_INST inst;
|
||||
struct { unsigned long :37, major:4; } generic;
|
||||
INST64_A5 A5; /* used in build_hypercall_bundle only */
|
||||
INST64_B4 B4; /* used in build_hypercall_bundle only */
|
||||
INST64_B8 B8; /* rfi, bsw.[01] */
|
||||
INST64_B9 B9; /* break.b */
|
||||
INST64_I19 I19; /* used in build_hypercall_bundle only */
|
||||
INST64_I26 I26; /* mov register to ar (I unit) */
|
||||
INST64_I27 I27; /* mov immediate to ar (I unit) */
|
||||
INST64_I28 I28; /* mov from ar (I unit) */
|
||||
INST64_M1 M1; /* ld integer */
|
||||
INST64_M2 M2;
|
||||
INST64_M3 M3;
|
||||
INST64_M4 M4; /* st integer */
|
||||
INST64_M5 M5;
|
||||
INST64_M6 M6; /* ldfd floating pointer */
|
||||
INST64_M9 M9; /* stfd floating pointer */
|
||||
INST64_M10 M10; /* stfd floating pointer */
|
||||
INST64_M12 M12; /* ldfd pair floating pointer */
|
||||
INST64_M15 M15; /* lfetch + imm update */
|
||||
INST64_M28 M28; /* purge translation cache entry */
|
||||
INST64_M29 M29; /* mov register to ar (M unit) */
|
||||
INST64_M30 M30; /* mov immediate to ar (M unit) */
|
||||
INST64_M31 M31; /* mov from ar (M unit) */
|
||||
INST64_M32 M32; /* mov reg to cr */
|
||||
INST64_M33 M33; /* mov from cr */
|
||||
INST64_M35 M35; /* mov to psr */
|
||||
INST64_M36 M36; /* mov from psr */
|
||||
INST64_M37 M37; /* break.m */
|
||||
INST64_M41 M41; /* translation cache insert */
|
||||
INST64_M42 M42; /* mov to indirect reg/translation reg insert*/
|
||||
INST64_M43 M43; /* mov from indirect reg */
|
||||
INST64_M44 M44; /* set/reset system mask */
|
||||
INST64_M45 M45; /* translation purge */
|
||||
INST64_M46 M46; /* translation access (tpa,tak) */
|
||||
INST64_M47 M47; /* purge translation entry */
|
||||
} INST64;
|
||||
|
||||
#define MASK_41 ((unsigned long)0x1ffffffffff)
|
||||
|
||||
/* Virtual address memory attributes encoding */
|
||||
#define VA_MATTR_WB 0x0
|
||||
#define VA_MATTR_UC 0x4
|
||||
#define VA_MATTR_UCE 0x5
|
||||
#define VA_MATTR_WC 0x6
|
||||
#define VA_MATTR_NATPAGE 0x7
|
||||
|
||||
#define PMASK(size) (~((size) - 1))
|
||||
#define PSIZE(size) (1UL<<(size))
|
||||
#define CLEARLSB(ppn, nbits) (((ppn) >> (nbits)) << (nbits))
|
||||
#define PAGEALIGN(va, ps) CLEARLSB(va, ps)
|
||||
#define PAGE_FLAGS_RV_MASK (0x2|(0x3UL<<50)|(((1UL<<11)-1)<<53))
|
||||
#define _PAGE_MA_ST (0x1 << 2) /* is reserved for software use */
|
||||
|
||||
#define ARCH_PAGE_SHIFT 12
|
||||
|
||||
#define INVALID_TI_TAG (1UL << 63)
|
||||
|
||||
#define VTLB_PTE_P_BIT 0
|
||||
#define VTLB_PTE_IO_BIT 60
|
||||
#define VTLB_PTE_IO (1UL<<VTLB_PTE_IO_BIT)
|
||||
#define VTLB_PTE_P (1UL<<VTLB_PTE_P_BIT)
|
||||
|
||||
#define vcpu_quick_region_check(_tr_regions,_ifa) \
|
||||
(_tr_regions & (1 << ((unsigned long)_ifa >> 61)))
|
||||
|
||||
#define vcpu_quick_region_set(_tr_regions,_ifa) \
|
||||
do {_tr_regions |= (1 << ((unsigned long)_ifa >> 61)); } while (0)
|
||||
|
||||
static inline void vcpu_set_tr(struct thash_data *trp, u64 pte, u64 itir,
|
||||
u64 va, u64 rid)
|
||||
{
|
||||
trp->page_flags = pte;
|
||||
trp->itir = itir;
|
||||
trp->vadr = va;
|
||||
trp->rid = rid;
|
||||
}
|
||||
|
||||
extern u64 kvm_get_mpt_entry(u64 gpfn);
|
||||
|
||||
/* Return I/ */
|
||||
static inline u64 __gpfn_is_io(u64 gpfn)
|
||||
{
|
||||
u64 pte;
|
||||
pte = kvm_get_mpt_entry(gpfn);
|
||||
if (!(pte & GPFN_INV_MASK)) {
|
||||
pte = pte & GPFN_IO_MASK;
|
||||
if (pte != GPFN_PHYS_MMIO)
|
||||
return pte;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#define IA64_NO_FAULT 0
|
||||
#define IA64_FAULT 1
|
||||
|
||||
#define VMM_RBS_OFFSET ((VMM_TASK_SIZE + 15) & ~15)
|
||||
|
||||
#define SW_BAD 0 /* Bad mode transitition */
|
||||
#define SW_V2P 1 /* Physical emulatino is activated */
|
||||
#define SW_P2V 2 /* Exit physical mode emulation */
|
||||
#define SW_SELF 3 /* No mode transition */
|
||||
#define SW_NOP 4 /* Mode transition, but without action required */
|
||||
|
||||
#define GUEST_IN_PHY 0x1
|
||||
#define GUEST_PHY_EMUL 0x2
|
||||
|
||||
#define current_vcpu ((struct kvm_vcpu *) ia64_getreg(_IA64_REG_TP))
|
||||
|
||||
#define VRN_SHIFT 61
|
||||
#define VRN_MASK 0xe000000000000000
|
||||
#define VRN0 0x0UL
|
||||
#define VRN1 0x1UL
|
||||
#define VRN2 0x2UL
|
||||
#define VRN3 0x3UL
|
||||
#define VRN4 0x4UL
|
||||
#define VRN5 0x5UL
|
||||
#define VRN6 0x6UL
|
||||
#define VRN7 0x7UL
|
||||
|
||||
#define IRQ_NO_MASKED 0
|
||||
#define IRQ_MASKED_BY_VTPR 1
|
||||
#define IRQ_MASKED_BY_INSVC 2 /* masked by inservice IRQ */
|
||||
|
||||
#define PTA_BASE_SHIFT 15
|
||||
|
||||
#define IA64_PSR_VM_BIT 46
|
||||
#define IA64_PSR_VM (__IA64_UL(1) << IA64_PSR_VM_BIT)
|
||||
|
||||
/* Interruption Function State */
|
||||
#define IA64_IFS_V_BIT 63
|
||||
#define IA64_IFS_V (__IA64_UL(1) << IA64_IFS_V_BIT)
|
||||
|
||||
#define PHY_PAGE_UC (_PAGE_A|_PAGE_D|_PAGE_P|_PAGE_MA_UC|_PAGE_AR_RWX)
|
||||
#define PHY_PAGE_WB (_PAGE_A|_PAGE_D|_PAGE_P|_PAGE_MA_WB|_PAGE_AR_RWX)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/gcc_intrin.h>
|
||||
|
||||
#define is_physical_mode(v) \
|
||||
((v->arch.mode_flags) & GUEST_IN_PHY)
|
||||
|
||||
#define is_virtual_mode(v) \
|
||||
(!is_physical_mode(v))
|
||||
|
||||
#define MODE_IND(psr) \
|
||||
(((psr).it << 2) + ((psr).dt << 1) + (psr).rt)
|
||||
|
||||
#ifndef CONFIG_SMP
|
||||
#define _vmm_raw_spin_lock(x) do {}while(0)
|
||||
#define _vmm_raw_spin_unlock(x) do {}while(0)
|
||||
#else
|
||||
typedef struct {
|
||||
volatile unsigned int lock;
|
||||
} vmm_spinlock_t;
|
||||
#define _vmm_raw_spin_lock(x) \
|
||||
do { \
|
||||
__u32 *ia64_spinlock_ptr = (__u32 *) (x); \
|
||||
__u64 ia64_spinlock_val; \
|
||||
ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0);\
|
||||
if (unlikely(ia64_spinlock_val)) { \
|
||||
do { \
|
||||
while (*ia64_spinlock_ptr) \
|
||||
ia64_barrier(); \
|
||||
ia64_spinlock_val = \
|
||||
ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0);\
|
||||
} while (ia64_spinlock_val); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define _vmm_raw_spin_unlock(x) \
|
||||
do { barrier(); \
|
||||
((vmm_spinlock_t *)x)->lock = 0; } \
|
||||
while (0)
|
||||
#endif
|
||||
|
||||
void vmm_spin_lock(vmm_spinlock_t *lock);
|
||||
void vmm_spin_unlock(vmm_spinlock_t *lock);
|
||||
enum {
|
||||
I_TLB = 1,
|
||||
D_TLB = 2
|
||||
};
|
||||
|
||||
union kvm_va {
|
||||
struct {
|
||||
unsigned long off : 60; /* intra-region offset */
|
||||
unsigned long reg : 4; /* region number */
|
||||
} f;
|
||||
unsigned long l;
|
||||
void *p;
|
||||
};
|
||||
|
||||
#define __kvm_pa(x) ({union kvm_va _v; _v.l = (long) (x); \
|
||||
_v.f.reg = 0; _v.l; })
|
||||
#define __kvm_va(x) ({union kvm_va _v; _v.l = (long) (x); \
|
||||
_v.f.reg = -1; _v.p; })
|
||||
|
||||
#define _REGION_ID(x) ({union ia64_rr _v; _v.val = (long)(x); \
|
||||
_v.rid; })
|
||||
#define _REGION_PAGE_SIZE(x) ({union ia64_rr _v; _v.val = (long)(x); \
|
||||
_v.ps; })
|
||||
#define _REGION_HW_WALKER(x) ({union ia64_rr _v; _v.val = (long)(x); \
|
||||
_v.ve; })
|
||||
|
||||
enum vhpt_ref{ DATA_REF, NA_REF, INST_REF, RSE_REF };
|
||||
enum tlb_miss_type { INSTRUCTION, DATA, REGISTER };
|
||||
|
||||
#define VCPU(_v, _x) ((_v)->arch.vpd->_x)
|
||||
#define VMX(_v, _x) ((_v)->arch._x)
|
||||
|
||||
#define VLSAPIC_INSVC(vcpu, i) ((vcpu)->arch.insvc[i])
|
||||
#define VLSAPIC_XTP(_v) VMX(_v, xtp)
|
||||
|
||||
static inline unsigned long itir_ps(unsigned long itir)
|
||||
{
|
||||
return ((itir >> 2) & 0x3f);
|
||||
}
|
||||
|
||||
|
||||
/**************************************************************************
|
||||
VCPU control register access routines
|
||||
**************************************************************************/
|
||||
|
||||
static inline u64 vcpu_get_itir(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return ((u64)VCPU(vcpu, itir));
|
||||
}
|
||||
|
||||
static inline void vcpu_set_itir(struct kvm_vcpu *vcpu, u64 val)
|
||||
{
|
||||
VCPU(vcpu, itir) = val;
|
||||
}
|
||||
|
||||
static inline u64 vcpu_get_ifa(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return ((u64)VCPU(vcpu, ifa));
|
||||
}
|
||||
|
||||
static inline void vcpu_set_ifa(struct kvm_vcpu *vcpu, u64 val)
|
||||
{
|
||||
VCPU(vcpu, ifa) = val;
|
||||
}
|
||||
|
||||
static inline u64 vcpu_get_iva(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return ((u64)VCPU(vcpu, iva));
|
||||
}
|
||||
|
||||
static inline u64 vcpu_get_pta(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return ((u64)VCPU(vcpu, pta));
|
||||
}
|
||||
|
||||
static inline u64 vcpu_get_lid(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return ((u64)VCPU(vcpu, lid));
|
||||
}
|
||||
|
||||
static inline u64 vcpu_get_tpr(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return ((u64)VCPU(vcpu, tpr));
|
||||
}
|
||||
|
||||
static inline u64 vcpu_get_eoi(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return (0UL); /*reads of eoi always return 0 */
|
||||
}
|
||||
|
||||
static inline u64 vcpu_get_irr0(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return ((u64)VCPU(vcpu, irr[0]));
|
||||
}
|
||||
|
||||
static inline u64 vcpu_get_irr1(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return ((u64)VCPU(vcpu, irr[1]));
|
||||
}
|
||||
|
||||
static inline u64 vcpu_get_irr2(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return ((u64)VCPU(vcpu, irr[2]));
|
||||
}
|
||||
|
||||
static inline u64 vcpu_get_irr3(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return ((u64)VCPU(vcpu, irr[3]));
|
||||
}
|
||||
|
||||
static inline void vcpu_set_dcr(struct kvm_vcpu *vcpu, u64 val)
|
||||
{
|
||||
ia64_setreg(_IA64_REG_CR_DCR, val);
|
||||
}
|
||||
|
||||
static inline void vcpu_set_isr(struct kvm_vcpu *vcpu, u64 val)
|
||||
{
|
||||
VCPU(vcpu, isr) = val;
|
||||
}
|
||||
|
||||
static inline void vcpu_set_lid(struct kvm_vcpu *vcpu, u64 val)
|
||||
{
|
||||
VCPU(vcpu, lid) = val;
|
||||
}
|
||||
|
||||
static inline void vcpu_set_ipsr(struct kvm_vcpu *vcpu, u64 val)
|
||||
{
|
||||
VCPU(vcpu, ipsr) = val;
|
||||
}
|
||||
|
||||
static inline void vcpu_set_iip(struct kvm_vcpu *vcpu, u64 val)
|
||||
{
|
||||
VCPU(vcpu, iip) = val;
|
||||
}
|
||||
|
||||
static inline void vcpu_set_ifs(struct kvm_vcpu *vcpu, u64 val)
|
||||
{
|
||||
VCPU(vcpu, ifs) = val;
|
||||
}
|
||||
|
||||
static inline void vcpu_set_iipa(struct kvm_vcpu *vcpu, u64 val)
|
||||
{
|
||||
VCPU(vcpu, iipa) = val;
|
||||
}
|
||||
|
||||
static inline void vcpu_set_iha(struct kvm_vcpu *vcpu, u64 val)
|
||||
{
|
||||
VCPU(vcpu, iha) = val;
|
||||
}
|
||||
|
||||
|
||||
static inline u64 vcpu_get_rr(struct kvm_vcpu *vcpu, u64 reg)
|
||||
{
|
||||
return vcpu->arch.vrr[reg>>61];
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
VCPU debug breakpoint register access routines
|
||||
**************************************************************************/
|
||||
|
||||
static inline void vcpu_set_dbr(struct kvm_vcpu *vcpu, u64 reg, u64 val)
|
||||
{
|
||||
__ia64_set_dbr(reg, val);
|
||||
}
|
||||
|
||||
static inline void vcpu_set_ibr(struct kvm_vcpu *vcpu, u64 reg, u64 val)
|
||||
{
|
||||
ia64_set_ibr(reg, val);
|
||||
}
|
||||
|
||||
static inline u64 vcpu_get_dbr(struct kvm_vcpu *vcpu, u64 reg)
|
||||
{
|
||||
return ((u64)__ia64_get_dbr(reg));
|
||||
}
|
||||
|
||||
static inline u64 vcpu_get_ibr(struct kvm_vcpu *vcpu, u64 reg)
|
||||
{
|
||||
return ((u64)ia64_get_ibr(reg));
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
VCPU performance monitor register access routines
|
||||
**************************************************************************/
|
||||
static inline void vcpu_set_pmc(struct kvm_vcpu *vcpu, u64 reg, u64 val)
|
||||
{
|
||||
/* NOTE: Writes to unimplemented PMC registers are discarded */
|
||||
ia64_set_pmc(reg, val);
|
||||
}
|
||||
|
||||
static inline void vcpu_set_pmd(struct kvm_vcpu *vcpu, u64 reg, u64 val)
|
||||
{
|
||||
/* NOTE: Writes to unimplemented PMD registers are discarded */
|
||||
ia64_set_pmd(reg, val);
|
||||
}
|
||||
|
||||
static inline u64 vcpu_get_pmc(struct kvm_vcpu *vcpu, u64 reg)
|
||||
{
|
||||
/* NOTE: Reads from unimplemented PMC registers return zero */
|
||||
return ((u64)ia64_get_pmc(reg));
|
||||
}
|
||||
|
||||
static inline u64 vcpu_get_pmd(struct kvm_vcpu *vcpu, u64 reg)
|
||||
{
|
||||
/* NOTE: Reads from unimplemented PMD registers return zero */
|
||||
return ((u64)ia64_get_pmd(reg));
|
||||
}
|
||||
|
||||
static inline unsigned long vrrtomrr(unsigned long val)
|
||||
{
|
||||
union ia64_rr rr;
|
||||
rr.val = val;
|
||||
rr.rid = (rr.rid << 4) | 0xe;
|
||||
if (rr.ps > PAGE_SHIFT)
|
||||
rr.ps = PAGE_SHIFT;
|
||||
rr.ve = 1;
|
||||
return rr.val;
|
||||
}
|
||||
|
||||
|
||||
static inline int highest_bits(int *dat)
|
||||
{
|
||||
u32 bits, bitnum;
|
||||
int i;
|
||||
|
||||
/* loop for all 256 bits */
|
||||
for (i = 7; i >= 0 ; i--) {
|
||||
bits = dat[i];
|
||||
if (bits) {
|
||||
bitnum = fls(bits);
|
||||
return i * 32 + bitnum - 1;
|
||||
}
|
||||
}
|
||||
return NULL_VECTOR;
|
||||
}
|
||||
|
||||
/*
|
||||
* The pending irq is higher than the inservice one.
|
||||
*
|
||||
*/
|
||||
static inline int is_higher_irq(int pending, int inservice)
|
||||
{
|
||||
return ((pending > inservice)
|
||||
|| ((pending != NULL_VECTOR)
|
||||
&& (inservice == NULL_VECTOR)));
|
||||
}
|
||||
|
||||
static inline int is_higher_class(int pending, int mic)
|
||||
{
|
||||
return ((pending >> 4) > mic);
|
||||
}
|
||||
|
||||
/*
|
||||
* Return 0-255 for pending irq.
|
||||
* NULL_VECTOR: when no pending.
|
||||
*/
|
||||
static inline int highest_pending_irq(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
if (VCPU(vcpu, irr[0]) & (1UL<<NMI_VECTOR))
|
||||
return NMI_VECTOR;
|
||||
if (VCPU(vcpu, irr[0]) & (1UL<<ExtINT_VECTOR))
|
||||
return ExtINT_VECTOR;
|
||||
|
||||
return highest_bits((int *)&VCPU(vcpu, irr[0]));
|
||||
}
|
||||
|
||||
static inline int highest_inservice_irq(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
if (VMX(vcpu, insvc[0]) & (1UL<<NMI_VECTOR))
|
||||
return NMI_VECTOR;
|
||||
if (VMX(vcpu, insvc[0]) & (1UL<<ExtINT_VECTOR))
|
||||
return ExtINT_VECTOR;
|
||||
|
||||
return highest_bits((int *)&(VMX(vcpu, insvc[0])));
|
||||
}
|
||||
|
||||
extern void vcpu_get_fpreg(struct kvm_vcpu *vcpu, unsigned long reg,
|
||||
struct ia64_fpreg *val);
|
||||
extern void vcpu_set_fpreg(struct kvm_vcpu *vcpu, unsigned long reg,
|
||||
struct ia64_fpreg *val);
|
||||
extern u64 vcpu_get_gr(struct kvm_vcpu *vcpu, unsigned long reg);
|
||||
extern void vcpu_set_gr(struct kvm_vcpu *vcpu, unsigned long reg,
|
||||
u64 val, int nat);
|
||||
extern unsigned long vcpu_get_psr(struct kvm_vcpu *vcpu);
|
||||
extern void vcpu_set_psr(struct kvm_vcpu *vcpu, unsigned long val);
|
||||
extern u64 vcpu_thash(struct kvm_vcpu *vcpu, u64 vadr);
|
||||
extern void vcpu_bsw0(struct kvm_vcpu *vcpu);
|
||||
extern void thash_vhpt_insert(struct kvm_vcpu *v, u64 pte,
|
||||
u64 itir, u64 va, int type);
|
||||
extern struct thash_data *vhpt_lookup(u64 va);
|
||||
extern u64 guest_vhpt_lookup(u64 iha, u64 *pte);
|
||||
extern void thash_purge_entries(struct kvm_vcpu *v, u64 va, u64 ps);
|
||||
extern void thash_purge_entries_remote(struct kvm_vcpu *v, u64 va, u64 ps);
|
||||
extern u64 translate_phy_pte(u64 *pte, u64 itir, u64 va);
|
||||
extern void thash_purge_and_insert(struct kvm_vcpu *v, u64 pte,
|
||||
u64 itir, u64 ifa, int type);
|
||||
extern void thash_purge_all(struct kvm_vcpu *v);
|
||||
extern struct thash_data *vtlb_lookup(struct kvm_vcpu *v,
|
||||
u64 va, int is_data);
|
||||
extern int vtr_find_overlap(struct kvm_vcpu *vcpu, u64 va,
|
||||
u64 ps, int is_data);
|
||||
|
||||
extern void vcpu_increment_iip(struct kvm_vcpu *v);
|
||||
extern void vcpu_decrement_iip(struct kvm_vcpu *vcpu);
|
||||
extern void vcpu_pend_interrupt(struct kvm_vcpu *vcpu, u8 vec);
|
||||
extern void vcpu_unpend_interrupt(struct kvm_vcpu *vcpu, u8 vec);
|
||||
extern void data_page_not_present(struct kvm_vcpu *vcpu, u64 vadr);
|
||||
extern void dnat_page_consumption(struct kvm_vcpu *vcpu, u64 vadr);
|
||||
extern void alt_dtlb(struct kvm_vcpu *vcpu, u64 vadr);
|
||||
extern void nested_dtlb(struct kvm_vcpu *vcpu);
|
||||
extern void dvhpt_fault(struct kvm_vcpu *vcpu, u64 vadr);
|
||||
extern int vhpt_enabled(struct kvm_vcpu *vcpu, u64 vadr, enum vhpt_ref ref);
|
||||
|
||||
extern void update_vhpi(struct kvm_vcpu *vcpu, int vec);
|
||||
extern int irq_masked(struct kvm_vcpu *vcpu, int h_pending, int h_inservice);
|
||||
|
||||
extern int fetch_code(struct kvm_vcpu *vcpu, u64 gip, IA64_BUNDLE *pbundle);
|
||||
extern void emulate_io_inst(struct kvm_vcpu *vcpu, u64 padr, u64 ma);
|
||||
extern void vmm_transition(struct kvm_vcpu *vcpu);
|
||||
extern void vmm_trampoline(union context *from, union context *to);
|
||||
extern int vmm_entry(void);
|
||||
extern u64 vcpu_get_itc(struct kvm_vcpu *vcpu);
|
||||
|
||||
extern void vmm_reset_entry(void);
|
||||
void kvm_init_vtlb(struct kvm_vcpu *v);
|
||||
void kvm_init_vhpt(struct kvm_vcpu *v);
|
||||
void thash_init(struct thash_cb *hcb, u64 sz);
|
||||
|
||||
void panic_vm(struct kvm_vcpu *v, const char *fmt, ...);
|
||||
u64 kvm_gpa_to_mpa(u64 gpa);
|
||||
extern u64 ia64_call_vsa(u64 proc, u64 arg1, u64 arg2, u64 arg3,
|
||||
u64 arg4, u64 arg5, u64 arg6, u64 arg7);
|
||||
|
||||
extern long vmm_sanity;
|
||||
|
||||
#endif
|
||||
#endif /* __VCPU_H__ */
|
|
@ -1,99 +0,0 @@
|
|||
/*
|
||||
* vmm.c: vmm module interface with kvm module
|
||||
*
|
||||
* Copyright (c) 2007, Intel Corporation.
|
||||
*
|
||||
* Xiantao Zhang (xiantao.zhang@intel.com)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
||||
*/
|
||||
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <asm/fpswa.h>
|
||||
|
||||
#include "vcpu.h"
|
||||
|
||||
MODULE_AUTHOR("Intel");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
extern char kvm_ia64_ivt;
|
||||
extern char kvm_asm_mov_from_ar;
|
||||
extern char kvm_asm_mov_from_ar_sn2;
|
||||
extern fpswa_interface_t *vmm_fpswa_interface;
|
||||
|
||||
long vmm_sanity = 1;
|
||||
|
||||
struct kvm_vmm_info vmm_info = {
|
||||
.module = THIS_MODULE,
|
||||
.vmm_entry = vmm_entry,
|
||||
.tramp_entry = vmm_trampoline,
|
||||
.vmm_ivt = (unsigned long)&kvm_ia64_ivt,
|
||||
.patch_mov_ar = (unsigned long)&kvm_asm_mov_from_ar,
|
||||
.patch_mov_ar_sn2 = (unsigned long)&kvm_asm_mov_from_ar_sn2,
|
||||
};
|
||||
|
||||
static int __init kvm_vmm_init(void)
|
||||
{
|
||||
|
||||
vmm_fpswa_interface = fpswa_interface;
|
||||
|
||||
/*Register vmm data to kvm side*/
|
||||
return kvm_init(&vmm_info, 1024, 0, THIS_MODULE);
|
||||
}
|
||||
|
||||
static void __exit kvm_vmm_exit(void)
|
||||
{
|
||||
kvm_exit();
|
||||
return ;
|
||||
}
|
||||
|
||||
void vmm_spin_lock(vmm_spinlock_t *lock)
|
||||
{
|
||||
_vmm_raw_spin_lock(lock);
|
||||
}
|
||||
|
||||
void vmm_spin_unlock(vmm_spinlock_t *lock)
|
||||
{
|
||||
_vmm_raw_spin_unlock(lock);
|
||||
}
|
||||
|
||||
static void vcpu_debug_exit(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
struct exit_ctl_data *p = &vcpu->arch.exit_data;
|
||||
long psr;
|
||||
|
||||
local_irq_save(psr);
|
||||
p->exit_reason = EXIT_REASON_DEBUG;
|
||||
vmm_transition(vcpu);
|
||||
local_irq_restore(psr);
|
||||
}
|
||||
|
||||
asmlinkage int printk(const char *fmt, ...)
|
||||
{
|
||||
struct kvm_vcpu *vcpu = current_vcpu;
|
||||
va_list args;
|
||||
int r;
|
||||
|
||||
memset(vcpu->arch.log_buf, 0, VMM_LOG_LEN);
|
||||
va_start(args, fmt);
|
||||
r = vsnprintf(vcpu->arch.log_buf, VMM_LOG_LEN, fmt, args);
|
||||
va_end(args);
|
||||
vcpu_debug_exit(vcpu);
|
||||
return r;
|
||||
}
|
||||
|
||||
module_init(kvm_vmm_init)
|
||||
module_exit(kvm_vmm_exit)
|
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
@ -1,290 +0,0 @@
|
|||
/*
|
||||
* vti.h: prototype for generial vt related interface
|
||||
* Copyright (c) 2004, Intel Corporation.
|
||||
*
|
||||
* Xuefei Xu (Anthony Xu) (anthony.xu@intel.com)
|
||||
* Fred Yang (fred.yang@intel.com)
|
||||
* Kun Tian (Kevin Tian) (kevin.tian@intel.com)
|
||||
*
|
||||
* Copyright (c) 2007, Intel Corporation.
|
||||
* Zhang xiantao <xiantao.zhang@intel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
||||
*/
|
||||
#ifndef _KVM_VT_I_H
|
||||
#define _KVM_VT_I_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#include <asm/page.h>
|
||||
|
||||
#include <linux/kvm_host.h>
|
||||
|
||||
/* define itr.i and itr.d in ia64_itr function */
|
||||
#define ITR 0x01
|
||||
#define DTR 0x02
|
||||
#define IaDTR 0x03
|
||||
|
||||
#define IA64_TR_VMM 6 /*itr6, dtr6 : maps vmm code, vmbuffer*/
|
||||
#define IA64_TR_VM_DATA 7 /*dtr7 : maps current vm data*/
|
||||
|
||||
#define RR6 (6UL<<61)
|
||||
#define RR7 (7UL<<61)
|
||||
|
||||
|
||||
/* config_options in pal_vp_init_env */
|
||||
#define VP_INITIALIZE 1UL
|
||||
#define VP_FR_PMC 1UL<<1
|
||||
#define VP_OPCODE 1UL<<8
|
||||
#define VP_CAUSE 1UL<<9
|
||||
#define VP_FW_ACC 1UL<<63
|
||||
|
||||
/* init vp env with initializing vm_buffer */
|
||||
#define VP_INIT_ENV_INITALIZE (VP_INITIALIZE | VP_FR_PMC |\
|
||||
VP_OPCODE | VP_CAUSE | VP_FW_ACC)
|
||||
/* init vp env without initializing vm_buffer */
|
||||
#define VP_INIT_ENV VP_FR_PMC | VP_OPCODE | VP_CAUSE | VP_FW_ACC
|
||||
|
||||
#define PAL_VP_CREATE 265
|
||||
/* Stacked Virt. Initializes a new VPD for the operation of
|
||||
* a new virtual processor in the virtual environment.
|
||||
*/
|
||||
#define PAL_VP_ENV_INFO 266
|
||||
/*Stacked Virt. Returns the parameters needed to enter a virtual environment.*/
|
||||
#define PAL_VP_EXIT_ENV 267
|
||||
/*Stacked Virt. Allows a logical processor to exit a virtual environment.*/
|
||||
#define PAL_VP_INIT_ENV 268
|
||||
/*Stacked Virt. Allows a logical processor to enter a virtual environment.*/
|
||||
#define PAL_VP_REGISTER 269
|
||||
/*Stacked Virt. Register a different host IVT for the virtual processor.*/
|
||||
#define PAL_VP_RESUME 270
|
||||
/* Renamed from PAL_VP_RESUME */
|
||||
#define PAL_VP_RESTORE 270
|
||||
/*Stacked Virt. Resumes virtual processor operation on the logical processor.*/
|
||||
#define PAL_VP_SUSPEND 271
|
||||
/* Renamed from PAL_VP_SUSPEND */
|
||||
#define PAL_VP_SAVE 271
|
||||
/* Stacked Virt. Suspends operation for the specified virtual processor on
|
||||
* the logical processor.
|
||||
*/
|
||||
#define PAL_VP_TERMINATE 272
|
||||
/* Stacked Virt. Terminates operation for the specified virtual processor.*/
|
||||
|
||||
union vac {
|
||||
unsigned long value;
|
||||
struct {
|
||||
unsigned int a_int:1;
|
||||
unsigned int a_from_int_cr:1;
|
||||
unsigned int a_to_int_cr:1;
|
||||
unsigned int a_from_psr:1;
|
||||
unsigned int a_from_cpuid:1;
|
||||
unsigned int a_cover:1;
|
||||
unsigned int a_bsw:1;
|
||||
long reserved:57;
|
||||
};
|
||||
};
|
||||
|
||||
union vdc {
|
||||
unsigned long value;
|
||||
struct {
|
||||
unsigned int d_vmsw:1;
|
||||
unsigned int d_extint:1;
|
||||
unsigned int d_ibr_dbr:1;
|
||||
unsigned int d_pmc:1;
|
||||
unsigned int d_to_pmd:1;
|
||||
unsigned int d_itm:1;
|
||||
long reserved:58;
|
||||
};
|
||||
};
|
||||
|
||||
struct vpd {
|
||||
union vac vac;
|
||||
union vdc vdc;
|
||||
unsigned long virt_env_vaddr;
|
||||
unsigned long reserved1[29];
|
||||
unsigned long vhpi;
|
||||
unsigned long reserved2[95];
|
||||
unsigned long vgr[16];
|
||||
unsigned long vbgr[16];
|
||||
unsigned long vnat;
|
||||
unsigned long vbnat;
|
||||
unsigned long vcpuid[5];
|
||||
unsigned long reserved3[11];
|
||||
unsigned long vpsr;
|
||||
unsigned long vpr;
|
||||
unsigned long reserved4[76];
|
||||
union {
|
||||
unsigned long vcr[128];
|
||||
struct {
|
||||
unsigned long dcr;
|
||||
unsigned long itm;
|
||||
unsigned long iva;
|
||||
unsigned long rsv1[5];
|
||||
unsigned long pta;
|
||||
unsigned long rsv2[7];
|
||||
unsigned long ipsr;
|
||||
unsigned long isr;
|
||||
unsigned long rsv3;
|
||||
unsigned long iip;
|
||||
unsigned long ifa;
|
||||
unsigned long itir;
|
||||
unsigned long iipa;
|
||||
unsigned long ifs;
|
||||
unsigned long iim;
|
||||
unsigned long iha;
|
||||
unsigned long rsv4[38];
|
||||
unsigned long lid;
|
||||
unsigned long ivr;
|
||||
unsigned long tpr;
|
||||
unsigned long eoi;
|
||||
unsigned long irr[4];
|
||||
unsigned long itv;
|
||||
unsigned long pmv;
|
||||
unsigned long cmcv;
|
||||
unsigned long rsv5[5];
|
||||
unsigned long lrr0;
|
||||
unsigned long lrr1;
|
||||
unsigned long rsv6[46];
|
||||
};
|
||||
};
|
||||
unsigned long reserved5[128];
|
||||
unsigned long reserved6[3456];
|
||||
unsigned long vmm_avail[128];
|
||||
unsigned long reserved7[4096];
|
||||
};
|
||||
|
||||
#define PAL_PROC_VM_BIT (1UL << 40)
|
||||
#define PAL_PROC_VMSW_BIT (1UL << 54)
|
||||
|
||||
static inline s64 ia64_pal_vp_env_info(u64 *buffer_size,
|
||||
u64 *vp_env_info)
|
||||
{
|
||||
struct ia64_pal_retval iprv;
|
||||
PAL_CALL_STK(iprv, PAL_VP_ENV_INFO, 0, 0, 0);
|
||||
*buffer_size = iprv.v0;
|
||||
*vp_env_info = iprv.v1;
|
||||
return iprv.status;
|
||||
}
|
||||
|
||||
static inline s64 ia64_pal_vp_exit_env(u64 iva)
|
||||
{
|
||||
struct ia64_pal_retval iprv;
|
||||
|
||||
PAL_CALL_STK(iprv, PAL_VP_EXIT_ENV, (u64)iva, 0, 0);
|
||||
return iprv.status;
|
||||
}
|
||||
|
||||
static inline s64 ia64_pal_vp_init_env(u64 config_options, u64 pbase_addr,
|
||||
u64 vbase_addr, u64 *vsa_base)
|
||||
{
|
||||
struct ia64_pal_retval iprv;
|
||||
|
||||
PAL_CALL_STK(iprv, PAL_VP_INIT_ENV, config_options, pbase_addr,
|
||||
vbase_addr);
|
||||
*vsa_base = iprv.v0;
|
||||
|
||||
return iprv.status;
|
||||
}
|
||||
|
||||
static inline s64 ia64_pal_vp_restore(u64 *vpd, u64 pal_proc_vector)
|
||||
{
|
||||
struct ia64_pal_retval iprv;
|
||||
|
||||
PAL_CALL_STK(iprv, PAL_VP_RESTORE, (u64)vpd, pal_proc_vector, 0);
|
||||
|
||||
return iprv.status;
|
||||
}
|
||||
|
||||
static inline s64 ia64_pal_vp_save(u64 *vpd, u64 pal_proc_vector)
|
||||
{
|
||||
struct ia64_pal_retval iprv;
|
||||
|
||||
PAL_CALL_STK(iprv, PAL_VP_SAVE, (u64)vpd, pal_proc_vector, 0);
|
||||
|
||||
return iprv.status;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*VPD field offset*/
|
||||
#define VPD_VAC_START_OFFSET 0
|
||||
#define VPD_VDC_START_OFFSET 8
|
||||
#define VPD_VHPI_START_OFFSET 256
|
||||
#define VPD_VGR_START_OFFSET 1024
|
||||
#define VPD_VBGR_START_OFFSET 1152
|
||||
#define VPD_VNAT_START_OFFSET 1280
|
||||
#define VPD_VBNAT_START_OFFSET 1288
|
||||
#define VPD_VCPUID_START_OFFSET 1296
|
||||
#define VPD_VPSR_START_OFFSET 1424
|
||||
#define VPD_VPR_START_OFFSET 1432
|
||||
#define VPD_VRSE_CFLE_START_OFFSET 1440
|
||||
#define VPD_VCR_START_OFFSET 2048
|
||||
#define VPD_VTPR_START_OFFSET 2576
|
||||
#define VPD_VRR_START_OFFSET 3072
|
||||
#define VPD_VMM_VAIL_START_OFFSET 31744
|
||||
|
||||
/*Virtualization faults*/
|
||||
|
||||
#define EVENT_MOV_TO_AR 1
|
||||
#define EVENT_MOV_TO_AR_IMM 2
|
||||
#define EVENT_MOV_FROM_AR 3
|
||||
#define EVENT_MOV_TO_CR 4
|
||||
#define EVENT_MOV_FROM_CR 5
|
||||
#define EVENT_MOV_TO_PSR 6
|
||||
#define EVENT_MOV_FROM_PSR 7
|
||||
#define EVENT_ITC_D 8
|
||||
#define EVENT_ITC_I 9
|
||||
#define EVENT_MOV_TO_RR 10
|
||||
#define EVENT_MOV_TO_DBR 11
|
||||
#define EVENT_MOV_TO_IBR 12
|
||||
#define EVENT_MOV_TO_PKR 13
|
||||
#define EVENT_MOV_TO_PMC 14
|
||||
#define EVENT_MOV_TO_PMD 15
|
||||
#define EVENT_ITR_D 16
|
||||
#define EVENT_ITR_I 17
|
||||
#define EVENT_MOV_FROM_RR 18
|
||||
#define EVENT_MOV_FROM_DBR 19
|
||||
#define EVENT_MOV_FROM_IBR 20
|
||||
#define EVENT_MOV_FROM_PKR 21
|
||||
#define EVENT_MOV_FROM_PMC 22
|
||||
#define EVENT_MOV_FROM_CPUID 23
|
||||
#define EVENT_SSM 24
|
||||
#define EVENT_RSM 25
|
||||
#define EVENT_PTC_L 26
|
||||
#define EVENT_PTC_G 27
|
||||
#define EVENT_PTC_GA 28
|
||||
#define EVENT_PTR_D 29
|
||||
#define EVENT_PTR_I 30
|
||||
#define EVENT_THASH 31
|
||||
#define EVENT_TTAG 32
|
||||
#define EVENT_TPA 33
|
||||
#define EVENT_TAK 34
|
||||
#define EVENT_PTC_E 35
|
||||
#define EVENT_COVER 36
|
||||
#define EVENT_RFI 37
|
||||
#define EVENT_BSW_0 38
|
||||
#define EVENT_BSW_1 39
|
||||
#define EVENT_VMSW 40
|
||||
|
||||
/**PAL virtual services offsets */
|
||||
#define PAL_VPS_RESUME_NORMAL 0x0000
|
||||
#define PAL_VPS_RESUME_HANDLER 0x0400
|
||||
#define PAL_VPS_SYNC_READ 0x0800
|
||||
#define PAL_VPS_SYNC_WRITE 0x0c00
|
||||
#define PAL_VPS_SET_PENDING_INTERRUPT 0x1000
|
||||
#define PAL_VPS_THASH 0x1400
|
||||
#define PAL_VPS_TTAG 0x1800
|
||||
#define PAL_VPS_RESTORE 0x1c00
|
||||
#define PAL_VPS_SAVE 0x2000
|
||||
|
||||
#endif/* _VT_I_H*/
|
|
@ -1,640 +0,0 @@
|
|||
/*
|
||||
* vtlb.c: guest virtual tlb handling module.
|
||||
* Copyright (c) 2004, Intel Corporation.
|
||||
* Yaozu Dong (Eddie Dong) <Eddie.dong@intel.com>
|
||||
* Xuefei Xu (Anthony Xu) <anthony.xu@intel.com>
|
||||
*
|
||||
* Copyright (c) 2007, Intel Corporation.
|
||||
* Xuefei Xu (Anthony Xu) <anthony.xu@intel.com>
|
||||
* Xiantao Zhang <xiantao.zhang@intel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
|
||||
* Place - Suite 330, Boston, MA 02111-1307 USA.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "vcpu.h"
|
||||
|
||||
#include <linux/rwsem.h>
|
||||
|
||||
#include <asm/tlb.h>
|
||||
|
||||
/*
|
||||
* Check to see if the address rid:va is translated by the TLB
|
||||
*/
|
||||
|
||||
static int __is_tr_translated(struct thash_data *trp, u64 rid, u64 va)
|
||||
{
|
||||
return ((trp->p) && (trp->rid == rid)
|
||||
&& ((va-trp->vadr) < PSIZE(trp->ps)));
|
||||
}
|
||||
|
||||
/*
|
||||
* Only for GUEST TR format.
|
||||
*/
|
||||
static int __is_tr_overlap(struct thash_data *trp, u64 rid, u64 sva, u64 eva)
|
||||
{
|
||||
u64 sa1, ea1;
|
||||
|
||||
if (!trp->p || trp->rid != rid)
|
||||
return 0;
|
||||
|
||||
sa1 = trp->vadr;
|
||||
ea1 = sa1 + PSIZE(trp->ps) - 1;
|
||||
eva -= 1;
|
||||
if ((sva > ea1) || (sa1 > eva))
|
||||
return 0;
|
||||
else
|
||||
return 1;
|
||||
|
||||
}
|
||||
|
||||
void machine_tlb_purge(u64 va, u64 ps)
|
||||
{
|
||||
ia64_ptcl(va, ps << 2);
|
||||
}
|
||||
|
||||
void local_flush_tlb_all(void)
|
||||
{
|
||||
int i, j;
|
||||
unsigned long flags, count0, count1;
|
||||
unsigned long stride0, stride1, addr;
|
||||
|
||||
addr = current_vcpu->arch.ptce_base;
|
||||
count0 = current_vcpu->arch.ptce_count[0];
|
||||
count1 = current_vcpu->arch.ptce_count[1];
|
||||
stride0 = current_vcpu->arch.ptce_stride[0];
|
||||
stride1 = current_vcpu->arch.ptce_stride[1];
|
||||
|
||||
local_irq_save(flags);
|
||||
for (i = 0; i < count0; ++i) {
|
||||
for (j = 0; j < count1; ++j) {
|
||||
ia64_ptce(addr);
|
||||
addr += stride1;
|
||||
}
|
||||
addr += stride0;
|
||||
}
|
||||
local_irq_restore(flags);
|
||||
ia64_srlz_i(); /* srlz.i implies srlz.d */
|
||||
}
|
||||
|
||||
int vhpt_enabled(struct kvm_vcpu *vcpu, u64 vadr, enum vhpt_ref ref)
|
||||
{
|
||||
union ia64_rr vrr;
|
||||
union ia64_pta vpta;
|
||||
struct ia64_psr vpsr;
|
||||
|
||||
vpsr = *(struct ia64_psr *)&VCPU(vcpu, vpsr);
|
||||
vrr.val = vcpu_get_rr(vcpu, vadr);
|
||||
vpta.val = vcpu_get_pta(vcpu);
|
||||
|
||||
if (vrr.ve & vpta.ve) {
|
||||
switch (ref) {
|
||||
case DATA_REF:
|
||||
case NA_REF:
|
||||
return vpsr.dt;
|
||||
case INST_REF:
|
||||
return vpsr.dt && vpsr.it && vpsr.ic;
|
||||
case RSE_REF:
|
||||
return vpsr.dt && vpsr.rt;
|
||||
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct thash_data *vsa_thash(union ia64_pta vpta, u64 va, u64 vrr, u64 *tag)
|
||||
{
|
||||
u64 index, pfn, rid, pfn_bits;
|
||||
|
||||
pfn_bits = vpta.size - 5 - 8;
|
||||
pfn = REGION_OFFSET(va) >> _REGION_PAGE_SIZE(vrr);
|
||||
rid = _REGION_ID(vrr);
|
||||
index = ((rid & 0xff) << pfn_bits)|(pfn & ((1UL << pfn_bits) - 1));
|
||||
*tag = ((rid >> 8) & 0xffff) | ((pfn >> pfn_bits) << 16);
|
||||
|
||||
return (struct thash_data *)((vpta.base << PTA_BASE_SHIFT) +
|
||||
(index << 5));
|
||||
}
|
||||
|
||||
struct thash_data *__vtr_lookup(struct kvm_vcpu *vcpu, u64 va, int type)
|
||||
{
|
||||
|
||||
struct thash_data *trp;
|
||||
int i;
|
||||
u64 rid;
|
||||
|
||||
rid = vcpu_get_rr(vcpu, va);
|
||||
rid = rid & RR_RID_MASK;
|
||||
if (type == D_TLB) {
|
||||
if (vcpu_quick_region_check(vcpu->arch.dtr_regions, va)) {
|
||||
for (trp = (struct thash_data *)&vcpu->arch.dtrs, i = 0;
|
||||
i < NDTRS; i++, trp++) {
|
||||
if (__is_tr_translated(trp, rid, va))
|
||||
return trp;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (vcpu_quick_region_check(vcpu->arch.itr_regions, va)) {
|
||||
for (trp = (struct thash_data *)&vcpu->arch.itrs, i = 0;
|
||||
i < NITRS; i++, trp++) {
|
||||
if (__is_tr_translated(trp, rid, va))
|
||||
return trp;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void vhpt_insert(u64 pte, u64 itir, u64 ifa, u64 gpte)
|
||||
{
|
||||
union ia64_rr rr;
|
||||
struct thash_data *head;
|
||||
unsigned long ps, gpaddr;
|
||||
|
||||
ps = itir_ps(itir);
|
||||
rr.val = ia64_get_rr(ifa);
|
||||
|
||||
gpaddr = ((gpte & _PAGE_PPN_MASK) >> ps << ps) |
|
||||
(ifa & ((1UL << ps) - 1));
|
||||
|
||||
head = (struct thash_data *)ia64_thash(ifa);
|
||||
head->etag = INVALID_TI_TAG;
|
||||
ia64_mf();
|
||||
head->page_flags = pte & ~PAGE_FLAGS_RV_MASK;
|
||||
head->itir = rr.ps << 2;
|
||||
head->etag = ia64_ttag(ifa);
|
||||
head->gpaddr = gpaddr;
|
||||
}
|
||||
|
||||
void mark_pages_dirty(struct kvm_vcpu *v, u64 pte, u64 ps)
|
||||
{
|
||||
u64 i, dirty_pages = 1;
|
||||
u64 base_gfn = (pte&_PAGE_PPN_MASK) >> PAGE_SHIFT;
|
||||
vmm_spinlock_t *lock = __kvm_va(v->arch.dirty_log_lock_pa);
|
||||
void *dirty_bitmap = (void *)KVM_MEM_DIRTY_LOG_BASE;
|
||||
|
||||
dirty_pages <<= ps <= PAGE_SHIFT ? 0 : ps - PAGE_SHIFT;
|
||||
|
||||
vmm_spin_lock(lock);
|
||||
for (i = 0; i < dirty_pages; i++) {
|
||||
/* avoid RMW */
|
||||
if (!test_bit(base_gfn + i, dirty_bitmap))
|
||||
set_bit(base_gfn + i , dirty_bitmap);
|
||||
}
|
||||
vmm_spin_unlock(lock);
|
||||
}
|
||||
|
||||
void thash_vhpt_insert(struct kvm_vcpu *v, u64 pte, u64 itir, u64 va, int type)
|
||||
{
|
||||
u64 phy_pte, psr;
|
||||
union ia64_rr mrr;
|
||||
|
||||
mrr.val = ia64_get_rr(va);
|
||||
phy_pte = translate_phy_pte(&pte, itir, va);
|
||||
|
||||
if (itir_ps(itir) >= mrr.ps) {
|
||||
vhpt_insert(phy_pte, itir, va, pte);
|
||||
} else {
|
||||
phy_pte &= ~PAGE_FLAGS_RV_MASK;
|
||||
psr = ia64_clear_ic();
|
||||
ia64_itc(type, va, phy_pte, itir_ps(itir));
|
||||
paravirt_dv_serialize_data();
|
||||
ia64_set_psr(psr);
|
||||
}
|
||||
|
||||
if (!(pte&VTLB_PTE_IO))
|
||||
mark_pages_dirty(v, pte, itir_ps(itir));
|
||||
}
|
||||
|
||||
/*
|
||||
* vhpt lookup
|
||||
*/
|
||||
struct thash_data *vhpt_lookup(u64 va)
|
||||
{
|
||||
struct thash_data *head;
|
||||
u64 tag;
|
||||
|
||||
head = (struct thash_data *)ia64_thash(va);
|
||||
tag = ia64_ttag(va);
|
||||
if (head->etag == tag)
|
||||
return head;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
u64 guest_vhpt_lookup(u64 iha, u64 *pte)
|
||||
{
|
||||
u64 ret;
|
||||
struct thash_data *data;
|
||||
|
||||
data = __vtr_lookup(current_vcpu, iha, D_TLB);
|
||||
if (data != NULL)
|
||||
thash_vhpt_insert(current_vcpu, data->page_flags,
|
||||
data->itir, iha, D_TLB);
|
||||
|
||||
asm volatile ("rsm psr.ic|psr.i;;"
|
||||
"srlz.d;;"
|
||||
"ld8.s r9=[%1];;"
|
||||
"tnat.nz p6,p7=r9;;"
|
||||
"(p6) mov %0=1;"
|
||||
"(p6) mov r9=r0;"
|
||||
"(p7) extr.u r9=r9,0,53;;"
|
||||
"(p7) mov %0=r0;"
|
||||
"(p7) st8 [%2]=r9;;"
|
||||
"ssm psr.ic;;"
|
||||
"srlz.d;;"
|
||||
"ssm psr.i;;"
|
||||
"srlz.d;;"
|
||||
: "=&r"(ret) : "r"(iha), "r"(pte) : "memory");
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* purge software guest tlb
|
||||
*/
|
||||
|
||||
static void vtlb_purge(struct kvm_vcpu *v, u64 va, u64 ps)
|
||||
{
|
||||
struct thash_data *cur;
|
||||
u64 start, curadr, size, psbits, tag, rr_ps, num;
|
||||
union ia64_rr vrr;
|
||||
struct thash_cb *hcb = &v->arch.vtlb;
|
||||
|
||||
vrr.val = vcpu_get_rr(v, va);
|
||||
psbits = VMX(v, psbits[(va >> 61)]);
|
||||
start = va & ~((1UL << ps) - 1);
|
||||
while (psbits) {
|
||||
curadr = start;
|
||||
rr_ps = __ffs(psbits);
|
||||
psbits &= ~(1UL << rr_ps);
|
||||
num = 1UL << ((ps < rr_ps) ? 0 : (ps - rr_ps));
|
||||
size = PSIZE(rr_ps);
|
||||
vrr.ps = rr_ps;
|
||||
while (num) {
|
||||
cur = vsa_thash(hcb->pta, curadr, vrr.val, &tag);
|
||||
if (cur->etag == tag && cur->ps == rr_ps)
|
||||
cur->etag = INVALID_TI_TAG;
|
||||
curadr += size;
|
||||
num--;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* purge VHPT and machine TLB
|
||||
*/
|
||||
static void vhpt_purge(struct kvm_vcpu *v, u64 va, u64 ps)
|
||||
{
|
||||
struct thash_data *cur;
|
||||
u64 start, size, tag, num;
|
||||
union ia64_rr rr;
|
||||
|
||||
start = va & ~((1UL << ps) - 1);
|
||||
rr.val = ia64_get_rr(va);
|
||||
size = PSIZE(rr.ps);
|
||||
num = 1UL << ((ps < rr.ps) ? 0 : (ps - rr.ps));
|
||||
while (num) {
|
||||
cur = (struct thash_data *)ia64_thash(start);
|
||||
tag = ia64_ttag(start);
|
||||
if (cur->etag == tag)
|
||||
cur->etag = INVALID_TI_TAG;
|
||||
start += size;
|
||||
num--;
|
||||
}
|
||||
machine_tlb_purge(va, ps);
|
||||
}
|
||||
|
||||
/*
|
||||
* Insert an entry into hash TLB or VHPT.
|
||||
* NOTES:
|
||||
* 1: When inserting VHPT to thash, "va" is a must covered
|
||||
* address by the inserted machine VHPT entry.
|
||||
* 2: The format of entry is always in TLB.
|
||||
* 3: The caller need to make sure the new entry will not overlap
|
||||
* with any existed entry.
|
||||
*/
|
||||
void vtlb_insert(struct kvm_vcpu *v, u64 pte, u64 itir, u64 va)
|
||||
{
|
||||
struct thash_data *head;
|
||||
union ia64_rr vrr;
|
||||
u64 tag;
|
||||
struct thash_cb *hcb = &v->arch.vtlb;
|
||||
|
||||
vrr.val = vcpu_get_rr(v, va);
|
||||
vrr.ps = itir_ps(itir);
|
||||
VMX(v, psbits[va >> 61]) |= (1UL << vrr.ps);
|
||||
head = vsa_thash(hcb->pta, va, vrr.val, &tag);
|
||||
head->page_flags = pte;
|
||||
head->itir = itir;
|
||||
head->etag = tag;
|
||||
}
|
||||
|
||||
int vtr_find_overlap(struct kvm_vcpu *vcpu, u64 va, u64 ps, int type)
|
||||
{
|
||||
struct thash_data *trp;
|
||||
int i;
|
||||
u64 end, rid;
|
||||
|
||||
rid = vcpu_get_rr(vcpu, va);
|
||||
rid = rid & RR_RID_MASK;
|
||||
end = va + PSIZE(ps);
|
||||
if (type == D_TLB) {
|
||||
if (vcpu_quick_region_check(vcpu->arch.dtr_regions, va)) {
|
||||
for (trp = (struct thash_data *)&vcpu->arch.dtrs, i = 0;
|
||||
i < NDTRS; i++, trp++) {
|
||||
if (__is_tr_overlap(trp, rid, va, end))
|
||||
return i;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (vcpu_quick_region_check(vcpu->arch.itr_regions, va)) {
|
||||
for (trp = (struct thash_data *)&vcpu->arch.itrs, i = 0;
|
||||
i < NITRS; i++, trp++) {
|
||||
if (__is_tr_overlap(trp, rid, va, end))
|
||||
return i;
|
||||
}
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Purge entries in VTLB and VHPT
|
||||
*/
|
||||
void thash_purge_entries(struct kvm_vcpu *v, u64 va, u64 ps)
|
||||
{
|
||||
if (vcpu_quick_region_check(v->arch.tc_regions, va))
|
||||
vtlb_purge(v, va, ps);
|
||||
vhpt_purge(v, va, ps);
|
||||
}
|
||||
|
||||
void thash_purge_entries_remote(struct kvm_vcpu *v, u64 va, u64 ps)
|
||||
{
|
||||
u64 old_va = va;
|
||||
va = REGION_OFFSET(va);
|
||||
if (vcpu_quick_region_check(v->arch.tc_regions, old_va))
|
||||
vtlb_purge(v, va, ps);
|
||||
vhpt_purge(v, va, ps);
|
||||
}
|
||||
|
||||
u64 translate_phy_pte(u64 *pte, u64 itir, u64 va)
|
||||
{
|
||||
u64 ps, ps_mask, paddr, maddr, io_mask;
|
||||
union pte_flags phy_pte;
|
||||
|
||||
ps = itir_ps(itir);
|
||||
ps_mask = ~((1UL << ps) - 1);
|
||||
phy_pte.val = *pte;
|
||||
paddr = *pte;
|
||||
paddr = ((paddr & _PAGE_PPN_MASK) & ps_mask) | (va & ~ps_mask);
|
||||
maddr = kvm_get_mpt_entry(paddr >> PAGE_SHIFT);
|
||||
io_mask = maddr & GPFN_IO_MASK;
|
||||
if (io_mask && (io_mask != GPFN_PHYS_MMIO)) {
|
||||
*pte |= VTLB_PTE_IO;
|
||||
return -1;
|
||||
}
|
||||
maddr = ((maddr & _PAGE_PPN_MASK) & PAGE_MASK) |
|
||||
(paddr & ~PAGE_MASK);
|
||||
phy_pte.ppn = maddr >> ARCH_PAGE_SHIFT;
|
||||
return phy_pte.val;
|
||||
}
|
||||
|
||||
/*
|
||||
* Purge overlap TCs and then insert the new entry to emulate itc ops.
|
||||
* Notes: Only TC entry can purge and insert.
|
||||
*/
|
||||
void thash_purge_and_insert(struct kvm_vcpu *v, u64 pte, u64 itir,
|
||||
u64 ifa, int type)
|
||||
{
|
||||
u64 ps;
|
||||
u64 phy_pte, io_mask, index;
|
||||
union ia64_rr vrr, mrr;
|
||||
|
||||
ps = itir_ps(itir);
|
||||
vrr.val = vcpu_get_rr(v, ifa);
|
||||
mrr.val = ia64_get_rr(ifa);
|
||||
|
||||
index = (pte & _PAGE_PPN_MASK) >> PAGE_SHIFT;
|
||||
io_mask = kvm_get_mpt_entry(index) & GPFN_IO_MASK;
|
||||
phy_pte = translate_phy_pte(&pte, itir, ifa);
|
||||
|
||||
/* Ensure WB attribute if pte is related to a normal mem page,
|
||||
* which is required by vga acceleration since qemu maps shared
|
||||
* vram buffer with WB.
|
||||
*/
|
||||
if (!(pte & VTLB_PTE_IO) && ((pte & _PAGE_MA_MASK) != _PAGE_MA_NAT) &&
|
||||
io_mask != GPFN_PHYS_MMIO) {
|
||||
pte &= ~_PAGE_MA_MASK;
|
||||
phy_pte &= ~_PAGE_MA_MASK;
|
||||
}
|
||||
|
||||
vtlb_purge(v, ifa, ps);
|
||||
vhpt_purge(v, ifa, ps);
|
||||
|
||||
if ((ps != mrr.ps) || (pte & VTLB_PTE_IO)) {
|
||||
vtlb_insert(v, pte, itir, ifa);
|
||||
vcpu_quick_region_set(VMX(v, tc_regions), ifa);
|
||||
}
|
||||
if (pte & VTLB_PTE_IO)
|
||||
return;
|
||||
|
||||
if (ps >= mrr.ps)
|
||||
vhpt_insert(phy_pte, itir, ifa, pte);
|
||||
else {
|
||||
u64 psr;
|
||||
phy_pte &= ~PAGE_FLAGS_RV_MASK;
|
||||
psr = ia64_clear_ic();
|
||||
ia64_itc(type, ifa, phy_pte, ps);
|
||||
paravirt_dv_serialize_data();
|
||||
ia64_set_psr(psr);
|
||||
}
|
||||
if (!(pte&VTLB_PTE_IO))
|
||||
mark_pages_dirty(v, pte, ps);
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* Purge all TCs or VHPT entries including those in Hash table.
|
||||
*
|
||||
*/
|
||||
|
||||
void thash_purge_all(struct kvm_vcpu *v)
|
||||
{
|
||||
int i;
|
||||
struct thash_data *head;
|
||||
struct thash_cb *vtlb, *vhpt;
|
||||
vtlb = &v->arch.vtlb;
|
||||
vhpt = &v->arch.vhpt;
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
VMX(v, psbits[i]) = 0;
|
||||
|
||||
head = vtlb->hash;
|
||||
for (i = 0; i < vtlb->num; i++) {
|
||||
head->page_flags = 0;
|
||||
head->etag = INVALID_TI_TAG;
|
||||
head->itir = 0;
|
||||
head->next = 0;
|
||||
head++;
|
||||
};
|
||||
|
||||
head = vhpt->hash;
|
||||
for (i = 0; i < vhpt->num; i++) {
|
||||
head->page_flags = 0;
|
||||
head->etag = INVALID_TI_TAG;
|
||||
head->itir = 0;
|
||||
head->next = 0;
|
||||
head++;
|
||||
};
|
||||
|
||||
local_flush_tlb_all();
|
||||
}
|
||||
|
||||
/*
|
||||
* Lookup the hash table and its collision chain to find an entry
|
||||
* covering this address rid:va or the entry.
|
||||
*
|
||||
* INPUT:
|
||||
* in: TLB format for both VHPT & TLB.
|
||||
*/
|
||||
struct thash_data *vtlb_lookup(struct kvm_vcpu *v, u64 va, int is_data)
|
||||
{
|
||||
struct thash_data *cch;
|
||||
u64 psbits, ps, tag;
|
||||
union ia64_rr vrr;
|
||||
|
||||
struct thash_cb *hcb = &v->arch.vtlb;
|
||||
|
||||
cch = __vtr_lookup(v, va, is_data);
|
||||
if (cch)
|
||||
return cch;
|
||||
|
||||
if (vcpu_quick_region_check(v->arch.tc_regions, va) == 0)
|
||||
return NULL;
|
||||
|
||||
psbits = VMX(v, psbits[(va >> 61)]);
|
||||
vrr.val = vcpu_get_rr(v, va);
|
||||
while (psbits) {
|
||||
ps = __ffs(psbits);
|
||||
psbits &= ~(1UL << ps);
|
||||
vrr.ps = ps;
|
||||
cch = vsa_thash(hcb->pta, va, vrr.val, &tag);
|
||||
if (cch->etag == tag && cch->ps == ps)
|
||||
return cch;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize internal control data before service.
|
||||
*/
|
||||
void thash_init(struct thash_cb *hcb, u64 sz)
|
||||
{
|
||||
int i;
|
||||
struct thash_data *head;
|
||||
|
||||
hcb->pta.val = (unsigned long)hcb->hash;
|
||||
hcb->pta.vf = 1;
|
||||
hcb->pta.ve = 1;
|
||||
hcb->pta.size = sz;
|
||||
head = hcb->hash;
|
||||
for (i = 0; i < hcb->num; i++) {
|
||||
head->page_flags = 0;
|
||||
head->itir = 0;
|
||||
head->etag = INVALID_TI_TAG;
|
||||
head->next = 0;
|
||||
head++;
|
||||
}
|
||||
}
|
||||
|
||||
u64 kvm_get_mpt_entry(u64 gpfn)
|
||||
{
|
||||
u64 *base = (u64 *) KVM_P2M_BASE;
|
||||
|
||||
if (gpfn >= (KVM_P2M_SIZE >> 3))
|
||||
panic_vm(current_vcpu, "Invalid gpfn =%lx\n", gpfn);
|
||||
|
||||
return *(base + gpfn);
|
||||
}
|
||||
|
||||
u64 kvm_lookup_mpa(u64 gpfn)
|
||||
{
|
||||
u64 maddr;
|
||||
maddr = kvm_get_mpt_entry(gpfn);
|
||||
return maddr&_PAGE_PPN_MASK;
|
||||
}
|
||||
|
||||
u64 kvm_gpa_to_mpa(u64 gpa)
|
||||
{
|
||||
u64 pte = kvm_lookup_mpa(gpa >> PAGE_SHIFT);
|
||||
return (pte >> PAGE_SHIFT << PAGE_SHIFT) | (gpa & ~PAGE_MASK);
|
||||
}
|
||||
|
||||
/*
|
||||
* Fetch guest bundle code.
|
||||
* INPUT:
|
||||
* gip: guest ip
|
||||
* pbundle: used to return fetched bundle.
|
||||
*/
|
||||
int fetch_code(struct kvm_vcpu *vcpu, u64 gip, IA64_BUNDLE *pbundle)
|
||||
{
|
||||
u64 gpip = 0; /* guest physical IP*/
|
||||
u64 *vpa;
|
||||
struct thash_data *tlb;
|
||||
u64 maddr;
|
||||
|
||||
if (!(VCPU(vcpu, vpsr) & IA64_PSR_IT)) {
|
||||
/* I-side physical mode */
|
||||
gpip = gip;
|
||||
} else {
|
||||
tlb = vtlb_lookup(vcpu, gip, I_TLB);
|
||||
if (tlb)
|
||||
gpip = (tlb->ppn >> (tlb->ps - 12) << tlb->ps) |
|
||||
(gip & (PSIZE(tlb->ps) - 1));
|
||||
}
|
||||
if (gpip) {
|
||||
maddr = kvm_gpa_to_mpa(gpip);
|
||||
} else {
|
||||
tlb = vhpt_lookup(gip);
|
||||
if (tlb == NULL) {
|
||||
ia64_ptcl(gip, ARCH_PAGE_SHIFT << 2);
|
||||
return IA64_FAULT;
|
||||
}
|
||||
maddr = (tlb->ppn >> (tlb->ps - 12) << tlb->ps)
|
||||
| (gip & (PSIZE(tlb->ps) - 1));
|
||||
}
|
||||
vpa = (u64 *)__kvm_va(maddr);
|
||||
|
||||
pbundle->i64[0] = *vpa++;
|
||||
pbundle->i64[1] = *vpa;
|
||||
|
||||
return IA64_NO_FAULT;
|
||||
}
|
||||
|
||||
void kvm_init_vhpt(struct kvm_vcpu *v)
|
||||
{
|
||||
v->arch.vhpt.num = VHPT_NUM_ENTRIES;
|
||||
thash_init(&v->arch.vhpt, VHPT_SHIFT);
|
||||
ia64_set_pta(v->arch.vhpt.pta.val);
|
||||
/*Enable VHPT here?*/
|
||||
}
|
||||
|
||||
void kvm_init_vtlb(struct kvm_vcpu *v)
|
||||
{
|
||||
v->arch.vtlb.num = VTLB_NUM_ENTRIES;
|
||||
thash_init(&v->arch.vtlb, VTLB_SHIFT);
|
||||
}
|
|
@ -586,11 +586,6 @@ static int ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
|
|||
case IOAPIC_REG_WINDOW:
|
||||
ioapic_write_indirect(ioapic, data);
|
||||
break;
|
||||
#ifdef CONFIG_IA64
|
||||
case IOAPIC_REG_EOI:
|
||||
__kvm_ioapic_update_eoi(NULL, ioapic, data, IOAPIC_LEVEL_TRIG);
|
||||
break;
|
||||
#endif
|
||||
|
||||
default:
|
||||
break;
|
||||
|
|
|
@ -19,7 +19,6 @@ struct kvm_vcpu;
|
|||
/* Direct registers. */
|
||||
#define IOAPIC_REG_SELECT 0x00
|
||||
#define IOAPIC_REG_WINDOW 0x10
|
||||
#define IOAPIC_REG_EOI 0x40 /* IA64 IOSAPIC only */
|
||||
|
||||
/* Indirect registers. */
|
||||
#define IOAPIC_REG_APIC_ID 0x00 /* x86 IOAPIC only */
|
||||
|
|
|
@ -26,9 +26,6 @@
|
|||
#include <trace/events/kvm.h>
|
||||
|
||||
#include <asm/msidef.h>
|
||||
#ifdef CONFIG_IA64
|
||||
#include <asm/iosapic.h>
|
||||
#endif
|
||||
|
||||
#include "irq.h"
|
||||
|
||||
|
@ -57,12 +54,7 @@ static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
|
|||
|
||||
inline static bool kvm_is_dm_lowest_prio(struct kvm_lapic_irq *irq)
|
||||
{
|
||||
#ifdef CONFIG_IA64
|
||||
return irq->delivery_mode ==
|
||||
(IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
|
||||
#else
|
||||
return irq->delivery_mode == APIC_DM_LOWEST;
|
||||
#endif
|
||||
}
|
||||
|
||||
int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
|
||||
|
@ -346,20 +338,6 @@ static const struct kvm_irq_routing_entry default_routing[] = {
|
|||
ROUTING_ENTRY1(18), ROUTING_ENTRY1(19),
|
||||
ROUTING_ENTRY1(20), ROUTING_ENTRY1(21),
|
||||
ROUTING_ENTRY1(22), ROUTING_ENTRY1(23),
|
||||
#ifdef CONFIG_IA64
|
||||
ROUTING_ENTRY1(24), ROUTING_ENTRY1(25),
|
||||
ROUTING_ENTRY1(26), ROUTING_ENTRY1(27),
|
||||
ROUTING_ENTRY1(28), ROUTING_ENTRY1(29),
|
||||
ROUTING_ENTRY1(30), ROUTING_ENTRY1(31),
|
||||
ROUTING_ENTRY1(32), ROUTING_ENTRY1(33),
|
||||
ROUTING_ENTRY1(34), ROUTING_ENTRY1(35),
|
||||
ROUTING_ENTRY1(36), ROUTING_ENTRY1(37),
|
||||
ROUTING_ENTRY1(38), ROUTING_ENTRY1(39),
|
||||
ROUTING_ENTRY1(40), ROUTING_ENTRY1(41),
|
||||
ROUTING_ENTRY1(42), ROUTING_ENTRY1(43),
|
||||
ROUTING_ENTRY1(44), ROUTING_ENTRY1(45),
|
||||
ROUTING_ENTRY1(46), ROUTING_ENTRY1(47),
|
||||
#endif
|
||||
};
|
||||
|
||||
int kvm_setup_default_irq_routing(struct kvm *kvm)
|
||||
|
|
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