KVM: x86 emulator: convert shift/rotate instructions to fastop
SHL, SHR, ROL, ROR, RCL, RCR, SAR, SAL Reviewed-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Avi Kivity <avi.kivity@gmail.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
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0bdea06892
Коммит
007a3b5475
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@ -478,6 +478,15 @@ static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
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ON64(FOP2E(op##q, rax, rbx)) \
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FOP_END
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/* 2 operand, src is CL */
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#define FASTOP2CL(op) \
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FOP_START(op) \
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FOP2E(op##b, al, cl) \
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FOP2E(op##w, ax, cl) \
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FOP2E(op##l, eax, cl) \
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ON64(FOP2E(op##q, rax, cl)) \
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FOP_END
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#define FOP3E(op, dst, src, src2) \
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FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
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@ -2046,38 +2055,17 @@ static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
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return X86EMUL_CONTINUE;
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}
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static int em_grp2(struct x86_emulate_ctxt *ctxt)
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{
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switch (ctxt->modrm_reg) {
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case 0: /* rol */
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emulate_2op_SrcB(ctxt, "rol");
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break;
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case 1: /* ror */
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emulate_2op_SrcB(ctxt, "ror");
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break;
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case 2: /* rcl */
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emulate_2op_SrcB(ctxt, "rcl");
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break;
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case 3: /* rcr */
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emulate_2op_SrcB(ctxt, "rcr");
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break;
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case 4: /* sal/shl */
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case 6: /* sal/shl */
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emulate_2op_SrcB(ctxt, "sal");
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break;
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case 5: /* shr */
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emulate_2op_SrcB(ctxt, "shr");
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break;
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case 7: /* sar */
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emulate_2op_SrcB(ctxt, "sar");
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break;
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}
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return X86EMUL_CONTINUE;
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}
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FASTOP1(not);
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FASTOP1(neg);
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FASTOP2CL(rol);
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FASTOP2CL(ror);
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FASTOP2CL(rcl);
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FASTOP2CL(rcr);
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FASTOP2CL(shl);
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FASTOP2CL(shr);
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FASTOP2CL(sar);
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static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
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{
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u8 ex = 0;
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@ -3726,6 +3714,17 @@ static const struct opcode group1A[] = {
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I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
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};
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static const struct opcode group2[] = {
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F(DstMem | ModRM, em_rol),
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F(DstMem | ModRM, em_ror),
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F(DstMem | ModRM, em_rcl),
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F(DstMem | ModRM, em_rcr),
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F(DstMem | ModRM, em_shl),
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F(DstMem | ModRM, em_shr),
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F(DstMem | ModRM, em_shl),
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F(DstMem | ModRM, em_sar),
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};
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static const struct opcode group3[] = {
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F(DstMem | SrcImm | NoWrite, em_test),
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F(DstMem | SrcImm | NoWrite, em_test),
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@ -3949,7 +3948,7 @@ static const struct opcode opcode_table[256] = {
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/* 0xB8 - 0xBF */
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X8(I(DstReg | SrcImm64 | Mov, em_mov)),
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/* 0xC0 - 0xC7 */
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D2bv(DstMem | SrcImmByte | ModRM),
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G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
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I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
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I(ImplicitOps | Stack, em_ret),
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I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
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@ -3961,7 +3960,8 @@ static const struct opcode opcode_table[256] = {
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D(ImplicitOps), DI(SrcImmByte, intn),
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D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
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/* 0xD0 - 0xD7 */
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D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
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G(Src2One | ByteOp, group2), G(Src2One, group2),
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G(Src2CL | ByteOp, group2), G(Src2CL, group2),
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N, I(DstAcc | SrcImmByte | No64, em_aad), N, N,
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/* 0xD8 - 0xDF */
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N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
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@ -4713,9 +4713,6 @@ special_insn:
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case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
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}
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break;
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case 0xc0 ... 0xc1:
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rc = em_grp2(ctxt);
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break;
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case 0xcc: /* int3 */
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rc = emulate_int(ctxt, 3);
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break;
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@ -4726,13 +4723,6 @@ special_insn:
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if (ctxt->eflags & EFLG_OF)
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rc = emulate_int(ctxt, 4);
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break;
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case 0xd0 ... 0xd1: /* Grp2 */
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rc = em_grp2(ctxt);
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break;
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case 0xd2 ... 0xd3: /* Grp2 */
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ctxt->src.val = reg_read(ctxt, VCPU_REGS_RCX);
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rc = em_grp2(ctxt);
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break;
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case 0xe9: /* jmp rel */
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case 0xeb: /* jmp rel short */
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jmp_rel(ctxt, ctxt->src.val);
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