platform/x86: intel_pmc_ipc: Use BIT() macro
Use BIT() and BIT_MASK() macros for definitions. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
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@ -41,13 +41,13 @@
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* the IPC1 registers, updates the IPC_STS response register with the status.
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* the IPC1 registers, updates the IPC_STS response register with the status.
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*/
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*/
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#define IPC_CMD 0x0
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#define IPC_CMD 0x0
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#define IPC_CMD_MSI 0x100
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#define IPC_CMD_MSI BIT(8)
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#define IPC_CMD_SIZE 16
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#define IPC_CMD_SIZE 16
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#define IPC_CMD_SUBCMD 12
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#define IPC_CMD_SUBCMD 12
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#define IPC_STATUS 0x04
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#define IPC_STATUS 0x04
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#define IPC_STATUS_IRQ 0x4
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#define IPC_STATUS_IRQ BIT(2)
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#define IPC_STATUS_ERR 0x2
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#define IPC_STATUS_ERR BIT(1)
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#define IPC_STATUS_BUSY 0x1
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#define IPC_STATUS_BUSY BIT(0)
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#define IPC_SPTR 0x08
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#define IPC_SPTR 0x08
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#define IPC_DPTR 0x0C
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#define IPC_DPTR 0x0C
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#define IPC_WRITE_BUFFER 0x80
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#define IPC_WRITE_BUFFER 0x80
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@ -107,7 +107,7 @@
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/* PMC register bit definitions */
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/* PMC register bit definitions */
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/* PMC_CFG_REG bit masks */
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/* PMC_CFG_REG bit masks */
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#define PMC_CFG_NO_REBOOT_MASK (1 << 4)
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#define PMC_CFG_NO_REBOOT_MASK BIT_MASK(4)
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#define PMC_CFG_NO_REBOOT_EN (1 << 4)
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#define PMC_CFG_NO_REBOOT_EN (1 << 4)
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#define PMC_CFG_NO_REBOOT_DIS (0 << 4)
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#define PMC_CFG_NO_REBOOT_DIS (0 << 4)
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