irqchip/armada-xp: Consolidate hotplug state space
The mpic is either the main interrupt controller or is cascaded behind a GIC. The mpic is single instance and the modes are mutually exclusive, so there is no reason to have seperate cpu hotplug states. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: Sebastian Siewior <bigeasy@linutronix.de> Cc: Marc Zyngier <marc.zyngier@arm.com> Link: http://lkml.kernel.org/r/20161221192112.333161745@linutronix.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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@ -583,7 +583,7 @@ static int __init armada_370_xp_mpic_of_init(struct device_node *node,
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#endif
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} else {
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#ifdef CONFIG_SMP
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cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_CASC_STARTING,
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cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
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"irqchip/armada/cascade:starting",
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mpic_cascaded_starting_cpu, NULL);
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#endif
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@ -82,7 +82,6 @@ enum cpuhp_state {
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CPUHP_AP_IRQ_GIC_STARTING,
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CPUHP_AP_IRQ_HIP04_STARTING,
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CPUHP_AP_IRQ_ARMADA_XP_STARTING,
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CPUHP_AP_IRQ_ARMADA_CASC_STARTING,
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CPUHP_AP_IRQ_BCM2836_STARTING,
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CPUHP_AP_ARM_MVEBU_COHERENCY,
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CPUHP_AP_PERF_X86_UNCORE_STARTING,
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