MIPS: lantiq: remove orphaned code
Now that all drivers are converted to OF we are able to remove some remaining pieces of orphaned code. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3841/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
John Crispin
Ralf Baechle
Родитель
d41ced01f2
Коммит
009d6914f1
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@ -27,9 +27,6 @@
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ltq_w32_mask(x, y, ltq_ebu_membase + (z))
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extern __iomem void *ltq_ebu_membase;
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extern unsigned int ltq_get_cpu_ver(void);
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extern unsigned int ltq_get_soc_type(void);
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/* spinlock all ebu i/o */
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extern spinlock_t ebu_lock;
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@ -54,7 +51,5 @@ extern int ltq_reset_cause(void);
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#define IOPORT_RESOURCE_END 0xffffffff
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#define IOMEM_RESOURCE_START 0x10000000
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#define IOMEM_RESOURCE_END 0xffffffff
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#define LTQ_FLASH_START 0x10000000
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#define LTQ_FLASH_MAX 0x04000000
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#endif
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@ -9,41 +9,8 @@
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#ifndef _LANTIQ_PLATFORM_H__
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#define _LANTIQ_PLATFORM_H__
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#include <linux/mtd/partitions.h>
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#include <linux/socket.h>
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/* struct used to pass info to the pci core */
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enum {
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PCI_CLOCK_INT = 0,
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PCI_CLOCK_EXT
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};
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#define PCI_EXIN0 0x0001
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#define PCI_EXIN1 0x0002
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#define PCI_EXIN2 0x0004
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#define PCI_EXIN3 0x0008
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#define PCI_EXIN4 0x0010
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#define PCI_EXIN5 0x0020
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#define PCI_EXIN_MAX 6
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#define PCI_GNT1 0x0040
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#define PCI_GNT2 0x0080
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#define PCI_GNT3 0x0100
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#define PCI_GNT4 0x0200
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#define PCI_REQ1 0x0400
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#define PCI_REQ2 0x0800
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#define PCI_REQ3 0x1000
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#define PCI_REQ4 0x2000
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#define PCI_REQ_SHIFT 10
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#define PCI_REQ_MASK 0xf
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struct ltq_pci_data {
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int clock;
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int gpio;
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int irq[16];
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};
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/* struct used to pass info to network drivers */
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struct ltq_eth_data {
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struct sockaddr mac;
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@ -17,50 +17,8 @@
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#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128)
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#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)
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#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8))
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#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1)
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#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2)
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#define LTQ_ASC_ASE_TIR INT_NUM_IM2_IRL0
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#define LTQ_ASC_ASE_RIR (INT_NUM_IM2_IRL0 + 2)
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#define LTQ_ASC_ASE_EIR (INT_NUM_IM2_IRL0 + 3)
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#define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15)
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#define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14)
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#define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16)
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#define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21)
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#define LTQ_MEI_INT (INT_NUM_IM1_IRL0 + 23)
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#define LTQ_TIMER6_INT (INT_NUM_IM1_IRL0 + 23)
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#define LTQ_USB_INT (INT_NUM_IM1_IRL0 + 22)
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#define LTQ_USB_OC_INT (INT_NUM_IM4_IRL0 + 23)
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#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
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#define MIPS_CPU_TIMER_IRQ 7
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#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0)
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#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1)
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#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2)
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#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3)
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#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4)
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#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5)
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#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6)
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#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7)
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#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8)
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#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9)
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#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10)
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#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11)
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#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25)
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#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26)
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#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27)
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#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28)
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#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29)
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#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30)
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#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16)
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#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21)
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#define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24)
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#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14)
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#endif
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@ -44,11 +44,6 @@
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#define SOC_TYPE_VR9_2 0x05 /* v1.2 */
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#define SOC_TYPE_AMAZON_SE 0x06
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/* ASC0/1 - serial port */
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#define LTQ_ASC0_BASE_ADDR 0x1E100400
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#define LTQ_ASC1_BASE_ADDR 0x1E100C00
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#define LTQ_ASC_SIZE 0x400
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/* BOOT_SEL - find what boot media we have */
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#define BS_EXT_ROM 0x0
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#define BS_FLASH 0x1
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@ -68,23 +63,10 @@ extern __iomem void *ltq_cgu_membase;
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* during early_printk no ioremap is possible
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* lets use KSEG1 instead
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*/
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#define LTQ_ASC1_BASE_ADDR 0x1E100C00
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#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
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/* RCU - reset control unit */
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#define LTQ_RCU_BASE_ADDR 0x1F203000
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#define LTQ_RCU_SIZE 0x1000
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/* GPTU - general purpose timer unit */
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#define LTQ_GPTU_BASE_ADDR 0x18000300
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#define LTQ_GPTU_SIZE 0x100
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/* EBU - external bus unit */
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#define LTQ_EBU_GPIO_START 0x14000000
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#define LTQ_EBU_GPIO_SIZE 0x1000
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#define LTQ_EBU_BASE_ADDR 0x1E105300
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#define LTQ_EBU_SIZE 0x100
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#define LTQ_EBU_BUSCON0 0x0060
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#define LTQ_EBU_PCC_CON 0x0090
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#define LTQ_EBU_PCC_IEN 0x00A4
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@ -93,85 +75,17 @@ extern __iomem void *ltq_cgu_membase;
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#define LTQ_EBU_ADDRSEL1 0x0024
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#define EBU_WRDIS 0x80000000
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/* CGU - clock generation unit */
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#define LTQ_CGU_BASE_ADDR 0x1F103000
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#define LTQ_CGU_SIZE 0x1000
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/* ICU - interrupt control unit */
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#define LTQ_ICU_BASE_ADDR 0x1F880200
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#define LTQ_ICU_SIZE 0x100
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/* EIU - external interrupt unit */
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#define LTQ_EIU_BASE_ADDR 0x1F101000
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#define LTQ_EIU_SIZE 0x1000
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/* PMU - power management unit */
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#define LTQ_PMU_BASE_ADDR 0x1F102000
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#define LTQ_PMU_SIZE 0x1000
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#define PMU_DMA 0x0020
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#define PMU_USB 0x8041
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#define PMU_LED 0x0800
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#define PMU_GPT 0x1000
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#define PMU_PPE 0x2000
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#define PMU_FPI 0x4000
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#define PMU_SWITCH 0x10000000
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/* ETOP - ethernet */
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#define LTQ_ETOP_BASE_ADDR 0x1E180000
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#define LTQ_ETOP_SIZE 0x40000
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/* DMA */
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#define LTQ_DMA_BASE_ADDR 0x1E104100
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#define LTQ_DMA_SIZE 0x800
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/* PCI */
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#define PCI_CR_BASE_ADDR 0x1E105400
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#define PCI_CR_SIZE 0x400
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/* WDT */
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#define LTQ_WDT_BASE_ADDR 0x1F8803F0
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#define LTQ_WDT_SIZE 0x10
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#define LTQ_RST_CAUSE_WDTRST 0x20
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/* STP - serial to parallel conversion unit */
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#define LTQ_STP_BASE_ADDR 0x1E100BB0
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#define LTQ_STP_SIZE 0x40
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/* GPIO */
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#define LTQ_GPIO0_BASE_ADDR 0x1E100B10
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#define LTQ_GPIO1_BASE_ADDR 0x1E100B40
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#define LTQ_GPIO2_BASE_ADDR 0x1E100B70
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#define LTQ_GPIO_SIZE 0x30
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/* SSC */
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#define LTQ_SSC_BASE_ADDR 0x1e100800
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#define LTQ_SSC_SIZE 0x100
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/* MEI - dsl core */
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#define LTQ_MEI_BASE_ADDR 0x1E116000
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/* DEU - data encryption unit */
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#define LTQ_DEU_BASE_ADDR 0x1E103100
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/* MPS - multi processor unit (voice) */
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#define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000)
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#define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344))
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/* request a non-gpio and set the PIO config */
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#define PMU_PPE BIT(13)
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extern void ltq_pmu_enable(unsigned int module);
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extern void ltq_pmu_disable(unsigned int module);
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static inline int ltq_is_ar9(void)
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{
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return (ltq_get_soc_type() == SOC_TYPE_AR9);
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}
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static inline int ltq_is_vr9(void)
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{
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return (ltq_get_soc_type() == SOC_TYPE_VR9);
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}
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#endif /* CONFIG_SOC_TYPE_XWAY */
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#endif /* _LTQ_XWAY_H__ */
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@ -27,12 +27,6 @@ EXPORT_SYMBOL_GPL(ebu_lock);
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*/
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static struct ltq_soc_info soc_info;
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unsigned int ltq_get_soc_type(void)
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{
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return soc_info.type;
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}
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EXPORT_SYMBOL(ltq_get_soc_type);
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const char *get_system_type(void)
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{
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return soc_info.sys_type;
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@ -42,6 +42,7 @@
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/* clock gates that we can en/disable */
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#define PMU_USB0_P BIT(0)
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#define PMU_PCI BIT(4)
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#define PMU_DMA BIT(5)
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#define PMU_USB0 BIT(6)
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#define PMU_ASC0 BIT(7)
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#define PMU_EPHY BIT(7) /* ase */
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@ -49,7 +50,9 @@
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#define PMU_DFE BIT(9)
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#define PMU_EBU BIT(10)
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#define PMU_STP BIT(11)
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#define PMU_GPT BIT(12)
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#define PMU_AHBS BIT(13) /* vr9 */
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#define PMU_FPI BIT(14)
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#define PMU_AHBM BIT(15)
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#define PMU_ASC1 BIT(17)
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#define PMU_PPE_QSB BIT(18)
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@ -60,6 +63,7 @@
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#define PMU_PPE_DPLUS BIT(24)
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#define PMU_USB1_P BIT(26)
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#define PMU_USB1 BIT(27)
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#define PMU_SWITCH BIT(28)
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#define PMU_PPE_TOP BIT(29)
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#define PMU_GPHY BIT(30)
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#define PMU_PCIE_CLK BIT(31)
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