ARM: SoC non-urgent fixes for v4.3
We normally collect non-urgent fixes during the release cycle and queue them for the merge window. This time around the list is short (in part because some have gone in other branches). - Maintainers addition for bcm2835 - IRQ number fix for orion5x (been present since 3.18) - DT fix for display on exynos3250 - Exynos fix to use of IOMEM_ERR_PTR properly -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJV5OyFAAoJEIwa5zzehBx3fuUQAJeQC42dQfSzJaQ2KE9Ob26l ARH2NKy1EYJ1b7xpwoyV2aMHpqfIuf6bo2lom1GuqsxhNViF8Sc0hKv4erm4qt1N xXZCMEAuOrpV6PLgBh+EnNre9fTRkTGqgIvFOAN0c1OtFylX8FSVWFEWeOi+ACPb APFoioB/bpylbGt0Fi8g015QERjaZXCzWZqninyiVdv+n3KuRjZsaqZ8BflmPC0a CqFrtMcHWJprxPVRZ+AxEB833HAW54FzXp0QEYzDcyHDhHkV3Oplpw9YzHBhdwAo I3TXpxX2+jF4qaIBHN9XcMJNyrN0xAT0RdTgsGk10wYTJwxFr05SmPup7KJicyvY s6N9YlS191YnXBZQTX95LzC0BDem3w5+6dEr++GwWbXs1oWfYNhk7sXr5Y/qxeCU QPhuX3OBNnSr3YcRj45iROMiVam9L88YLmQstauzszMbByRcnRBWE8ONF/h1GIFs fiZ8rypppwtiS+9pWO1VqlLOVmjReWLdR4zumyBZrg4FU7WKbw4/FWXN4cZn3D87 In5Aud+94gU3VXjunI339DkaaDBVHVMcg0/6dGg1IWwPnImzpY+EqEXDS+sdP59w gGo8YxZRgDOIi0jUFC7eOnsmQsSwlzhgQLzMlijWEp/zRhCkqFuB7lYiGAZzNylN Ac1+///e6kxc6m4N/UM8 =RBvV -----END PGP SIGNATURE----- Merge tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC non-urgent fixes from Olof Johansson: "We normally collect non-urgent fixes during the release cycle and queue them for the merge window. This time around the list is short (in part because some have gone in other branches). - Maintainers addition for bcm2835 - IRQ number fix for orion5x (been present since 3.18) - DT fix for display on exynos3250 - Exynos fix to use of IOMEM_ERR_PTR properly" * tag 'armsoc-fixes-nc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: orion5x: fix legacy orion5x IRQ numbers MAINTAINERS: Explicitly add linux-arm-kernel for bcm2835 MAINTAINERS: Add myself as a bcm2835 co-maintainer. ARM: EXYNOS: Use IOMEM_ERR_PTR when function returns iomem ARM: dts: fix clock-frequency of display timing0 for exynos3250-rinato
This commit is contained in:
Linus Torvalds
Коммит
00e3fcc221
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@ -2224,7 +2224,9 @@ F: drivers/clocksource/bcm_kona_timer.c
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BROADCOM BCM2835 ARM ARCHITECTURE
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M: Stephen Warren <swarren@wwwdotorg.org>
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M: Lee Jones <lee@kernel.org>
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M: Eric Anholt <eric@anholt.net>
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L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi.git
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S: Maintained
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N: bcm2835
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@ -536,6 +536,7 @@ config ARCH_ORION5X
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select MVEBU_MBUS
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select PCI
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select PLAT_ORION_LEGACY
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select MULTI_IRQ_HANDLER
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help
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Support for the following Marvell Orion 5x series SoCs:
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Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
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@ -182,7 +182,7 @@
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display-timings {
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timing-0 {
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clock-frequency = <0>;
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clock-frequency = <4600000>;
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hactive = <320>;
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vactive = <320>;
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hfront-porch = <1>;
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@ -182,7 +182,7 @@ static inline void __iomem *cpu_boot_reg(int cpu)
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boot_reg = cpu_boot_reg_base();
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if (!boot_reg)
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return ERR_PTR(-ENODEV);
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return IOMEM_ERR_PTR(-ENODEV);
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if (soc_is_exynos4412())
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boot_reg += 4*cpu;
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else if (soc_is_exynos5420() || soc_is_exynos5800())
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@ -16,42 +16,42 @@
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/*
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* Orion Main Interrupt Controller
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*/
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#define IRQ_ORION5X_BRIDGE 0
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#define IRQ_ORION5X_DOORBELL_H2C 1
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#define IRQ_ORION5X_DOORBELL_C2H 2
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#define IRQ_ORION5X_UART0 3
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#define IRQ_ORION5X_UART1 4
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#define IRQ_ORION5X_I2C 5
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#define IRQ_ORION5X_GPIO_0_7 6
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#define IRQ_ORION5X_GPIO_8_15 7
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#define IRQ_ORION5X_GPIO_16_23 8
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#define IRQ_ORION5X_GPIO_24_31 9
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#define IRQ_ORION5X_PCIE0_ERR 10
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#define IRQ_ORION5X_PCIE0_INT 11
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#define IRQ_ORION5X_USB1_CTRL 12
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#define IRQ_ORION5X_DEV_BUS_ERR 14
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#define IRQ_ORION5X_PCI_ERR 15
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#define IRQ_ORION5X_USB_BR_ERR 16
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#define IRQ_ORION5X_USB0_CTRL 17
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#define IRQ_ORION5X_ETH_RX 18
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#define IRQ_ORION5X_ETH_TX 19
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#define IRQ_ORION5X_ETH_MISC 20
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#define IRQ_ORION5X_ETH_SUM 21
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#define IRQ_ORION5X_ETH_ERR 22
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#define IRQ_ORION5X_IDMA_ERR 23
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#define IRQ_ORION5X_IDMA_0 24
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#define IRQ_ORION5X_IDMA_1 25
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#define IRQ_ORION5X_IDMA_2 26
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#define IRQ_ORION5X_IDMA_3 27
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#define IRQ_ORION5X_CESA 28
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#define IRQ_ORION5X_SATA 29
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#define IRQ_ORION5X_XOR0 30
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#define IRQ_ORION5X_XOR1 31
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#define IRQ_ORION5X_BRIDGE (1 + 0)
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#define IRQ_ORION5X_DOORBELL_H2C (1 + 1)
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#define IRQ_ORION5X_DOORBELL_C2H (1 + 2)
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#define IRQ_ORION5X_UART0 (1 + 3)
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#define IRQ_ORION5X_UART1 (1 + 4)
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#define IRQ_ORION5X_I2C (1 + 5)
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#define IRQ_ORION5X_GPIO_0_7 (1 + 6)
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#define IRQ_ORION5X_GPIO_8_15 (1 + 7)
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#define IRQ_ORION5X_GPIO_16_23 (1 + 8)
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#define IRQ_ORION5X_GPIO_24_31 (1 + 9)
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#define IRQ_ORION5X_PCIE0_ERR (1 + 10)
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#define IRQ_ORION5X_PCIE0_INT (1 + 11)
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#define IRQ_ORION5X_USB1_CTRL (1 + 12)
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#define IRQ_ORION5X_DEV_BUS_ERR (1 + 14)
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#define IRQ_ORION5X_PCI_ERR (1 + 15)
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#define IRQ_ORION5X_USB_BR_ERR (1 + 16)
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#define IRQ_ORION5X_USB0_CTRL (1 + 17)
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#define IRQ_ORION5X_ETH_RX (1 + 18)
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#define IRQ_ORION5X_ETH_TX (1 + 19)
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#define IRQ_ORION5X_ETH_MISC (1 + 20)
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#define IRQ_ORION5X_ETH_SUM (1 + 21)
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#define IRQ_ORION5X_ETH_ERR (1 + 22)
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#define IRQ_ORION5X_IDMA_ERR (1 + 23)
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#define IRQ_ORION5X_IDMA_0 (1 + 24)
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#define IRQ_ORION5X_IDMA_1 (1 + 25)
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#define IRQ_ORION5X_IDMA_2 (1 + 26)
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#define IRQ_ORION5X_IDMA_3 (1 + 27)
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#define IRQ_ORION5X_CESA (1 + 28)
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#define IRQ_ORION5X_SATA (1 + 29)
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#define IRQ_ORION5X_XOR0 (1 + 30)
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#define IRQ_ORION5X_XOR1 (1 + 31)
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/*
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* Orion General Purpose Pins
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*/
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#define IRQ_ORION5X_GPIO_START 32
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#define IRQ_ORION5X_GPIO_START 33
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#define NR_GPIO_IRQS 32
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#define NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
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@ -42,7 +42,7 @@ __exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs)
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stat = readl_relaxed(MAIN_IRQ_CAUSE);
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stat &= readl_relaxed(MAIN_IRQ_MASK);
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if (stat) {
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unsigned int hwirq = __fls(stat);
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unsigned int hwirq = 1 + __fls(stat);
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handle_IRQ(hwirq, regs);
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return;
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}
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@ -51,7 +51,7 @@ __exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs)
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void __init orion5x_init_irq(void)
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{
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orion_irq_init(0, MAIN_IRQ_MASK);
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orion_irq_init(1, MAIN_IRQ_MASK);
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#ifdef CONFIG_MULTI_IRQ_HANDLER
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set_handle_irq(orion5x_legacy_handle_irq);
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