spi/ep93xx: implemented driver for Cirrus EP93xx SPI controller
This patch adds an SPI master driver for the Cirrus EP93xx SPI controller found in EP93xx chips. Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi> Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
Mika Westerberg
Grant Likely
Родитель
1dcf57ceb4
Коммит
011f23a3c2
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@ -0,0 +1,95 @@
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Cirrus EP93xx SPI controller driver HOWTO
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=========================================
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ep93xx_spi driver brings SPI master support for EP93xx SPI controller. Chip
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selects are implemented with GPIO lines.
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NOTE: If possible, don't use SFRMOUT (SFRM1) signal as a chip select. It will
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not work correctly (it cannot be controlled by software). Use GPIO lines
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instead.
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Sample configuration
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====================
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Typically driver configuration is done in platform board files (the files under
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arch/arm/mach-ep93xx/*.c). In this example we configure MMC over SPI through
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this driver on TS-7260 board. You can adapt the code to suit your needs.
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This example uses EGPIO9 as SD/MMC card chip select (this is wired in DIO1
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header on the board).
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You need to select CONFIG_MMC_SPI to use mmc_spi driver.
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arch/arm/mach-ep93xx/ts72xx.c:
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...
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#include <linux/gpio.h>
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#include <linux/spi/spi.h>
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#include <mach/ep93xx_spi.h>
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/* this is our GPIO line used for chip select */
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#define MMC_CHIP_SELECT_GPIO EP93XX_GPIO_LINE_EGPIO9
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static int ts72xx_mmc_spi_setup(struct spi_device *spi)
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{
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int err;
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err = gpio_request(MMC_CHIP_SELECT_GPIO, spi->modalias);
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if (err)
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return err;
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gpio_direction_output(MMC_CHIP_SELECT_GPIO, 1);
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return 0;
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}
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static void ts72xx_mmc_spi_cleanup(struct spi_device *spi)
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{
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gpio_set_value(MMC_CHIP_SELECT_GPIO, 1);
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gpio_direction_input(MMC_CHIP_SELECT_GPIO);
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gpio_free(MMC_CHIP_SELECT_GPIO);
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}
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static void ts72xx_mmc_spi_cs_control(struct spi_device *spi, int value)
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{
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gpio_set_value(MMC_CHIP_SELECT_GPIO, value);
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}
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static struct ep93xx_spi_chip_ops ts72xx_mmc_spi_ops = {
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.setup = ts72xx_mmc_spi_setup,
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.cleanup = ts72xx_mmc_spi_cleanup,
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.cs_control = ts72xx_mmc_spi_cs_control,
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};
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static struct spi_board_info ts72xx_spi_devices[] __initdata = {
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{
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.modalias = "mmc_spi",
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.controller_data = &ts72xx_mmc_spi_ops,
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/*
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* We use 10 MHz even though the maximum is 7.4 MHz. The driver
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* will limit it automatically to max. frequency.
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*/
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.max_speed_hz = 10 * 1000 * 1000,
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.bus_num = 0,
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.chip_select = 0,
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.mode = SPI_MODE_0,
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},
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};
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static struct ep93xx_spi_info ts72xx_spi_info = {
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.num_chipselect = ARRAY_SIZE(ts72xx_spi_devices),
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};
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static void __init ts72xx_init_machine(void)
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{
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...
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ep93xx_register_spi(&ts72xx_spi_info, ts72xx_spi_devices,
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ARRAY_SIZE(ts72xx_spi_devices));
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}
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Thanks to
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=========
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Martin Guy, H. Hartley Sweeten and others who helped me during development of
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the driver. Simplemachines.it donated me a Sim.One board which I used testing
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the driver on EP9307.
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@ -0,0 +1,27 @@
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#ifndef __ASM_MACH_EP93XX_SPI_H
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#define __ASM_MACH_EP93XX_SPI_H
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struct spi_device;
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/**
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* struct ep93xx_spi_info - EP93xx specific SPI descriptor
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* @num_chipselect: number of chip selects on this board, must be
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* at least one
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*/
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struct ep93xx_spi_info {
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int num_chipselect;
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};
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/**
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* struct ep93xx_spi_chip_ops - operation callbacks for SPI slave device
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* @setup: setup the chip select mechanism
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* @cleanup: cleanup the chip select mechanism
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* @cs_control: control the device chip select
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*/
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struct ep93xx_spi_chip_ops {
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int (*setup)(struct spi_device *spi);
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void (*cleanup)(struct spi_device *spi);
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void (*cs_control)(struct spi_device *spi, int value);
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};
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#endif /* __ASM_MACH_EP93XX_SPI_H */
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@ -117,6 +117,16 @@ config SPI_DAVINCI
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help
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SPI master controller for DaVinci and DA8xx SPI modules.
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config SPI_EP93XX
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tristate "Cirrus Logic EP93xx SPI controller"
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depends on ARCH_EP93XX
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help
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This enables using the Cirrus EP93xx SPI controller in master
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mode.
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To compile this driver as a module, choose M here. The module will be
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called ep93xx_spi.
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config SPI_GPIO
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tristate "GPIO-based bitbanging SPI Master"
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depends on GENERIC_GPIO
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@ -21,6 +21,7 @@ obj-$(CONFIG_SPI_DAVINCI) += davinci_spi.o
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obj-$(CONFIG_SPI_DESIGNWARE) += dw_spi.o
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obj-$(CONFIG_SPI_DW_PCI) += dw_spi_pci.o
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obj-$(CONFIG_SPI_DW_MMIO) += dw_spi_mmio.o
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obj-$(CONFIG_SPI_EP93XX) += ep93xx_spi.o
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obj-$(CONFIG_SPI_GPIO) += spi_gpio.o
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obj-$(CONFIG_SPI_IMX) += spi_imx.o
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obj-$(CONFIG_SPI_LM70_LLP) += spi_lm70llp.o
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@ -0,0 +1,938 @@
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/*
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* Driver for Cirrus Logic EP93xx SPI controller.
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*
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* Copyright (c) 2010 Mika Westerberg
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*
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* Explicit FIFO handling code was inspired by amba-pl022 driver.
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*
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* Chip select support using other than built-in GPIOs by H. Hartley Sweeten.
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*
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* For more information about the SPI controller see documentation on Cirrus
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* Logic web site:
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* http://www.cirrus.com/en/pubs/manual/EP93xx_Users_Guide_UM1.pdf
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/bitops.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/workqueue.h>
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#include <linux/sched.h>
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#include <linux/spi/spi.h>
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#include <mach/ep93xx_spi.h>
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#define SSPCR0 0x0000
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#define SSPCR0_MODE_SHIFT 6
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#define SSPCR0_SCR_SHIFT 8
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#define SSPCR1 0x0004
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#define SSPCR1_RIE BIT(0)
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#define SSPCR1_TIE BIT(1)
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#define SSPCR1_RORIE BIT(2)
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#define SSPCR1_LBM BIT(3)
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#define SSPCR1_SSE BIT(4)
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#define SSPCR1_MS BIT(5)
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#define SSPCR1_SOD BIT(6)
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#define SSPDR 0x0008
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#define SSPSR 0x000c
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#define SSPSR_TFE BIT(0)
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#define SSPSR_TNF BIT(1)
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#define SSPSR_RNE BIT(2)
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#define SSPSR_RFF BIT(3)
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#define SSPSR_BSY BIT(4)
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#define SSPCPSR 0x0010
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#define SSPIIR 0x0014
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#define SSPIIR_RIS BIT(0)
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#define SSPIIR_TIS BIT(1)
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#define SSPIIR_RORIS BIT(2)
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#define SSPICR SSPIIR
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/* timeout in milliseconds */
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#define SPI_TIMEOUT 5
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/* maximum depth of RX/TX FIFO */
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#define SPI_FIFO_SIZE 8
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/**
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* struct ep93xx_spi - EP93xx SPI controller structure
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* @lock: spinlock that protects concurrent accesses to fields @running,
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* @current_msg and @msg_queue
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* @pdev: pointer to platform device
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* @clk: clock for the controller
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* @regs_base: pointer to ioremap()'d registers
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* @irq: IRQ number used by the driver
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* @min_rate: minimum clock rate (in Hz) supported by the controller
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* @max_rate: maximum clock rate (in Hz) supported by the controller
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* @running: is the queue running
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* @wq: workqueue used by the driver
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* @msg_work: work that is queued for the driver
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* @wait: wait here until given transfer is completed
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* @msg_queue: queue for the messages
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* @current_msg: message that is currently processed (or %NULL if none)
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* @tx: current byte in transfer to transmit
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* @rx: current byte in transfer to receive
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* @fifo_level: how full is FIFO (%0..%SPI_FIFO_SIZE - %1). Receiving one
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* frame decreases this level and sending one frame increases it.
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*
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* This structure holds EP93xx SPI controller specific information. When
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* @running is %true, driver accepts transfer requests from protocol drivers.
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* @current_msg is used to hold pointer to the message that is currently
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* processed. If @current_msg is %NULL, it means that no processing is going
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* on.
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*
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* Most of the fields are only written once and they can be accessed without
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* taking the @lock. Fields that are accessed concurrently are: @current_msg,
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* @running, and @msg_queue.
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*/
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struct ep93xx_spi {
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spinlock_t lock;
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const struct platform_device *pdev;
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struct clk *clk;
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void __iomem *regs_base;
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int irq;
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unsigned long min_rate;
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unsigned long max_rate;
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bool running;
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struct workqueue_struct *wq;
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struct work_struct msg_work;
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struct completion wait;
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struct list_head msg_queue;
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struct spi_message *current_msg;
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size_t tx;
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size_t rx;
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size_t fifo_level;
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};
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/**
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* struct ep93xx_spi_chip - SPI device hardware settings
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* @spi: back pointer to the SPI device
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* @rate: max rate in hz this chip supports
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* @div_cpsr: cpsr (pre-scaler) divider
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* @div_scr: scr divider
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* @dss: bits per word (4 - 16 bits)
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* @ops: private chip operations
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*
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* This structure is used to store hardware register specific settings for each
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* SPI device. Settings are written to hardware by function
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* ep93xx_spi_chip_setup().
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*/
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struct ep93xx_spi_chip {
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const struct spi_device *spi;
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unsigned long rate;
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u8 div_cpsr;
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u8 div_scr;
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u8 dss;
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struct ep93xx_spi_chip_ops *ops;
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};
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/* converts bits per word to CR0.DSS value */
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#define bits_per_word_to_dss(bpw) ((bpw) - 1)
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static inline void
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ep93xx_spi_write_u8(const struct ep93xx_spi *espi, u16 reg, u8 value)
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{
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__raw_writeb(value, espi->regs_base + reg);
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}
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static inline u8
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ep93xx_spi_read_u8(const struct ep93xx_spi *spi, u16 reg)
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{
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return __raw_readb(spi->regs_base + reg);
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}
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static inline void
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ep93xx_spi_write_u16(const struct ep93xx_spi *espi, u16 reg, u16 value)
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{
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__raw_writew(value, espi->regs_base + reg);
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}
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static inline u16
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ep93xx_spi_read_u16(const struct ep93xx_spi *spi, u16 reg)
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{
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return __raw_readw(spi->regs_base + reg);
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}
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static int ep93xx_spi_enable(const struct ep93xx_spi *espi)
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{
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u8 regval;
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int err;
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err = clk_enable(espi->clk);
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if (err)
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return err;
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regval = ep93xx_spi_read_u8(espi, SSPCR1);
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regval |= SSPCR1_SSE;
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ep93xx_spi_write_u8(espi, SSPCR1, regval);
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return 0;
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}
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static void ep93xx_spi_disable(const struct ep93xx_spi *espi)
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{
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u8 regval;
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regval = ep93xx_spi_read_u8(espi, SSPCR1);
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regval &= ~SSPCR1_SSE;
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ep93xx_spi_write_u8(espi, SSPCR1, regval);
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clk_disable(espi->clk);
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}
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static void ep93xx_spi_enable_interrupts(const struct ep93xx_spi *espi)
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{
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u8 regval;
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regval = ep93xx_spi_read_u8(espi, SSPCR1);
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regval |= (SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
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ep93xx_spi_write_u8(espi, SSPCR1, regval);
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}
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static void ep93xx_spi_disable_interrupts(const struct ep93xx_spi *espi)
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{
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u8 regval;
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regval = ep93xx_spi_read_u8(espi, SSPCR1);
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regval &= ~(SSPCR1_RORIE | SSPCR1_TIE | SSPCR1_RIE);
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ep93xx_spi_write_u8(espi, SSPCR1, regval);
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}
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/**
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* ep93xx_spi_calc_divisors() - calculates SPI clock divisors
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* @espi: ep93xx SPI controller struct
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* @chip: divisors are calculated for this chip
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* @rate: desired SPI output clock rate
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*
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* Function calculates cpsr (clock pre-scaler) and scr divisors based on
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* given @rate and places them to @chip->div_cpsr and @chip->div_scr. If,
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* for some reason, divisors cannot be calculated nothing is stored and
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* %-EINVAL is returned.
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*/
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static int ep93xx_spi_calc_divisors(const struct ep93xx_spi *espi,
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struct ep93xx_spi_chip *chip,
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unsigned long rate)
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{
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unsigned long spi_clk_rate = clk_get_rate(espi->clk);
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int cpsr, scr;
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/*
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* Make sure that max value is between values supported by the
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* controller. Note that minimum value is already checked in
|
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* ep93xx_spi_transfer().
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*/
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rate = clamp(rate, espi->min_rate, espi->max_rate);
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/*
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* Calculate divisors so that we can get speed according the
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* following formula:
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* rate = spi_clock_rate / (cpsr * (1 + scr))
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*
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* cpsr must be even number and starts from 2, scr can be any number
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* between 0 and 255.
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*/
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for (cpsr = 2; cpsr <= 254; cpsr += 2) {
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for (scr = 0; scr <= 255; scr++) {
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if ((spi_clk_rate / (cpsr * (scr + 1))) <= rate) {
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chip->div_scr = (u8)scr;
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chip->div_cpsr = (u8)cpsr;
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return 0;
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}
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}
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}
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return -EINVAL;
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}
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static void ep93xx_spi_cs_control(struct spi_device *spi, bool control)
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{
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struct ep93xx_spi_chip *chip = spi_get_ctldata(spi);
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int value = (spi->mode & SPI_CS_HIGH) ? control : !control;
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if (chip->ops && chip->ops->cs_control)
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chip->ops->cs_control(spi, value);
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}
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/**
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* ep93xx_spi_setup() - setup an SPI device
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* @spi: SPI device to setup
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*
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* This function sets up SPI device mode, speed etc. Can be called multiple
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* times for a single device. Returns %0 in case of success, negative error in
|
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* case of failure. When this function returns success, the device is
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* deselected.
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*/
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static int ep93xx_spi_setup(struct spi_device *spi)
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{
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struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
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struct ep93xx_spi_chip *chip;
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if (spi->bits_per_word < 4 || spi->bits_per_word > 16) {
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dev_err(&espi->pdev->dev, "invalid bits per word %d\n",
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spi->bits_per_word);
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return -EINVAL;
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}
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chip = spi_get_ctldata(spi);
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if (!chip) {
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dev_dbg(&espi->pdev->dev, "initial setup for %s\n",
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spi->modalias);
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chip = kzalloc(sizeof(*chip), GFP_KERNEL);
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if (!chip)
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return -ENOMEM;
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chip->spi = spi;
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chip->ops = spi->controller_data;
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if (chip->ops && chip->ops->setup) {
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int ret = chip->ops->setup(spi);
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if (ret) {
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kfree(chip);
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return ret;
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}
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}
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|
||||
spi_set_ctldata(spi, chip);
|
||||
}
|
||||
|
||||
if (spi->max_speed_hz != chip->rate) {
|
||||
int err;
|
||||
|
||||
err = ep93xx_spi_calc_divisors(espi, chip, spi->max_speed_hz);
|
||||
if (err != 0) {
|
||||
spi_set_ctldata(spi, NULL);
|
||||
kfree(chip);
|
||||
return err;
|
||||
}
|
||||
chip->rate = spi->max_speed_hz;
|
||||
}
|
||||
|
||||
chip->dss = bits_per_word_to_dss(spi->bits_per_word);
|
||||
|
||||
ep93xx_spi_cs_control(spi, false);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* ep93xx_spi_transfer() - queue message to be transferred
|
||||
* @spi: target SPI device
|
||||
* @msg: message to be transferred
|
||||
*
|
||||
* This function is called by SPI device drivers when they are going to transfer
|
||||
* a new message. It simply puts the message in the queue and schedules
|
||||
* workqueue to perform the actual transfer later on.
|
||||
*
|
||||
* Returns %0 on success and negative error in case of failure.
|
||||
*/
|
||||
static int ep93xx_spi_transfer(struct spi_device *spi, struct spi_message *msg)
|
||||
{
|
||||
struct ep93xx_spi *espi = spi_master_get_devdata(spi->master);
|
||||
struct spi_transfer *t;
|
||||
unsigned long flags;
|
||||
|
||||
if (!msg || !msg->complete)
|
||||
return -EINVAL;
|
||||
|
||||
/* first validate each transfer */
|
||||
list_for_each_entry(t, &msg->transfers, transfer_list) {
|
||||
if (t->bits_per_word) {
|
||||
if (t->bits_per_word < 4 || t->bits_per_word > 16)
|
||||
return -EINVAL;
|
||||
}
|
||||
if (t->speed_hz && t->speed_hz < espi->min_rate)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Now that we own the message, let's initialize it so that it is
|
||||
* suitable for us. We use @msg->status to signal whether there was
|
||||
* error in transfer and @msg->state is used to hold pointer to the
|
||||
* current transfer (or %NULL if no active current transfer).
|
||||
*/
|
||||
msg->state = NULL;
|
||||
msg->status = 0;
|
||||
msg->actual_length = 0;
|
||||
|
||||
spin_lock_irqsave(&espi->lock, flags);
|
||||
if (!espi->running) {
|
||||
spin_unlock_irqrestore(&espi->lock, flags);
|
||||
return -ESHUTDOWN;
|
||||
}
|
||||
list_add_tail(&msg->queue, &espi->msg_queue);
|
||||
queue_work(espi->wq, &espi->msg_work);
|
||||
spin_unlock_irqrestore(&espi->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* ep93xx_spi_cleanup() - cleans up master controller specific state
|
||||
* @spi: SPI device to cleanup
|
||||
*
|
||||
* This function releases master controller specific state for given @spi
|
||||
* device.
|
||||
*/
|
||||
static void ep93xx_spi_cleanup(struct spi_device *spi)
|
||||
{
|
||||
struct ep93xx_spi_chip *chip;
|
||||
|
||||
chip = spi_get_ctldata(spi);
|
||||
if (chip) {
|
||||
if (chip->ops && chip->ops->cleanup)
|
||||
chip->ops->cleanup(spi);
|
||||
spi_set_ctldata(spi, NULL);
|
||||
kfree(chip);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* ep93xx_spi_chip_setup() - configures hardware according to given @chip
|
||||
* @espi: ep93xx SPI controller struct
|
||||
* @chip: chip specific settings
|
||||
*
|
||||
* This function sets up the actual hardware registers with settings given in
|
||||
* @chip. Note that no validation is done so make sure that callers validate
|
||||
* settings before calling this.
|
||||
*/
|
||||
static void ep93xx_spi_chip_setup(const struct ep93xx_spi *espi,
|
||||
const struct ep93xx_spi_chip *chip)
|
||||
{
|
||||
u16 cr0;
|
||||
|
||||
cr0 = chip->div_scr << SSPCR0_SCR_SHIFT;
|
||||
cr0 |= (chip->spi->mode & (SPI_CPHA|SPI_CPOL)) << SSPCR0_MODE_SHIFT;
|
||||
cr0 |= chip->dss;
|
||||
|
||||
dev_dbg(&espi->pdev->dev, "setup: mode %d, cpsr %d, scr %d, dss %d\n",
|
||||
chip->spi->mode, chip->div_cpsr, chip->div_scr, chip->dss);
|
||||
dev_dbg(&espi->pdev->dev, "setup: cr0 %#x", cr0);
|
||||
|
||||
ep93xx_spi_write_u8(espi, SSPCPSR, chip->div_cpsr);
|
||||
ep93xx_spi_write_u16(espi, SSPCR0, cr0);
|
||||
}
|
||||
|
||||
static inline int bits_per_word(const struct ep93xx_spi *espi)
|
||||
{
|
||||
struct spi_message *msg = espi->current_msg;
|
||||
struct spi_transfer *t = msg->state;
|
||||
|
||||
return t->bits_per_word ? t->bits_per_word : msg->spi->bits_per_word;
|
||||
}
|
||||
|
||||
static void ep93xx_do_write(struct ep93xx_spi *espi, struct spi_transfer *t)
|
||||
{
|
||||
if (bits_per_word(espi) > 8) {
|
||||
u16 tx_val = 0;
|
||||
|
||||
if (t->tx_buf)
|
||||
tx_val = ((u16 *)t->tx_buf)[espi->tx];
|
||||
ep93xx_spi_write_u16(espi, SSPDR, tx_val);
|
||||
espi->tx += sizeof(tx_val);
|
||||
} else {
|
||||
u8 tx_val = 0;
|
||||
|
||||
if (t->tx_buf)
|
||||
tx_val = ((u8 *)t->tx_buf)[espi->tx];
|
||||
ep93xx_spi_write_u8(espi, SSPDR, tx_val);
|
||||
espi->tx += sizeof(tx_val);
|
||||
}
|
||||
}
|
||||
|
||||
static void ep93xx_do_read(struct ep93xx_spi *espi, struct spi_transfer *t)
|
||||
{
|
||||
if (bits_per_word(espi) > 8) {
|
||||
u16 rx_val;
|
||||
|
||||
rx_val = ep93xx_spi_read_u16(espi, SSPDR);
|
||||
if (t->rx_buf)
|
||||
((u16 *)t->rx_buf)[espi->rx] = rx_val;
|
||||
espi->rx += sizeof(rx_val);
|
||||
} else {
|
||||
u8 rx_val;
|
||||
|
||||
rx_val = ep93xx_spi_read_u8(espi, SSPDR);
|
||||
if (t->rx_buf)
|
||||
((u8 *)t->rx_buf)[espi->rx] = rx_val;
|
||||
espi->rx += sizeof(rx_val);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* ep93xx_spi_read_write() - perform next RX/TX transfer
|
||||
* @espi: ep93xx SPI controller struct
|
||||
*
|
||||
* This function transfers next bytes (or half-words) to/from RX/TX FIFOs. If
|
||||
* called several times, the whole transfer will be completed. Returns
|
||||
* %-EINPROGRESS when current transfer was not yet completed otherwise %0.
|
||||
*
|
||||
* When this function is finished, RX FIFO should be empty and TX FIFO should be
|
||||
* full.
|
||||
*/
|
||||
static int ep93xx_spi_read_write(struct ep93xx_spi *espi)
|
||||
{
|
||||
struct spi_message *msg = espi->current_msg;
|
||||
struct spi_transfer *t = msg->state;
|
||||
|
||||
/* read as long as RX FIFO has frames in it */
|
||||
while ((ep93xx_spi_read_u8(espi, SSPSR) & SSPSR_RNE)) {
|
||||
ep93xx_do_read(espi, t);
|
||||
espi->fifo_level--;
|
||||
}
|
||||
|
||||
/* write as long as TX FIFO has room */
|
||||
while (espi->fifo_level < SPI_FIFO_SIZE && espi->tx < t->len) {
|
||||
ep93xx_do_write(espi, t);
|
||||
espi->fifo_level++;
|
||||
}
|
||||
|
||||
if (espi->rx == t->len) {
|
||||
msg->actual_length += t->len;
|
||||
return 0;
|
||||
}
|
||||
|
||||
return -EINPROGRESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* ep93xx_spi_process_transfer() - processes one SPI transfer
|
||||
* @espi: ep93xx SPI controller struct
|
||||
* @msg: current message
|
||||
* @t: transfer to process
|
||||
*
|
||||
* This function processes one SPI transfer given in @t. Function waits until
|
||||
* transfer is complete (may sleep) and updates @msg->status based on whether
|
||||
* transfer was succesfully processed or not.
|
||||
*/
|
||||
static void ep93xx_spi_process_transfer(struct ep93xx_spi *espi,
|
||||
struct spi_message *msg,
|
||||
struct spi_transfer *t)
|
||||
{
|
||||
struct ep93xx_spi_chip *chip = spi_get_ctldata(msg->spi);
|
||||
|
||||
msg->state = t;
|
||||
|
||||
/*
|
||||
* Handle any transfer specific settings if needed. We use
|
||||
* temporary chip settings here and restore original later when
|
||||
* the transfer is finished.
|
||||
*/
|
||||
if (t->speed_hz || t->bits_per_word) {
|
||||
struct ep93xx_spi_chip tmp_chip = *chip;
|
||||
|
||||
if (t->speed_hz) {
|
||||
int err;
|
||||
|
||||
err = ep93xx_spi_calc_divisors(espi, &tmp_chip,
|
||||
t->speed_hz);
|
||||
if (err) {
|
||||
dev_err(&espi->pdev->dev,
|
||||
"failed to adjust speed\n");
|
||||
msg->status = err;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if (t->bits_per_word)
|
||||
tmp_chip.dss = bits_per_word_to_dss(t->bits_per_word);
|
||||
|
||||
/*
|
||||
* Set up temporary new hw settings for this transfer.
|
||||
*/
|
||||
ep93xx_spi_chip_setup(espi, &tmp_chip);
|
||||
}
|
||||
|
||||
espi->rx = 0;
|
||||
espi->tx = 0;
|
||||
|
||||
/*
|
||||
* Now everything is set up for the current transfer. We prime the TX
|
||||
* FIFO, enable interrupts, and wait for the transfer to complete.
|
||||
*/
|
||||
if (ep93xx_spi_read_write(espi)) {
|
||||
ep93xx_spi_enable_interrupts(espi);
|
||||
wait_for_completion(&espi->wait);
|
||||
}
|
||||
|
||||
/*
|
||||
* In case of error during transmit, we bail out from processing
|
||||
* the message.
|
||||
*/
|
||||
if (msg->status)
|
||||
return;
|
||||
|
||||
/*
|
||||
* After this transfer is finished, perform any possible
|
||||
* post-transfer actions requested by the protocol driver.
|
||||
*/
|
||||
if (t->delay_usecs) {
|
||||
set_current_state(TASK_UNINTERRUPTIBLE);
|
||||
schedule_timeout(usecs_to_jiffies(t->delay_usecs));
|
||||
}
|
||||
if (t->cs_change) {
|
||||
if (!list_is_last(&t->transfer_list, &msg->transfers)) {
|
||||
/*
|
||||
* In case protocol driver is asking us to drop the
|
||||
* chipselect briefly, we let the scheduler to handle
|
||||
* any "delay" here.
|
||||
*/
|
||||
ep93xx_spi_cs_control(msg->spi, false);
|
||||
cond_resched();
|
||||
ep93xx_spi_cs_control(msg->spi, true);
|
||||
}
|
||||
}
|
||||
|
||||
if (t->speed_hz || t->bits_per_word)
|
||||
ep93xx_spi_chip_setup(espi, chip);
|
||||
}
|
||||
|
||||
/*
|
||||
* ep93xx_spi_process_message() - process one SPI message
|
||||
* @espi: ep93xx SPI controller struct
|
||||
* @msg: message to process
|
||||
*
|
||||
* This function processes a single SPI message. We go through all transfers in
|
||||
* the message and pass them to ep93xx_spi_process_transfer(). Chipselect is
|
||||
* asserted during the whole message (unless per transfer cs_change is set).
|
||||
*
|
||||
* @msg->status contains %0 in case of success or negative error code in case of
|
||||
* failure.
|
||||
*/
|
||||
static void ep93xx_spi_process_message(struct ep93xx_spi *espi,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
unsigned long timeout;
|
||||
struct spi_transfer *t;
|
||||
int err;
|
||||
|
||||
/*
|
||||
* Enable the SPI controller and its clock.
|
||||
*/
|
||||
err = ep93xx_spi_enable(espi);
|
||||
if (err) {
|
||||
dev_err(&espi->pdev->dev, "failed to enable SPI controller\n");
|
||||
msg->status = err;
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* Just to be sure: flush any data from RX FIFO.
|
||||
*/
|
||||
timeout = jiffies + msecs_to_jiffies(SPI_TIMEOUT);
|
||||
while (ep93xx_spi_read_u16(espi, SSPSR) & SSPSR_RNE) {
|
||||
if (time_after(jiffies, timeout)) {
|
||||
dev_warn(&espi->pdev->dev,
|
||||
"timeout while flushing RX FIFO\n");
|
||||
msg->status = -ETIMEDOUT;
|
||||
return;
|
||||
}
|
||||
ep93xx_spi_read_u16(espi, SSPDR);
|
||||
}
|
||||
|
||||
/*
|
||||
* We explicitly handle FIFO level. This way we don't have to check TX
|
||||
* FIFO status using %SSPSR_TNF bit which may cause RX FIFO overruns.
|
||||
*/
|
||||
espi->fifo_level = 0;
|
||||
|
||||
/*
|
||||
* Update SPI controller registers according to spi device and assert
|
||||
* the chipselect.
|
||||
*/
|
||||
ep93xx_spi_chip_setup(espi, spi_get_ctldata(msg->spi));
|
||||
ep93xx_spi_cs_control(msg->spi, true);
|
||||
|
||||
list_for_each_entry(t, &msg->transfers, transfer_list) {
|
||||
ep93xx_spi_process_transfer(espi, msg, t);
|
||||
if (msg->status)
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Now the whole message is transferred (or failed for some reason). We
|
||||
* deselect the device and disable the SPI controller.
|
||||
*/
|
||||
ep93xx_spi_cs_control(msg->spi, false);
|
||||
ep93xx_spi_disable(espi);
|
||||
}
|
||||
|
||||
#define work_to_espi(work) (container_of((work), struct ep93xx_spi, msg_work))
|
||||
|
||||
/**
|
||||
* ep93xx_spi_work() - EP93xx SPI workqueue worker function
|
||||
* @work: work struct
|
||||
*
|
||||
* Workqueue worker function. This function is called when there are new
|
||||
* SPI messages to be processed. Message is taken out from the queue and then
|
||||
* passed to ep93xx_spi_process_message().
|
||||
*
|
||||
* After message is transferred, protocol driver is notified by calling
|
||||
* @msg->complete(). In case of error, @msg->status is set to negative error
|
||||
* number, otherwise it contains zero (and @msg->actual_length is updated).
|
||||
*/
|
||||
static void ep93xx_spi_work(struct work_struct *work)
|
||||
{
|
||||
struct ep93xx_spi *espi = work_to_espi(work);
|
||||
struct spi_message *msg;
|
||||
|
||||
spin_lock_irq(&espi->lock);
|
||||
if (!espi->running || espi->current_msg ||
|
||||
list_empty(&espi->msg_queue)) {
|
||||
spin_unlock_irq(&espi->lock);
|
||||
return;
|
||||
}
|
||||
msg = list_first_entry(&espi->msg_queue, struct spi_message, queue);
|
||||
list_del_init(&msg->queue);
|
||||
espi->current_msg = msg;
|
||||
spin_unlock_irq(&espi->lock);
|
||||
|
||||
ep93xx_spi_process_message(espi, msg);
|
||||
|
||||
/*
|
||||
* Update the current message and re-schedule ourselves if there are
|
||||
* more messages in the queue.
|
||||
*/
|
||||
spin_lock_irq(&espi->lock);
|
||||
espi->current_msg = NULL;
|
||||
if (espi->running && !list_empty(&espi->msg_queue))
|
||||
queue_work(espi->wq, &espi->msg_work);
|
||||
spin_unlock_irq(&espi->lock);
|
||||
|
||||
/* notify the protocol driver that we are done with this message */
|
||||
msg->complete(msg->context);
|
||||
}
|
||||
|
||||
static irqreturn_t ep93xx_spi_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct ep93xx_spi *espi = dev_id;
|
||||
u8 irq_status = ep93xx_spi_read_u8(espi, SSPIIR);
|
||||
|
||||
/*
|
||||
* If we got ROR (receive overrun) interrupt we know that something is
|
||||
* wrong. Just abort the message.
|
||||
*/
|
||||
if (unlikely(irq_status & SSPIIR_RORIS)) {
|
||||
/* clear the overrun interrupt */
|
||||
ep93xx_spi_write_u8(espi, SSPICR, 0);
|
||||
dev_warn(&espi->pdev->dev,
|
||||
"receive overrun, aborting the message\n");
|
||||
espi->current_msg->status = -EIO;
|
||||
} else {
|
||||
/*
|
||||
* Interrupt is either RX (RIS) or TX (TIS). For both cases we
|
||||
* simply execute next data transfer.
|
||||
*/
|
||||
if (ep93xx_spi_read_write(espi)) {
|
||||
/*
|
||||
* In normal case, there still is some processing left
|
||||
* for current transfer. Let's wait for the next
|
||||
* interrupt then.
|
||||
*/
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Current transfer is finished, either with error or with success. In
|
||||
* any case we disable interrupts and notify the worker to handle
|
||||
* any post-processing of the message.
|
||||
*/
|
||||
ep93xx_spi_disable_interrupts(espi);
|
||||
complete(&espi->wait);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int __init ep93xx_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
struct ep93xx_spi_info *info;
|
||||
struct ep93xx_spi *espi;
|
||||
struct resource *res;
|
||||
int error;
|
||||
|
||||
info = pdev->dev.platform_data;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(*espi));
|
||||
if (!master) {
|
||||
dev_err(&pdev->dev, "failed to allocate spi master\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
master->setup = ep93xx_spi_setup;
|
||||
master->transfer = ep93xx_spi_transfer;
|
||||
master->cleanup = ep93xx_spi_cleanup;
|
||||
master->bus_num = pdev->id;
|
||||
master->num_chipselect = info->num_chipselect;
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
|
||||
espi = spi_master_get_devdata(master);
|
||||
|
||||
espi->clk = clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(espi->clk)) {
|
||||
dev_err(&pdev->dev, "unable to get spi clock\n");
|
||||
error = PTR_ERR(espi->clk);
|
||||
goto fail_release_master;
|
||||
}
|
||||
|
||||
spin_lock_init(&espi->lock);
|
||||
init_completion(&espi->wait);
|
||||
|
||||
/*
|
||||
* Calculate maximum and minimum supported clock rates
|
||||
* for the controller.
|
||||
*/
|
||||
espi->max_rate = clk_get_rate(espi->clk) / 2;
|
||||
espi->min_rate = clk_get_rate(espi->clk) / (254 * 256);
|
||||
espi->pdev = pdev;
|
||||
|
||||
espi->irq = platform_get_irq(pdev, 0);
|
||||
if (espi->irq < 0) {
|
||||
error = -EBUSY;
|
||||
dev_err(&pdev->dev, "failed to get irq resources\n");
|
||||
goto fail_put_clock;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "unable to get iomem resource\n");
|
||||
error = -ENODEV;
|
||||
goto fail_put_clock;
|
||||
}
|
||||
|
||||
res = request_mem_region(res->start, resource_size(res), pdev->name);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "unable to request iomem resources\n");
|
||||
error = -EBUSY;
|
||||
goto fail_put_clock;
|
||||
}
|
||||
|
||||
espi->regs_base = ioremap(res->start, resource_size(res));
|
||||
if (!espi->regs_base) {
|
||||
dev_err(&pdev->dev, "failed to map resources\n");
|
||||
error = -ENODEV;
|
||||
goto fail_free_mem;
|
||||
}
|
||||
|
||||
error = request_irq(espi->irq, ep93xx_spi_interrupt, 0,
|
||||
"ep93xx-spi", espi);
|
||||
if (error) {
|
||||
dev_err(&pdev->dev, "failed to request irq\n");
|
||||
goto fail_unmap_regs;
|
||||
}
|
||||
|
||||
espi->wq = create_singlethread_workqueue("ep93xx_spid");
|
||||
if (!espi->wq) {
|
||||
dev_err(&pdev->dev, "unable to create workqueue\n");
|
||||
goto fail_free_irq;
|
||||
}
|
||||
INIT_WORK(&espi->msg_work, ep93xx_spi_work);
|
||||
INIT_LIST_HEAD(&espi->msg_queue);
|
||||
espi->running = true;
|
||||
|
||||
/* make sure that the hardware is disabled */
|
||||
ep93xx_spi_write_u8(espi, SSPCR1, 0);
|
||||
|
||||
error = spi_register_master(master);
|
||||
if (error) {
|
||||
dev_err(&pdev->dev, "failed to register SPI master\n");
|
||||
goto fail_free_queue;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "EP93xx SPI Controller at 0x%08lx irq %d\n",
|
||||
(unsigned long)res->start, espi->irq);
|
||||
|
||||
return 0;
|
||||
|
||||
fail_free_queue:
|
||||
destroy_workqueue(espi->wq);
|
||||
fail_free_irq:
|
||||
free_irq(espi->irq, espi);
|
||||
fail_unmap_regs:
|
||||
iounmap(espi->regs_base);
|
||||
fail_free_mem:
|
||||
release_mem_region(res->start, resource_size(res));
|
||||
fail_put_clock:
|
||||
clk_put(espi->clk);
|
||||
fail_release_master:
|
||||
spi_master_put(master);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
return error;
|
||||
}
|
||||
|
||||
static int __exit ep93xx_spi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct ep93xx_spi *espi = spi_master_get_devdata(master);
|
||||
struct resource *res;
|
||||
|
||||
spin_lock_irq(&espi->lock);
|
||||
espi->running = false;
|
||||
spin_unlock_irq(&espi->lock);
|
||||
|
||||
destroy_workqueue(espi->wq);
|
||||
|
||||
/*
|
||||
* Complete remaining messages with %-ESHUTDOWN status.
|
||||
*/
|
||||
spin_lock_irq(&espi->lock);
|
||||
while (!list_empty(&espi->msg_queue)) {
|
||||
struct spi_message *msg;
|
||||
|
||||
msg = list_first_entry(&espi->msg_queue,
|
||||
struct spi_message, queue);
|
||||
list_del_init(&msg->queue);
|
||||
msg->status = -ESHUTDOWN;
|
||||
spin_unlock_irq(&espi->lock);
|
||||
msg->complete(msg->context);
|
||||
spin_lock_irq(&espi->lock);
|
||||
}
|
||||
spin_unlock_irq(&espi->lock);
|
||||
|
||||
free_irq(espi->irq, espi);
|
||||
iounmap(espi->regs_base);
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
release_mem_region(res->start, resource_size(res));
|
||||
clk_put(espi->clk);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
|
||||
spi_unregister_master(master);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver ep93xx_spi_driver = {
|
||||
.driver = {
|
||||
.name = "ep93xx-spi",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
.remove = __exit_p(ep93xx_spi_remove),
|
||||
};
|
||||
|
||||
static int __init ep93xx_spi_init(void)
|
||||
{
|
||||
return platform_driver_probe(&ep93xx_spi_driver, ep93xx_spi_probe);
|
||||
}
|
||||
module_init(ep93xx_spi_init);
|
||||
|
||||
static void __exit ep93xx_spi_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&ep93xx_spi_driver);
|
||||
}
|
||||
module_exit(ep93xx_spi_exit);
|
||||
|
||||
MODULE_DESCRIPTION("EP93xx SPI Controller driver");
|
||||
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS("platform:ep93xx-spi");
|
||||
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