Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
drivers/net/ethernet/freescale/fec.h7b15515fc1("Revert "fec: Restart PPS after link state change"")40c79ce13b("net: fec: add stop mode support for imx8 platform") https://lore.kernel.org/all/20220921105337.62b41047@canb.auug.org.au/ drivers/pinctrl/pinctrl-ocelot.cc297561bc9("pinctrl: ocelot: Fix interrupt controller")181f604b33("pinctrl: ocelot: add ability to be used in a non-mmio configuration") https://lore.kernel.org/all/20220921110032.7cd28114@canb.auug.org.au/ tools/testing/selftests/drivers/net/bonding/Makefilebbb774d921("net: Add tests for bonding and team address list management")152e8ec776("selftests/bonding: add a test for bonding lladdr target") https://lore.kernel.org/all/20220921110437.5b7dbd82@canb.auug.org.au/ drivers/net/can/usb/gs_usb.c5440428b3d("can: gs_usb: gs_can_open(): fix race dev->can.state condition")45dfa45f52("can: gs_usb: add RX and TX hardware timestamp support") https://lore.kernel.org/all/84f45a7d-92b6-4dc5-d7a1-072152fab6ff@tessares.net/ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski
Коммит
0140a7168f
1
.mailmap
1
.mailmap
|
|
@ -315,6 +315,7 @@ Morten Welinder <welinder@troll.com>
|
|||
Mythri P K <mythripk@ti.com>
|
||||
Nadia Yvette Chambers <nyc@holomorphy.com> William Lee Irwin III <wli@holomorphy.com>
|
||||
Nathan Chancellor <nathan@kernel.org> <natechancellor@gmail.com>
|
||||
Neil Armstrong <neil.armstrong@linaro.org> <narmstrong@baylibre.com>
|
||||
Nguyen Anh Quynh <aquynh@gmail.com>
|
||||
Nicholas Piggin <npiggin@gmail.com> <npiggen@suse.de>
|
||||
Nicholas Piggin <npiggin@gmail.com> <npiggin@kernel.dk>
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic Meson Firmware registers Interface
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |
|
||||
The Meson SoCs have a register bank with status and data shared with the
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/sound/name-prefix.yaml#
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic Meson Display Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |
|
||||
The Amlogic Meson Display controller is composed of several components
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ title: Analogix ANX7814 SlimPort (Full-HD Transmitter)
|
|||
|
||||
maintainers:
|
||||
- Andrzej Hajda <andrzej.hajda@intel.com>
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Robert Foss <robert.foss@linaro.org>
|
||||
|
||||
properties:
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ title: ITE it66121 HDMI bridge Device Tree Bindings
|
|||
|
||||
maintainers:
|
||||
- Phong LE <ple@baylibre.com>
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |
|
||||
The IT66121 is a high-performance and low-power single channel HDMI
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Solomon Goldentek Display GKTW70SDAE4SE 7" WVGA LVDS Display Panel
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Thierry Reding <thierry.reding@gmail.com>
|
||||
|
||||
allOf:
|
||||
|
|
|
|||
|
|
@ -48,7 +48,6 @@ required:
|
|||
- compatible
|
||||
- reg
|
||||
- reg-names
|
||||
- intel,vm-map
|
||||
- clocks
|
||||
- resets
|
||||
- "#thermal-sensor-cells"
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic Meson I2C Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Beniamino Galvani <b.galvani@gmail.com>
|
||||
|
||||
allOf:
|
||||
|
|
|
|||
|
|
@ -60,6 +60,9 @@ properties:
|
|||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Generic i.MX bus frequency device
|
||||
|
||||
maintainers:
|
||||
- Leonard Crestez <leonard.crestez@nxp.com>
|
||||
- Peng Fan <peng.fan@nxp.com>
|
||||
|
||||
description: |
|
||||
The i.MX SoC family has multiple buses for which clock frequency (and
|
||||
|
|
|
|||
|
|
@ -96,7 +96,7 @@ properties:
|
|||
Documentation/devicetree/bindings/arm/cpus.yaml).
|
||||
|
||||
required:
|
||||
- fiq-index
|
||||
- apple,fiq-index
|
||||
- cpus
|
||||
|
||||
required:
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic Meson Message-Handling-Unit Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |
|
||||
The Amlogic's Meson SoCs Message-Handling-Unit (MHU) is a mailbox controller
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic GE2D Acceleration Unit
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic Video Decoder
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Maxime Jourdan <mjourdan@baylibre.com>
|
||||
|
||||
description: |
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic Meson AO-CEC Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |
|
||||
The Amlogic Meson AO-CEC module is present is Amlogic SoCs and its purpose is
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Khadas on-board Microcontroller Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |
|
||||
Khadas embeds a microcontroller on their VIM and Edge boards adding some
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic Meson DWMAC Ethernet controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||
|
||||
# We need a select here so we don't match all nodes with 'snps,dwmac'
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic AXG MIPI D-PHY
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic G12A USB2 PHY
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic G12A USB3 + PCIE Combo PHY
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@ title: Qualcomm Technologies, Inc. Low Power Audio SubSystem (LPASS)
|
|||
Low Power Island (LPI) TLMM block
|
||||
|
||||
maintainers:
|
||||
- Srinivasa Rao Mandadapu <srivasam@codeaurora.org>
|
||||
- Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
|
||||
description: |
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Qualcomm Technologies, Inc. SC7280 TLMM block
|
||||
|
||||
maintainers:
|
||||
- Rajendra Nayak <rnayak@codeaurora.org>
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description: |
|
||||
This binding describes the Top Level Mode Multiplexer block found in the
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Amlogic Meson Everything-Else Power Domains
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |+
|
||||
The Everything-Else Power Domains node should be the child of a syscon
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
|
|||
title: Qualcomm RPM/RPMh Power domains
|
||||
|
||||
maintainers:
|
||||
- Rajendra Nayak <rnayak@codeaurora.org>
|
||||
- Bjorn Andersson <andersson@kernel.org>
|
||||
|
||||
description:
|
||||
For RPM/RPMh Power domains, we communicate a performance state to RPM/RPMh
|
||||
|
|
|
|||
|
|
@ -35,6 +35,7 @@ patternProperties:
|
|||
description: List of regulators and its properties
|
||||
type: object
|
||||
$ref: regulator.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
properties:
|
||||
qcom,ocp-max-retries:
|
||||
|
|
@ -100,8 +101,6 @@ patternProperties:
|
|||
SAW controlled gang leader. Will be configured as SAW regulator.
|
||||
type: boolean
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic Meson SoC Reset Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -17,9 +17,6 @@ description:
|
|||
acts as directory-based coherency manager.
|
||||
All the properties in ePAPR/DeviceTree specification applies for this platform.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/cache-controller.yaml#
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
|
|
@ -33,11 +30,16 @@ select:
|
|||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- sifive,fu540-c000-ccache
|
||||
- sifive,fu740-c000-ccache
|
||||
- const: cache
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- sifive,fu540-c000-ccache
|
||||
- sifive,fu740-c000-ccache
|
||||
- const: cache
|
||||
- items:
|
||||
- const: microchip,mpfs-ccache
|
||||
- const: sifive,fu540-c000-ccache
|
||||
- const: cache
|
||||
|
||||
cache-block-size:
|
||||
const: 64
|
||||
|
|
@ -72,29 +74,46 @@ properties:
|
|||
The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
|
||||
The reserved memory node should be defined as per the bindings in reserved-memory.txt.
|
||||
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: sifive,fu540-c000-ccache
|
||||
allOf:
|
||||
- $ref: /schemas/cache-controller.yaml#
|
||||
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
description: |
|
||||
Must contain entries for DirError, DataError and DataFail signals.
|
||||
maxItems: 3
|
||||
cache-sets:
|
||||
const: 1024
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- sifive,fu740-c000-ccache
|
||||
- microchip,mpfs-ccache
|
||||
|
||||
else:
|
||||
properties:
|
||||
interrupts:
|
||||
description: |
|
||||
Must contain entries for DirError, DataError, DataFail, DirFail signals.
|
||||
minItems: 4
|
||||
cache-sets:
|
||||
const: 2048
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
description: |
|
||||
Must contain entries for DirError, DataError, DataFail, DirFail signals.
|
||||
minItems: 4
|
||||
|
||||
else:
|
||||
properties:
|
||||
interrupts:
|
||||
description: |
|
||||
Must contain entries for DirError, DataError and DataFail signals.
|
||||
maxItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: sifive,fu740-c000-ccache
|
||||
|
||||
then:
|
||||
properties:
|
||||
cache-sets:
|
||||
const: 2048
|
||||
|
||||
else:
|
||||
properties:
|
||||
cache-sets:
|
||||
const: 1024
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic Meson Random number generator
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic Meson SoC UART Serial Interface
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |
|
||||
The Amlogic Meson SoC UART Serial Interface is present on a large range
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic Canvas Video Lookup Table
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
- Maxime Jourdan <mjourdan@baylibre.com>
|
||||
|
||||
description: |
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic Meson SPI Communication Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: "spi-controller.yaml#"
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic Meson SPI Flash Controller
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: "spi-controller.yaml#"
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
description: |
|
||||
The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ $schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
|||
title: Meson GXBB SoCs Watchdog timer
|
||||
|
||||
maintainers:
|
||||
- Neil Armstrong <narmstrong@baylibre.com>
|
||||
- Neil Armstrong <neil.armstrong@linaro.org>
|
||||
|
||||
allOf:
|
||||
- $ref: watchdog.yaml#
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ correct address for this module, you could get in big trouble (read:
|
|||
crashes, data corruption, etc.). Try this only as a last resort (try BIOS
|
||||
updates first, for example), and backup first! An even more dangerous
|
||||
option is 'force_addr=<IOPORT>'. This will not only enable the PIIX4 like
|
||||
'force' foes, but it will also set a new base I/O port address. The SMBus
|
||||
'force' does, but it will also set a new base I/O port address. The SMBus
|
||||
parts of the PIIX4 needs a range of 8 of these addresses to function
|
||||
correctly. If these addresses are already reserved by some other device,
|
||||
you will get into big trouble! DON'T USE THIS IF YOU ARE NOT VERY SURE
|
||||
|
|
@ -86,15 +86,15 @@ If you own Force CPCI735 motherboard or other OSB4 based systems you may need
|
|||
to change the SMBus Interrupt Select register so the SMBus controller uses
|
||||
the SMI mode.
|
||||
|
||||
1) Use lspci command and locate the PCI device with the SMBus controller:
|
||||
1) Use ``lspci`` command and locate the PCI device with the SMBus controller:
|
||||
00:0f.0 ISA bridge: ServerWorks OSB4 South Bridge (rev 4f)
|
||||
The line may vary for different chipsets. Please consult the driver source
|
||||
for all possible PCI ids (and lspci -n to match them). Lets assume the
|
||||
for all possible PCI ids (and ``lspci -n`` to match them). Let's assume the
|
||||
device is located at 00:0f.0.
|
||||
2) Now you just need to change the value in 0xD2 register. Get it first with
|
||||
command: lspci -xxx -s 00:0f.0
|
||||
command: ``lspci -xxx -s 00:0f.0``
|
||||
If the value is 0x3 then you need to change it to 0x1:
|
||||
setpci -s 00:0f.0 d2.b=1
|
||||
``setpci -s 00:0f.0 d2.b=1``
|
||||
|
||||
Please note that you don't need to do that in all cases, just when the SMBus is
|
||||
not working properly.
|
||||
|
|
@ -109,6 +109,3 @@ which can easily get corrupted due to a state machine bug. These are mostly
|
|||
Thinkpad laptops, but desktop systems may also be affected. We have no list
|
||||
of all affected systems, so the only safe solution was to prevent access to
|
||||
the SMBus on all IBM systems (detected using DMI data.)
|
||||
|
||||
For additional information, read:
|
||||
http://www.lm-sensors.org/browser/lm-sensors/trunk/README
|
||||
|
|
|
|||
|
|
@ -5,6 +5,8 @@ I2C muxes and complex topologies
|
|||
There are a couple of reasons for building more complex I2C topologies
|
||||
than a straight-forward I2C bus with one adapter and one or more devices.
|
||||
|
||||
Some example use cases are:
|
||||
|
||||
1. A mux may be needed on the bus to prevent address collisions.
|
||||
|
||||
2. The bus may be accessible from some external bus master, and arbitration
|
||||
|
|
@ -14,10 +16,10 @@ than a straight-forward I2C bus with one adapter and one or more devices.
|
|||
from the I2C bus, at least most of the time, and sits behind a gate
|
||||
that has to be operated before the device can be accessed.
|
||||
|
||||
Etc
|
||||
===
|
||||
Several types of hardware components such as I2C muxes, I2C gates and I2C
|
||||
arbitrators allow to handle such needs.
|
||||
|
||||
These constructs are represented as I2C adapter trees by Linux, where
|
||||
These components are represented as I2C adapter trees by Linux, where
|
||||
each adapter has a parent adapter (except the root adapter) and zero or
|
||||
more child adapters. The root adapter is the actual adapter that issues
|
||||
I2C transfers, and all adapters with a parent are part of an "i2c-mux"
|
||||
|
|
@ -35,46 +37,7 @@ Locking
|
|||
=======
|
||||
|
||||
There are two variants of locking available to I2C muxes, they can be
|
||||
mux-locked or parent-locked muxes. As is evident from below, it can be
|
||||
useful to know if a mux is mux-locked or if it is parent-locked. The
|
||||
following list was correct at the time of writing:
|
||||
|
||||
In drivers/i2c/muxes/:
|
||||
|
||||
====================== =============================================
|
||||
i2c-arb-gpio-challenge Parent-locked
|
||||
i2c-mux-gpio Normally parent-locked, mux-locked iff
|
||||
all involved gpio pins are controlled by the
|
||||
same I2C root adapter that they mux.
|
||||
i2c-mux-gpmux Normally parent-locked, mux-locked iff
|
||||
specified in device-tree.
|
||||
i2c-mux-ltc4306 Mux-locked
|
||||
i2c-mux-mlxcpld Parent-locked
|
||||
i2c-mux-pca9541 Parent-locked
|
||||
i2c-mux-pca954x Parent-locked
|
||||
i2c-mux-pinctrl Normally parent-locked, mux-locked iff
|
||||
all involved pinctrl devices are controlled
|
||||
by the same I2C root adapter that they mux.
|
||||
i2c-mux-reg Parent-locked
|
||||
====================== =============================================
|
||||
|
||||
In drivers/iio/:
|
||||
|
||||
====================== =============================================
|
||||
gyro/mpu3050 Mux-locked
|
||||
imu/inv_mpu6050/ Mux-locked
|
||||
====================== =============================================
|
||||
|
||||
In drivers/media/:
|
||||
|
||||
======================= =============================================
|
||||
dvb-frontends/lgdt3306a Mux-locked
|
||||
dvb-frontends/m88ds3103 Parent-locked
|
||||
dvb-frontends/rtl2830 Parent-locked
|
||||
dvb-frontends/rtl2832 Mux-locked
|
||||
dvb-frontends/si2168 Mux-locked
|
||||
usb/cx231xx/ Parent-locked
|
||||
======================= =============================================
|
||||
mux-locked or parent-locked muxes.
|
||||
|
||||
|
||||
Mux-locked muxes
|
||||
|
|
@ -89,40 +52,8 @@ full transaction, unrelated I2C transfers may interleave the different
|
|||
stages of the transaction. This has the benefit that the mux driver
|
||||
may be easier and cleaner to implement, but it has some caveats.
|
||||
|
||||
==== =====================================================================
|
||||
ML1. If you build a topology with a mux-locked mux being the parent
|
||||
of a parent-locked mux, this might break the expectation from the
|
||||
parent-locked mux that the root adapter is locked during the
|
||||
transaction.
|
||||
|
||||
ML2. It is not safe to build arbitrary topologies with two (or more)
|
||||
mux-locked muxes that are not siblings, when there are address
|
||||
collisions between the devices on the child adapters of these
|
||||
non-sibling muxes.
|
||||
|
||||
I.e. the select-transfer-deselect transaction targeting e.g. device
|
||||
address 0x42 behind mux-one may be interleaved with a similar
|
||||
operation targeting device address 0x42 behind mux-two. The
|
||||
intension with such a topology would in this hypothetical example
|
||||
be that mux-one and mux-two should not be selected simultaneously,
|
||||
but mux-locked muxes do not guarantee that in all topologies.
|
||||
|
||||
ML3. A mux-locked mux cannot be used by a driver for auto-closing
|
||||
gates/muxes, i.e. something that closes automatically after a given
|
||||
number (one, in most cases) of I2C transfers. Unrelated I2C transfers
|
||||
may creep in and close prematurely.
|
||||
|
||||
ML4. If any non-I2C operation in the mux driver changes the I2C mux state,
|
||||
the driver has to lock the root adapter during that operation.
|
||||
Otherwise garbage may appear on the bus as seen from devices
|
||||
behind the mux, when an unrelated I2C transfer is in flight during
|
||||
the non-I2C mux-changing operation.
|
||||
==== =====================================================================
|
||||
|
||||
|
||||
Mux-locked Example
|
||||
------------------
|
||||
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
|
|
@ -153,6 +84,43 @@ This means that accesses to D2 are lockout out for the full duration
|
|||
of the entire operation. But accesses to D3 are possibly interleaved
|
||||
at any point.
|
||||
|
||||
Mux-locked caveats
|
||||
~~~~~~~~~~~~~~~~~~
|
||||
|
||||
When using a mux-locked mux, be aware of the following restrictions:
|
||||
|
||||
[ML1]
|
||||
If you build a topology with a mux-locked mux being the parent
|
||||
of a parent-locked mux, this might break the expectation from the
|
||||
parent-locked mux that the root adapter is locked during the
|
||||
transaction.
|
||||
|
||||
[ML2]
|
||||
It is not safe to build arbitrary topologies with two (or more)
|
||||
mux-locked muxes that are not siblings, when there are address
|
||||
collisions between the devices on the child adapters of these
|
||||
non-sibling muxes.
|
||||
|
||||
I.e. the select-transfer-deselect transaction targeting e.g. device
|
||||
address 0x42 behind mux-one may be interleaved with a similar
|
||||
operation targeting device address 0x42 behind mux-two. The
|
||||
intent with such a topology would in this hypothetical example
|
||||
be that mux-one and mux-two should not be selected simultaneously,
|
||||
but mux-locked muxes do not guarantee that in all topologies.
|
||||
|
||||
[ML3]
|
||||
A mux-locked mux cannot be used by a driver for auto-closing
|
||||
gates/muxes, i.e. something that closes automatically after a given
|
||||
number (one, in most cases) of I2C transfers. Unrelated I2C transfers
|
||||
may creep in and close prematurely.
|
||||
|
||||
[ML4]
|
||||
If any non-I2C operation in the mux driver changes the I2C mux state,
|
||||
the driver has to lock the root adapter during that operation.
|
||||
Otherwise garbage may appear on the bus as seen from devices
|
||||
behind the mux, when an unrelated I2C transfer is in flight during
|
||||
the non-I2C mux-changing operation.
|
||||
|
||||
|
||||
Parent-locked muxes
|
||||
-------------------
|
||||
|
|
@ -161,28 +129,10 @@ Parent-locked muxes lock the parent adapter during the full select-
|
|||
transfer-deselect transaction. The implication is that the mux driver
|
||||
has to ensure that any and all I2C transfers through that parent
|
||||
adapter during the transaction are unlocked I2C transfers (using e.g.
|
||||
__i2c_transfer), or a deadlock will follow. There are a couple of
|
||||
caveats.
|
||||
|
||||
==== ====================================================================
|
||||
PL1. If you build a topology with a parent-locked mux being the child
|
||||
of another mux, this might break a possible assumption from the
|
||||
child mux that the root adapter is unused between its select op
|
||||
and the actual transfer (e.g. if the child mux is auto-closing
|
||||
and the parent mux issues I2C transfers as part of its select).
|
||||
This is especially the case if the parent mux is mux-locked, but
|
||||
it may also happen if the parent mux is parent-locked.
|
||||
|
||||
PL2. If select/deselect calls out to other subsystems such as gpio,
|
||||
pinctrl, regmap or iio, it is essential that any I2C transfers
|
||||
caused by these subsystems are unlocked. This can be convoluted to
|
||||
accomplish, maybe even impossible if an acceptably clean solution
|
||||
is sought.
|
||||
==== ====================================================================
|
||||
|
||||
__i2c_transfer), or a deadlock will follow.
|
||||
|
||||
Parent-locked Example
|
||||
---------------------
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
::
|
||||
|
||||
|
|
@ -212,10 +162,30 @@ When there is an access to D1, this happens:
|
|||
9. M1 unlocks its parent adapter.
|
||||
10. M1 unlocks muxes on its parent.
|
||||
|
||||
|
||||
This means that accesses to both D2 and D3 are locked out for the full
|
||||
duration of the entire operation.
|
||||
|
||||
Parent-locked Caveats
|
||||
~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
When using a parent-locked mux, be aware of the following restrictions:
|
||||
|
||||
[PL1]
|
||||
If you build a topology with a parent-locked mux being the child
|
||||
of another mux, this might break a possible assumption from the
|
||||
child mux that the root adapter is unused between its select op
|
||||
and the actual transfer (e.g. if the child mux is auto-closing
|
||||
and the parent mux issues I2C transfers as part of its select).
|
||||
This is especially the case if the parent mux is mux-locked, but
|
||||
it may also happen if the parent mux is parent-locked.
|
||||
|
||||
[PL2]
|
||||
If select/deselect calls out to other subsystems such as gpio,
|
||||
pinctrl, regmap or iio, it is essential that any I2C transfers
|
||||
caused by these subsystems are unlocked. This can be convoluted to
|
||||
accomplish, maybe even impossible if an acceptably clean solution
|
||||
is sought.
|
||||
|
||||
|
||||
Complex Examples
|
||||
================
|
||||
|
|
@ -261,8 +231,10 @@ This is a good topology::
|
|||
When device D1 is accessed, accesses to D2 are locked out for the
|
||||
full duration of the operation (muxes on the top child adapter of M1
|
||||
are locked). But accesses to D3 and D4 are possibly interleaved at
|
||||
any point. Accesses to D3 locks out D1 and D2, but accesses to D4
|
||||
are still possibly interleaved.
|
||||
any point.
|
||||
|
||||
Accesses to D3 locks out D1 and D2, but accesses to D4 are still possibly
|
||||
interleaved.
|
||||
|
||||
|
||||
Mux-locked mux as parent of parent-locked mux
|
||||
|
|
@ -394,3 +366,47 @@ This is a good topology::
|
|||
When D1 or D2 are accessed, accesses to D3 and D4 are locked out while
|
||||
accesses to D5 may interleave. When D3 or D4 are accessed, accesses to
|
||||
all other devices are locked out.
|
||||
|
||||
|
||||
Mux type of existing device drivers
|
||||
===================================
|
||||
|
||||
Whether a device is mux-locked or parent-locked depends on its
|
||||
implementation. The following list was correct at the time of writing:
|
||||
|
||||
In drivers/i2c/muxes/:
|
||||
|
||||
====================== =============================================
|
||||
i2c-arb-gpio-challenge Parent-locked
|
||||
i2c-mux-gpio Normally parent-locked, mux-locked iff
|
||||
all involved gpio pins are controlled by the
|
||||
same I2C root adapter that they mux.
|
||||
i2c-mux-gpmux Normally parent-locked, mux-locked iff
|
||||
specified in device-tree.
|
||||
i2c-mux-ltc4306 Mux-locked
|
||||
i2c-mux-mlxcpld Parent-locked
|
||||
i2c-mux-pca9541 Parent-locked
|
||||
i2c-mux-pca954x Parent-locked
|
||||
i2c-mux-pinctrl Normally parent-locked, mux-locked iff
|
||||
all involved pinctrl devices are controlled
|
||||
by the same I2C root adapter that they mux.
|
||||
i2c-mux-reg Parent-locked
|
||||
====================== =============================================
|
||||
|
||||
In drivers/iio/:
|
||||
|
||||
====================== =============================================
|
||||
gyro/mpu3050 Mux-locked
|
||||
imu/inv_mpu6050/ Mux-locked
|
||||
====================== =============================================
|
||||
|
||||
In drivers/media/:
|
||||
|
||||
======================= =============================================
|
||||
dvb-frontends/lgdt3306a Mux-locked
|
||||
dvb-frontends/m88ds3103 Parent-locked
|
||||
dvb-frontends/rtl2830 Parent-locked
|
||||
dvb-frontends/rtl2832 Mux-locked
|
||||
dvb-frontends/si2168 Mux-locked
|
||||
usb/cx231xx/ Parent-locked
|
||||
======================= =============================================
|
||||
|
|
|
|||
|
|
@ -47,7 +47,6 @@ allow_join_initial_addr_port - BOOLEAN
|
|||
Default: 1
|
||||
|
||||
pm_type - INTEGER
|
||||
|
||||
Set the default path manager type to use for each new MPTCP
|
||||
socket. In-kernel path management will control subflow
|
||||
connections and address advertisements according to
|
||||
|
|
|
|||
|
|
@ -70,15 +70,6 @@ nf_conntrack_generic_timeout - INTEGER (seconds)
|
|||
Default for generic timeout. This refers to layer 4 unknown/unsupported
|
||||
protocols.
|
||||
|
||||
nf_conntrack_helper - BOOLEAN
|
||||
- 0 - disabled (default)
|
||||
- not 0 - enabled
|
||||
|
||||
Enable automatic conntrack helper assignment.
|
||||
If disabled it is required to set up iptables rules to assign
|
||||
helpers to connections. See the CT target description in the
|
||||
iptables-extensions(8) man page for further information.
|
||||
|
||||
nf_conntrack_icmp_timeout - INTEGER (seconds)
|
||||
default 30
|
||||
|
||||
|
|
|
|||
42
MAINTAINERS
42
MAINTAINERS
|
|
@ -1810,7 +1810,7 @@ N: sun[x456789]i
|
|||
N: sun50i
|
||||
|
||||
ARM/Amlogic Meson SoC CLOCK FRAMEWORK
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
M: Jerome Brunet <jbrunet@baylibre.com>
|
||||
L: linux-amlogic@lists.infradead.org
|
||||
S: Maintained
|
||||
|
|
@ -1835,7 +1835,7 @@ F: Documentation/devicetree/bindings/sound/amlogic*
|
|||
F: sound/soc/meson/
|
||||
|
||||
ARM/Amlogic Meson SoC support
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
M: Kevin Hilman <khilman@baylibre.com>
|
||||
R: Jerome Brunet <jbrunet@baylibre.com>
|
||||
R: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
|
||||
|
|
@ -2538,7 +2538,7 @@ W: http://www.digriz.org.uk/ts78xx/kernel
|
|||
F: arch/arm/mach-orion5x/ts78xx-*
|
||||
|
||||
ARM/OXNAS platform support
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: linux-oxnas@groups.io (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
|
|
@ -6792,7 +6792,7 @@ F: Documentation/devicetree/bindings/display/allwinner*
|
|||
F: drivers/gpu/drm/sun4i/
|
||||
|
||||
DRM DRIVERS FOR AMLOGIC SOCS
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
L: linux-amlogic@lists.infradead.org
|
||||
S: Supported
|
||||
|
|
@ -6814,7 +6814,7 @@ F: drivers/gpu/drm/atmel-hlcdc/
|
|||
|
||||
DRM DRIVERS FOR BRIDGE CHIPS
|
||||
M: Andrzej Hajda <andrzej.hajda@intel.com>
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
M: Robert Foss <robert.foss@linaro.org>
|
||||
R: Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
|
||||
R: Jonas Karlman <jonas@kwiboo.se>
|
||||
|
|
@ -8652,8 +8652,8 @@ F: drivers/input/touchscreen/goodix*
|
|||
|
||||
GOOGLE ETHERNET DRIVERS
|
||||
M: Jeroen de Borst <jeroendb@google.com>
|
||||
R: Catherine Sullivan <csully@google.com>
|
||||
R: David Awogbemila <awogbemila@google.com>
|
||||
M: Catherine Sullivan <csully@google.com>
|
||||
R: Shailend Chand <shailend@google.com>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/networking/device_drivers/ethernet/google/gve.rst
|
||||
|
|
@ -9122,7 +9122,7 @@ S: Maintained
|
|||
F: drivers/dma/hisi_dma.c
|
||||
|
||||
HISILICON GPIO DRIVER
|
||||
M: Luo Jiaxing <luojiaxing@huawei.com>
|
||||
M: Jay Fang <f.fangjian@huawei.com>
|
||||
L: linux-gpio@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/gpio/gpio-hisi.c
|
||||
|
|
@ -9208,8 +9208,8 @@ F: Documentation/ABI/testing/debugfs-hisi-zip
|
|||
F: drivers/crypto/hisilicon/zip/
|
||||
|
||||
HISILICON ROCE DRIVER
|
||||
M: Haoyue Xu <xuhaoyue1@hisilicon.com>
|
||||
M: Wenpeng Liang <liangwenpeng@huawei.com>
|
||||
M: Weihang Li <liweihang@huawei.com>
|
||||
L: linux-rdma@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/infiniband/hisilicon-hns-roce.txt
|
||||
|
|
@ -10828,7 +10828,7 @@ F: drivers/media/tuners/it913x*
|
|||
|
||||
ITE IT66121 HDMI BRIDGE DRIVER
|
||||
M: Phong LE <ple@baylibre.com>
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
S: Maintained
|
||||
T: git git://anongit.freedesktop.org/drm/drm-misc
|
||||
F: Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml
|
||||
|
|
@ -11347,7 +11347,7 @@ F: kernel/debug/
|
|||
F: kernel/module/kdb.c
|
||||
|
||||
KHADAS MCU MFD DRIVER
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
L: linux-amlogic@lists.infradead.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/mfd/khadas,mcu.yaml
|
||||
|
|
@ -13218,7 +13218,7 @@ S: Maintained
|
|||
F: drivers/watchdog/menz69_wdt.c
|
||||
|
||||
MESON AO CEC DRIVER FOR AMLOGIC SOCS
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
L: linux-amlogic@lists.infradead.org
|
||||
S: Supported
|
||||
|
|
@ -13229,7 +13229,7 @@ F: drivers/media/cec/platform/meson/ao-cec-g12a.c
|
|||
F: drivers/media/cec/platform/meson/ao-cec.c
|
||||
|
||||
MESON GE2D DRIVER FOR AMLOGIC SOCS
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
L: linux-amlogic@lists.infradead.org
|
||||
S: Supported
|
||||
|
|
@ -13245,7 +13245,7 @@ F: Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
|
|||
F: drivers/mtd/nand/raw/meson_*
|
||||
|
||||
MESON VIDEO DECODER DRIVER FOR AMLOGIC SOCS
|
||||
M: Neil Armstrong <narmstrong@baylibre.com>
|
||||
M: Neil Armstrong <neil.armstrong@linaro.org>
|
||||
L: linux-media@vger.kernel.org
|
||||
L: linux-amlogic@lists.infradead.org
|
||||
S: Supported
|
||||
|
|
@ -16864,6 +16864,7 @@ F: drivers/net/ethernet/qualcomm/emac/
|
|||
|
||||
QUALCOMM ETHQOS ETHERNET DRIVER
|
||||
M: Vinod Koul <vkoul@kernel.org>
|
||||
R: Bhupesh Sharma <bhupesh.sharma@linaro.org>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/net/qcom,ethqos.txt
|
||||
|
|
@ -17752,6 +17753,17 @@ L: linux-rdma@vger.kernel.org
|
|||
S: Maintained
|
||||
F: drivers/infiniband/ulp/rtrs/
|
||||
|
||||
RUNTIME VERIFICATION (RV)
|
||||
M: Daniel Bristot de Oliveira <bristot@kernel.org>
|
||||
M: Steven Rostedt <rostedt@goodmis.org>
|
||||
L: linux-trace-devel@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/trace/rv/
|
||||
F: include/linux/rv.h
|
||||
F: include/rv/
|
||||
F: kernel/trace/rv/
|
||||
F: tools/verification/
|
||||
|
||||
RXRPC SOCKETS (AF_RXRPC)
|
||||
M: David Howells <dhowells@redhat.com>
|
||||
M: Marc Dionne <marc.dionne@auristor.com>
|
||||
|
|
@ -19955,6 +19967,7 @@ S: Supported
|
|||
F: drivers/net/team/
|
||||
F: include/linux/if_team.h
|
||||
F: include/uapi/linux/if_team.h
|
||||
F: tools/testing/selftests/net/team/
|
||||
|
||||
TECHNOLOGIC SYSTEMS TS-5500 PLATFORM SUPPORT
|
||||
M: "Savoir-faire Linux Inc." <kernel@savoirfairelinux.com>
|
||||
|
|
@ -20618,6 +20631,7 @@ F: include/*/ftrace.h
|
|||
F: include/linux/trace*.h
|
||||
F: include/trace/
|
||||
F: kernel/trace/
|
||||
F: scripts/tracing/
|
||||
F: tools/testing/selftests/ftrace/
|
||||
|
||||
TRACING MMIO ACCESSES (MMIOTRACE)
|
||||
|
|
|
|||
5
Makefile
5
Makefile
|
|
@ -2,7 +2,7 @@
|
|||
VERSION = 6
|
||||
PATCHLEVEL = 0
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc4
|
||||
EXTRAVERSION = -rc6
|
||||
NAME = Hurr durr I'ma ninja sloth
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
@ -1287,8 +1287,7 @@ hdr-inst := -f $(srctree)/scripts/Makefile.headersinst obj
|
|||
|
||||
PHONY += headers
|
||||
headers: $(version_h) scripts_unifdef uapi-asm-generic archheaders archscripts
|
||||
$(if $(wildcard $(srctree)/arch/$(SRCARCH)/include/uapi/asm/Kbuild),, \
|
||||
$(error Headers not exportable for the $(SRCARCH) architecture))
|
||||
$(if $(filter um, $(SRCARCH)), $(error Headers not exportable for UML))
|
||||
$(Q)$(MAKE) $(hdr-inst)=include/uapi
|
||||
$(Q)$(MAKE) $(hdr-inst)=arch/$(SRCARCH)/include/uapi
|
||||
|
||||
|
|
|
|||
|
|
@ -923,6 +923,9 @@ config HAVE_SOFTIRQ_ON_OWN_STACK
|
|||
Architecture provides a function to run __do_softirq() on a
|
||||
separate stack.
|
||||
|
||||
config SOFTIRQ_ON_OWN_STACK
|
||||
def_bool HAVE_SOFTIRQ_ON_OWN_STACK && !PREEMPT_RT
|
||||
|
||||
config ALTERNATE_USER_ADDRESS_SPACE
|
||||
bool
|
||||
help
|
||||
|
|
|
|||
|
|
@ -70,7 +70,7 @@ static void __init init_irq_stacks(void)
|
|||
}
|
||||
}
|
||||
|
||||
#ifndef CONFIG_PREEMPT_RT
|
||||
#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
|
||||
static void ____do_softirq(void *arg)
|
||||
{
|
||||
__do_softirq();
|
||||
|
|
|
|||
|
|
@ -1887,6 +1887,8 @@ config ARM64_BTI_KERNEL
|
|||
depends on CC_HAS_BRANCH_PROT_PAC_RET_BTI
|
||||
# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=94697
|
||||
depends on !CC_IS_GCC || GCC_VERSION >= 100100
|
||||
# https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106671
|
||||
depends on !CC_IS_GCC
|
||||
# https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
|
||||
depends on !CC_IS_CLANG || CLANG_VERSION >= 120000
|
||||
depends on (!FUNCTION_GRAPH_TRACER || DYNAMIC_FTRACE_WITH_REGS)
|
||||
|
|
|
|||
|
|
@ -1084,7 +1084,6 @@ static int za_set(struct task_struct *target,
|
|||
if (!target->thread.sve_state) {
|
||||
sve_alloc(target, false);
|
||||
if (!target->thread.sve_state) {
|
||||
clear_thread_flag(TIF_SME);
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
}
|
||||
|
|
@ -1094,7 +1093,6 @@ static int za_set(struct task_struct *target,
|
|||
sme_alloc(target);
|
||||
if (!target->thread.za_state) {
|
||||
ret = -ENOMEM;
|
||||
clear_tsk_thread_flag(target, TIF_SME);
|
||||
goto out;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -101,6 +101,9 @@ SYM_FUNC_END(__cpu_suspend_enter)
|
|||
SYM_CODE_START(cpu_resume)
|
||||
bl init_kernel_el
|
||||
bl finalise_el2
|
||||
#if VA_BITS > 48
|
||||
ldr_l x0, vabits_actual
|
||||
#endif
|
||||
bl __cpu_setup
|
||||
/* enable the MMU early - so we can access sleep_save_stash by va */
|
||||
adrp x1, swapper_pg_dir
|
||||
|
|
|
|||
|
|
@ -2669,7 +2669,6 @@ config ARCH_FLATMEM_ENABLE
|
|||
|
||||
config ARCH_SPARSEMEM_ENABLE
|
||||
bool
|
||||
select SPARSEMEM_STATIC if !SGI_IP27
|
||||
|
||||
config NUMA
|
||||
bool "NUMA Support"
|
||||
|
|
|
|||
|
|
@ -57,14 +57,11 @@ EXPORT_SYMBOL_GPL(__cvmx_cmd_queue_state_ptr);
|
|||
static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void)
|
||||
{
|
||||
char *alloc_name = "cvmx_cmd_queues";
|
||||
#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32
|
||||
extern uint64_t octeon_reserve32_memory;
|
||||
#endif
|
||||
|
||||
if (likely(__cvmx_cmd_queue_state_ptr))
|
||||
return CVMX_CMD_QUEUE_SUCCESS;
|
||||
|
||||
#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32
|
||||
if (octeon_reserve32_memory)
|
||||
__cvmx_cmd_queue_state_ptr =
|
||||
cvmx_bootmem_alloc_named_range(sizeof(*__cvmx_cmd_queue_state_ptr),
|
||||
|
|
@ -73,7 +70,6 @@ static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void)
|
|||
(CONFIG_CAVIUM_RESERVE32 <<
|
||||
20) - 1, 128, alloc_name);
|
||||
else
|
||||
#endif
|
||||
__cvmx_cmd_queue_state_ptr =
|
||||
cvmx_bootmem_alloc_named(sizeof(*__cvmx_cmd_queue_state_ptr),
|
||||
128,
|
||||
|
|
|
|||
|
|
@ -127,6 +127,16 @@ static void octeon_irq_free_cd(struct irq_domain *d, unsigned int irq)
|
|||
static int octeon_irq_force_ciu_mapping(struct irq_domain *domain,
|
||||
int irq, int line, int bit)
|
||||
{
|
||||
struct device_node *of_node;
|
||||
int ret;
|
||||
|
||||
of_node = irq_domain_get_of_node(domain);
|
||||
if (!of_node)
|
||||
return -EINVAL;
|
||||
ret = irq_alloc_desc_at(irq, of_node_to_nid(of_node));
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
return irq_domain_associate(domain, irq, line << 6 | bit);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -284,10 +284,8 @@ void octeon_crash_smp_send_stop(void)
|
|||
|
||||
#endif /* CONFIG_KEXEC */
|
||||
|
||||
#ifdef CONFIG_CAVIUM_RESERVE32
|
||||
uint64_t octeon_reserve32_memory;
|
||||
EXPORT_SYMBOL(octeon_reserve32_memory);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_KEXEC
|
||||
/* crashkernel cmdline parameter is parsed _after_ memory setup
|
||||
|
|
@ -666,9 +664,6 @@ void __init prom_init(void)
|
|||
int i;
|
||||
u64 t;
|
||||
int argc;
|
||||
#ifdef CONFIG_CAVIUM_RESERVE32
|
||||
int64_t addr = -1;
|
||||
#endif
|
||||
/*
|
||||
* The bootloader passes a pointer to the boot descriptor in
|
||||
* $a3, this is available as fw_arg3.
|
||||
|
|
@ -783,7 +778,7 @@ void __init prom_init(void)
|
|||
cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
|
||||
cvmx_write_csr(CVMX_LED_EN, 1);
|
||||
}
|
||||
#ifdef CONFIG_CAVIUM_RESERVE32
|
||||
|
||||
/*
|
||||
* We need to temporarily allocate all memory in the reserve32
|
||||
* region. This makes sure the kernel doesn't allocate this
|
||||
|
|
@ -794,14 +789,16 @@ void __init prom_init(void)
|
|||
* Allocate memory for RESERVED32 aligned on 2MB boundary. This
|
||||
* is in case we later use hugetlb entries with it.
|
||||
*/
|
||||
addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
|
||||
0, 0, 2 << 20,
|
||||
"CAVIUM_RESERVE32", 0);
|
||||
if (addr < 0)
|
||||
pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
|
||||
else
|
||||
octeon_reserve32_memory = addr;
|
||||
#endif
|
||||
if (CONFIG_CAVIUM_RESERVE32) {
|
||||
int64_t addr =
|
||||
cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
|
||||
0, 0, 2 << 20,
|
||||
"CAVIUM_RESERVE32", 0);
|
||||
if (addr < 0)
|
||||
pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
|
||||
else
|
||||
octeon_reserve32_memory = addr;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
|
||||
if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
|
||||
|
|
@ -1079,7 +1076,6 @@ void __init plat_mem_setup(void)
|
|||
cvmx_bootmem_unlock();
|
||||
#endif /* CONFIG_CRASH_DUMP */
|
||||
|
||||
#ifdef CONFIG_CAVIUM_RESERVE32
|
||||
/*
|
||||
* Now that we've allocated the kernel memory it is safe to
|
||||
* free the reserved region. We free it here so that builtin
|
||||
|
|
@ -1087,7 +1083,6 @@ void __init plat_mem_setup(void)
|
|||
*/
|
||||
if (octeon_reserve32_memory)
|
||||
cvmx_bootmem_free_named("CAVIUM_RESERVE32");
|
||||
#endif /* CONFIG_CAVIUM_RESERVE32 */
|
||||
|
||||
if (total == 0)
|
||||
panic("Unable to allocate memory from "
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ struct clk *clk_get_io(void)
|
|||
{
|
||||
return &cpu_clk_generic[2];
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(clk_get_io);
|
||||
|
||||
struct clk *clk_get_ppe(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ int ls1x_eth_mux_init(struct platform_device *pdev, void *priv)
|
|||
if (plat_dat->bus_id) {
|
||||
__raw_writel(__raw_readl(LS1X_MUX_CTRL0) | GMAC1_USE_UART1 |
|
||||
GMAC1_USE_UART0, LS1X_MUX_CTRL0);
|
||||
switch (plat_dat->interface) {
|
||||
switch (plat_dat->phy_interface) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
val &= ~(GMAC1_USE_TXCLK | GMAC1_USE_PWM23);
|
||||
break;
|
||||
|
|
@ -107,12 +107,12 @@ int ls1x_eth_mux_init(struct platform_device *pdev, void *priv)
|
|||
break;
|
||||
default:
|
||||
pr_err("unsupported mii mode %d\n",
|
||||
plat_dat->interface);
|
||||
plat_dat->phy_interface);
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
val &= ~GMAC1_SHUT;
|
||||
} else {
|
||||
switch (plat_dat->interface) {
|
||||
switch (plat_dat->phy_interface) {
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
val &= ~(GMAC0_USE_TXCLK | GMAC0_USE_PWM01);
|
||||
break;
|
||||
|
|
@ -121,7 +121,7 @@ int ls1x_eth_mux_init(struct platform_device *pdev, void *priv)
|
|||
break;
|
||||
default:
|
||||
pr_err("unsupported mii mode %d\n",
|
||||
plat_dat->interface);
|
||||
plat_dat->phy_interface);
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
val &= ~GMAC0_SHUT;
|
||||
|
|
@ -131,7 +131,7 @@ int ls1x_eth_mux_init(struct platform_device *pdev, void *priv)
|
|||
plat_dat = dev_get_platdata(&pdev->dev);
|
||||
|
||||
val &= ~PHY_INTF_SELI;
|
||||
if (plat_dat->interface == PHY_INTERFACE_MODE_RMII)
|
||||
if (plat_dat->phy_interface == PHY_INTERFACE_MODE_RMII)
|
||||
val |= 0x4 << PHY_INTF_SELI_SHIFT;
|
||||
__raw_writel(val, LS1X_MUX_CTRL1);
|
||||
|
||||
|
|
@ -146,9 +146,9 @@ static struct plat_stmmacenet_data ls1x_eth0_pdata = {
|
|||
.bus_id = 0,
|
||||
.phy_addr = -1,
|
||||
#if defined(CONFIG_LOONGSON1_LS1B)
|
||||
.interface = PHY_INTERFACE_MODE_MII,
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
#elif defined(CONFIG_LOONGSON1_LS1C)
|
||||
.interface = PHY_INTERFACE_MODE_RMII,
|
||||
.phy_interface = PHY_INTERFACE_MODE_RMII,
|
||||
#endif
|
||||
.mdio_bus_data = &ls1x_mdio_bus_data,
|
||||
.dma_cfg = &ls1x_eth_dma_cfg,
|
||||
|
|
@ -186,7 +186,7 @@ struct platform_device ls1x_eth0_pdev = {
|
|||
static struct plat_stmmacenet_data ls1x_eth1_pdata = {
|
||||
.bus_id = 1,
|
||||
.phy_addr = -1,
|
||||
.interface = PHY_INTERFACE_MODE_MII,
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
.mdio_bus_data = &ls1x_mdio_bus_data,
|
||||
.dma_cfg = &ls1x_eth_dma_cfg,
|
||||
.has_gmac = 1,
|
||||
|
|
|
|||
|
|
@ -15,7 +15,6 @@ static struct platform_device *ls1c_platform_devices[] __initdata = {
|
|||
static int __init ls1c_platform_init(void)
|
||||
{
|
||||
ls1x_serial_set_uartclk(&ls1x_uart_pdev);
|
||||
ls1x_rtc_set_extclk(&ls1x_rtc_pdev);
|
||||
|
||||
return platform_add_devices(ls1c_platform_devices,
|
||||
ARRAY_SIZE(ls1c_platform_devices));
|
||||
|
|
|
|||
|
|
@ -224,8 +224,18 @@ config MLONGCALLS
|
|||
Enabling this option will probably slow down your kernel.
|
||||
|
||||
config 64BIT
|
||||
def_bool "$(ARCH)" = "parisc64"
|
||||
def_bool y if "$(ARCH)" = "parisc64"
|
||||
bool "64-bit kernel" if "$(ARCH)" = "parisc"
|
||||
depends on PA8X00
|
||||
help
|
||||
Enable this if you want to support 64bit kernel on PA-RISC platform.
|
||||
|
||||
At the moment, only people willing to use more than 2GB of RAM,
|
||||
or having a 64bit-only capable PA-RISC machine should say Y here.
|
||||
|
||||
Since there is no 64bit userland on PA-RISC, there is no point to
|
||||
enable this option otherwise. The 64bit kernel is significantly bigger
|
||||
and slower than the 32bit one.
|
||||
|
||||
choice
|
||||
prompt "Kernel page size"
|
||||
|
|
|
|||
|
|
@ -480,7 +480,7 @@ static void execute_on_irq_stack(void *func, unsigned long param1)
|
|||
*irq_stack_in_use = 1;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_PREEMPT_RT
|
||||
#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
|
||||
void do_softirq_own_stack(void)
|
||||
{
|
||||
execute_on_irq_stack(__do_softirq, 0);
|
||||
|
|
|
|||
|
|
@ -199,7 +199,7 @@ static inline void check_stack_overflow(unsigned long sp)
|
|||
}
|
||||
}
|
||||
|
||||
#ifndef CONFIG_PREEMPT_RT
|
||||
#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
|
||||
static __always_inline void call_do_softirq(const void *sp)
|
||||
{
|
||||
/* Temporarily switch r1 to sp, call __do_softirq() then restore r1. */
|
||||
|
|
@ -335,7 +335,7 @@ void *mcheckirq_ctx[NR_CPUS] __read_mostly;
|
|||
void *softirq_ctx[NR_CPUS] __read_mostly;
|
||||
void *hardirq_ctx[NR_CPUS] __read_mostly;
|
||||
|
||||
#ifndef CONFIG_PREEMPT_RT
|
||||
#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
|
||||
void do_softirq_own_stack(void)
|
||||
{
|
||||
call_do_softirq(softirq_ctx[smp_processor_id()]);
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/string.h>
|
||||
#include <linux/types.h>
|
||||
#include <asm/hvcall.h>
|
||||
#include <asm/machdep.h>
|
||||
|
||||
#include "plpks.h"
|
||||
|
||||
|
|
@ -457,4 +458,4 @@ static __init int pseries_plpks_init(void)
|
|||
|
||||
return rc;
|
||||
}
|
||||
arch_initcall(pseries_plpks_init);
|
||||
machine_arch_initcall(pseries, pseries_plpks_init);
|
||||
|
|
|
|||
|
|
@ -185,7 +185,7 @@
|
|||
ranges;
|
||||
|
||||
cctrllr: cache-controller@2010000 {
|
||||
compatible = "sifive,fu540-c000-ccache", "cache";
|
||||
compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
|
||||
reg = <0x0 0x2010000 0x0 0x1000>;
|
||||
cache-block-size = <64>;
|
||||
cache-level = <2>;
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
#include <asm/lowcore.h>
|
||||
#include <asm/stacktrace.h>
|
||||
|
||||
#ifndef CONFIG_PREEMPT_RT
|
||||
#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
|
||||
static inline void do_softirq_own_stack(void)
|
||||
{
|
||||
call_on_stack(0, S390_lowcore.async_stack, void, __do_softirq);
|
||||
|
|
|
|||
|
|
@ -64,7 +64,7 @@ static inline unsigned long nmi_get_mcesa_size(void)
|
|||
* structure. The structure is required for machine check happening
|
||||
* early in the boot process.
|
||||
*/
|
||||
static struct mcesa boot_mcesa __initdata __aligned(MCESA_MAX_SIZE);
|
||||
static struct mcesa boot_mcesa __aligned(MCESA_MAX_SIZE);
|
||||
|
||||
void __init nmi_alloc_mcesa_early(u64 *mcesad)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -479,6 +479,7 @@ static void __init setup_lowcore_dat_off(void)
|
|||
put_abs_lowcore(restart_data, lc->restart_data);
|
||||
put_abs_lowcore(restart_source, lc->restart_source);
|
||||
put_abs_lowcore(restart_psw, lc->restart_psw);
|
||||
put_abs_lowcore(mcesad, lc->mcesad);
|
||||
|
||||
mcck_stack = (unsigned long)memblock_alloc(THREAD_SIZE, THREAD_SIZE);
|
||||
if (!mcck_stack)
|
||||
|
|
@ -507,8 +508,8 @@ static void __init setup_lowcore_dat_on(void)
|
|||
S390_lowcore.svc_new_psw.mask |= PSW_MASK_DAT;
|
||||
S390_lowcore.program_new_psw.mask |= PSW_MASK_DAT;
|
||||
S390_lowcore.io_new_psw.mask |= PSW_MASK_DAT;
|
||||
__ctl_store(S390_lowcore.cregs_save_area, 0, 15);
|
||||
__ctl_set_bit(0, 28);
|
||||
__ctl_store(S390_lowcore.cregs_save_area, 0, 15);
|
||||
put_abs_lowcore(restart_flags, RESTART_FLAG_CTLREGS);
|
||||
put_abs_lowcore(program_new_psw, lc->program_new_psw);
|
||||
for (cr = 0; cr < ARRAY_SIZE(lc->cregs_save_area); cr++)
|
||||
|
|
|
|||
|
|
@ -149,7 +149,7 @@ void irq_ctx_exit(int cpu)
|
|||
hardirq_ctx[cpu] = NULL;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_PREEMPT_RT
|
||||
#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
|
||||
void do_softirq_own_stack(void)
|
||||
{
|
||||
struct thread_info *curctx;
|
||||
|
|
|
|||
|
|
@ -855,7 +855,7 @@ void __irq_entry handler_irq(int pil, struct pt_regs *regs)
|
|||
set_irq_regs(old_regs);
|
||||
}
|
||||
|
||||
#ifndef CONFIG_PREEMPT_RT
|
||||
#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
|
||||
void do_softirq_own_stack(void)
|
||||
{
|
||||
void *orig_sp, *sp = softirq_stack[smp_processor_id()];
|
||||
|
|
|
|||
|
|
@ -132,10 +132,18 @@ export LDS_ELF_FORMAT := $(ELF_FORMAT)
|
|||
# The wrappers will select whether using "malloc" or the kernel allocator.
|
||||
LINK_WRAPS = -Wl,--wrap,malloc -Wl,--wrap,free -Wl,--wrap,calloc
|
||||
|
||||
# Avoid binutils 2.39+ warnings by marking the stack non-executable and
|
||||
# ignorning warnings for the kallsyms sections.
|
||||
LDFLAGS_EXECSTACK = -z noexecstack
|
||||
ifeq ($(CONFIG_LD_IS_BFD),y)
|
||||
LDFLAGS_EXECSTACK += $(call ld-option,--no-warn-rwx-segments)
|
||||
endif
|
||||
|
||||
LD_FLAGS_CMDLINE = $(foreach opt,$(KBUILD_LDFLAGS),-Wl,$(opt))
|
||||
|
||||
# Used by link-vmlinux.sh which has special support for um link
|
||||
export CFLAGS_vmlinux := $(LINK-y) $(LINK_WRAPS) $(LD_FLAGS_CMDLINE)
|
||||
export LDFLAGS_vmlinux := $(LDFLAGS_EXECSTACK)
|
||||
|
||||
# When cleaning we don't include .config, so we don't include
|
||||
# TT or skas makefiles and don't clean skas_ptregs.h.
|
||||
|
|
|
|||
|
|
@ -48,7 +48,8 @@ void show_stack(struct task_struct *task, unsigned long *stack,
|
|||
break;
|
||||
if (i && ((i % STACKSLOTS_PER_LINE) == 0))
|
||||
pr_cont("\n");
|
||||
pr_cont(" %08lx", *stack++);
|
||||
pr_cont(" %08lx", READ_ONCE_NOCHECK(*stack));
|
||||
stack++;
|
||||
}
|
||||
|
||||
printk("%sCall Trace:\n", loglvl);
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@
|
|||
#include "um_arch.h"
|
||||
|
||||
#define DEFAULT_COMMAND_LINE_ROOT "root=98:0"
|
||||
#define DEFAULT_COMMAND_LINE_CONSOLE "console=tty"
|
||||
#define DEFAULT_COMMAND_LINE_CONSOLE "console=tty0"
|
||||
|
||||
/* Changed in add_arg and setup_arch, which run before SMP is started */
|
||||
static char __initdata command_line[COMMAND_LINE_SIZE] = { 0 };
|
||||
|
|
|
|||
|
|
@ -203,7 +203,7 @@
|
|||
IRQ_CONSTRAINTS, regs, vector); \
|
||||
}
|
||||
|
||||
#ifndef CONFIG_PREEMPT_RT
|
||||
#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
|
||||
/*
|
||||
* Macro to invoke __do_softirq on the irq stack. This is only called from
|
||||
* task context when bottom halves are about to be reenabled and soft
|
||||
|
|
|
|||
|
|
@ -132,7 +132,7 @@ int irq_init_percpu_irqstack(unsigned int cpu)
|
|||
return 0;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_PREEMPT_RT
|
||||
#ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
|
||||
void do_softirq_own_stack(void)
|
||||
{
|
||||
struct irq_stack *irqstk;
|
||||
|
|
|
|||
|
|
@ -6,10 +6,9 @@
|
|||
#include <asm/unistd.h>
|
||||
#include <sysdep/ptrace.h>
|
||||
|
||||
typedef long syscall_handler_t(struct pt_regs);
|
||||
typedef long syscall_handler_t(struct syscall_args);
|
||||
|
||||
extern syscall_handler_t *sys_call_table[];
|
||||
|
||||
#define EXECUTE_SYSCALL(syscall, regs) \
|
||||
((long (*)(struct syscall_args)) \
|
||||
(*sys_call_table[syscall]))(SYSCALL_ARGS(®s->regs))
|
||||
((*sys_call_table[syscall]))(SYSCALL_ARGS(®s->regs))
|
||||
|
|
|
|||
|
|
@ -65,9 +65,6 @@ static int get_free_idx(struct task_struct* task)
|
|||
struct thread_struct *t = &task->thread;
|
||||
int idx;
|
||||
|
||||
if (!t->arch.tls_array)
|
||||
return GDT_ENTRY_TLS_MIN;
|
||||
|
||||
for (idx = 0; idx < GDT_ENTRY_TLS_ENTRIES; idx++)
|
||||
if (!t->arch.tls_array[idx].present)
|
||||
return idx + GDT_ENTRY_TLS_MIN;
|
||||
|
|
@ -240,9 +237,6 @@ static int get_tls_entry(struct task_struct *task, struct user_desc *info,
|
|||
{
|
||||
struct thread_struct *t = &task->thread;
|
||||
|
||||
if (!t->arch.tls_array)
|
||||
goto clear;
|
||||
|
||||
if (idx < GDT_ENTRY_TLS_MIN || idx > GDT_ENTRY_TLS_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ quiet_cmd_vdso = VDSO $@
|
|||
-Wl,-T,$(filter %.lds,$^) $(filter %.o,$^) && \
|
||||
sh $(srctree)/$(src)/checkundef.sh '$(NM)' '$@'
|
||||
|
||||
VDSO_LDFLAGS = -fPIC -shared -Wl,--hash-style=sysv
|
||||
VDSO_LDFLAGS = -fPIC -shared -Wl,--hash-style=sysv -z noexecstack
|
||||
GCOV_PROFILE := n
|
||||
|
||||
#
|
||||
|
|
|
|||
|
|
@ -295,7 +295,7 @@ int blk_queue_enter(struct request_queue *q, blk_mq_req_flags_t flags)
|
|||
|
||||
while (!blk_try_enter_queue(q, pm)) {
|
||||
if (flags & BLK_MQ_REQ_NOWAIT)
|
||||
return -EBUSY;
|
||||
return -EAGAIN;
|
||||
|
||||
/*
|
||||
* read pair of barrier in blk_freeze_queue_start(), we need to
|
||||
|
|
@ -325,7 +325,7 @@ int __bio_queue_enter(struct request_queue *q, struct bio *bio)
|
|||
if (test_bit(GD_DEAD, &disk->state))
|
||||
goto dead;
|
||||
bio_wouldblock_error(bio);
|
||||
return -EBUSY;
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -309,6 +309,11 @@ int blkdev_issue_secure_erase(struct block_device *bdev, sector_t sector,
|
|||
struct blk_plug plug;
|
||||
int ret = 0;
|
||||
|
||||
/* make sure that "len << SECTOR_SHIFT" doesn't overflow */
|
||||
if (max_sectors > UINT_MAX >> SECTOR_SHIFT)
|
||||
max_sectors = UINT_MAX >> SECTOR_SHIFT;
|
||||
max_sectors &= ~bs_mask;
|
||||
|
||||
if (max_sectors == 0)
|
||||
return -EOPNOTSUPP;
|
||||
if ((sector | nr_sects) & bs_mask)
|
||||
|
|
@ -322,10 +327,10 @@ int blkdev_issue_secure_erase(struct block_device *bdev, sector_t sector,
|
|||
|
||||
bio = blk_next_bio(bio, bdev, 0, REQ_OP_SECURE_ERASE, gfp);
|
||||
bio->bi_iter.bi_sector = sector;
|
||||
bio->bi_iter.bi_size = len;
|
||||
bio->bi_iter.bi_size = len << SECTOR_SHIFT;
|
||||
|
||||
sector += len << SECTOR_SHIFT;
|
||||
nr_sects -= len << SECTOR_SHIFT;
|
||||
sector += len;
|
||||
nr_sects -= len;
|
||||
if (!nr_sects) {
|
||||
ret = submit_bio_wait(bio);
|
||||
bio_put(bio);
|
||||
|
|
|
|||
|
|
@ -283,7 +283,9 @@ static const char *const rqf_name[] = {
|
|||
RQF_NAME(SPECIAL_PAYLOAD),
|
||||
RQF_NAME(ZONE_WRITE_LOCKED),
|
||||
RQF_NAME(MQ_POLL_SLEPT),
|
||||
RQF_NAME(TIMED_OUT),
|
||||
RQF_NAME(ELV),
|
||||
RQF_NAME(RESV),
|
||||
};
|
||||
#undef RQF_NAME
|
||||
|
||||
|
|
|
|||
|
|
@ -596,6 +596,9 @@ static int blk_add_partitions(struct gendisk *disk)
|
|||
if (disk->flags & GENHD_FL_NO_PART)
|
||||
return 0;
|
||||
|
||||
if (test_bit(GD_SUPPRESS_PART_SCAN, &disk->state))
|
||||
return 0;
|
||||
|
||||
state = check_partition(disk);
|
||||
if (!state)
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -724,7 +724,7 @@ const struct cpumask *cpu_clustergroup_mask(int cpu)
|
|||
*/
|
||||
if (cpumask_subset(cpu_coregroup_mask(cpu),
|
||||
&cpu_topology[cpu].cluster_sibling))
|
||||
return get_cpu_mask(cpu);
|
||||
return topology_sibling_cpumask(cpu);
|
||||
|
||||
return &cpu_topology[cpu].cluster_sibling;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -63,6 +63,12 @@ int driver_set_override(struct device *dev, const char **override,
|
|||
if (len >= (PAGE_SIZE - 1))
|
||||
return -EINVAL;
|
||||
|
||||
/*
|
||||
* Compute the real length of the string in case userspace sends us a
|
||||
* bunch of \0 characters like python likes to do.
|
||||
*/
|
||||
len = strlen(s);
|
||||
|
||||
if (!len) {
|
||||
/* Empty string passed - clear override */
|
||||
device_lock(dev);
|
||||
|
|
|
|||
|
|
@ -113,6 +113,7 @@ static const struct regmap_bus *regmap_get_spi_bus(struct spi_device *spi,
|
|||
const struct regmap_config *config)
|
||||
{
|
||||
size_t max_size = spi_max_transfer_size(spi);
|
||||
size_t max_msg_size, reg_reserve_size;
|
||||
struct regmap_bus *bus;
|
||||
|
||||
if (max_size != SIZE_MAX) {
|
||||
|
|
@ -120,9 +121,16 @@ static const struct regmap_bus *regmap_get_spi_bus(struct spi_device *spi,
|
|||
if (!bus)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
max_msg_size = spi_max_message_size(spi);
|
||||
reg_reserve_size = config->reg_bits / BITS_PER_BYTE
|
||||
+ config->pad_bits / BITS_PER_BYTE;
|
||||
if (max_size + reg_reserve_size > max_msg_size)
|
||||
max_size -= reg_reserve_size;
|
||||
|
||||
bus->free_on_exit = true;
|
||||
bus->max_raw_read = max_size;
|
||||
bus->max_raw_write = max_size;
|
||||
|
||||
return bus;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -31,14 +31,14 @@ struct udma_dev *of_xudma_dev_get(struct device_node *np, const char *property)
|
|||
}
|
||||
|
||||
pdev = of_find_device_by_node(udma_node);
|
||||
if (np != udma_node)
|
||||
of_node_put(udma_node);
|
||||
|
||||
if (!pdev) {
|
||||
pr_debug("UDMA device not found\n");
|
||||
return ERR_PTR(-EPROBE_DEFER);
|
||||
}
|
||||
|
||||
if (np != udma_node)
|
||||
of_node_put(udma_node);
|
||||
|
||||
ud = platform_get_drvdata(pdev);
|
||||
if (!ud) {
|
||||
pr_debug("UDMA has not been probed\n");
|
||||
|
|
|
|||
|
|
@ -3040,9 +3040,10 @@ static int xilinx_dma_probe(struct platform_device *pdev)
|
|||
|
||||
/* Request and map I/O memory */
|
||||
xdev->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(xdev->regs))
|
||||
return PTR_ERR(xdev->regs);
|
||||
|
||||
if (IS_ERR(xdev->regs)) {
|
||||
err = PTR_ERR(xdev->regs);
|
||||
goto disable_clks;
|
||||
}
|
||||
/* Retrieve the DMA engine properties from the device tree */
|
||||
xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0);
|
||||
xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2;
|
||||
|
|
@ -3070,7 +3071,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)
|
|||
if (err < 0) {
|
||||
dev_err(xdev->dev,
|
||||
"missing xlnx,num-fstores property\n");
|
||||
return err;
|
||||
goto disable_clks;
|
||||
}
|
||||
|
||||
err = of_property_read_u32(node, "xlnx,flush-fsync",
|
||||
|
|
@ -3090,7 +3091,11 @@ static int xilinx_dma_probe(struct platform_device *pdev)
|
|||
xdev->ext_addr = false;
|
||||
|
||||
/* Set the dma mask bits */
|
||||
dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width));
|
||||
err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width));
|
||||
if (err < 0) {
|
||||
dev_err(xdev->dev, "DMA mask error %d\n", err);
|
||||
goto disable_clks;
|
||||
}
|
||||
|
||||
/* Initialize the DMA engine */
|
||||
xdev->common.dev = &pdev->dev;
|
||||
|
|
@ -3137,7 +3142,7 @@ static int xilinx_dma_probe(struct platform_device *pdev)
|
|||
for_each_child_of_node(node, child) {
|
||||
err = xilinx_dma_child_probe(xdev, child);
|
||||
if (err < 0)
|
||||
goto disable_clks;
|
||||
goto error;
|
||||
}
|
||||
|
||||
if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
|
||||
|
|
@ -3172,12 +3177,12 @@ static int xilinx_dma_probe(struct platform_device *pdev)
|
|||
|
||||
return 0;
|
||||
|
||||
disable_clks:
|
||||
xdma_disable_allclks(xdev);
|
||||
error:
|
||||
for (i = 0; i < xdev->dma_config->max_channels; i++)
|
||||
if (xdev->chan[i])
|
||||
xilinx_dma_chan_remove(xdev->chan[i]);
|
||||
disable_clks:
|
||||
xdma_disable_allclks(xdev);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -849,7 +849,7 @@ static struct dma_async_tx_descriptor *zynqmp_dma_prep_memcpy(
|
|||
|
||||
zynqmp_dma_desc_config_eod(chan, desc);
|
||||
async_tx_ack(&first->async_tx);
|
||||
first->async_tx.flags = flags;
|
||||
first->async_tx.flags = (enum dma_ctrl_flags)flags;
|
||||
return &first->async_tx;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -48,6 +48,9 @@ static int efibc_reboot_notifier_call(struct notifier_block *notifier,
|
|||
return NOTIFY_DONE;
|
||||
|
||||
wdata = kmalloc(MAX_DATA_LEN * sizeof(efi_char16_t), GFP_KERNEL);
|
||||
if (!wdata)
|
||||
return NOTIFY_DONE;
|
||||
|
||||
for (l = 0; l < MAX_DATA_LEN - 1 && str[l] != '\0'; l++)
|
||||
wdata[l] = str[l];
|
||||
wdata[l] = L'\0';
|
||||
|
|
|
|||
|
|
@ -14,7 +14,7 @@
|
|||
|
||||
/* SHIM variables */
|
||||
static const efi_guid_t shim_guid = EFI_SHIM_LOCK_GUID;
|
||||
static const efi_char16_t shim_MokSBState_name[] = L"MokSBState";
|
||||
static const efi_char16_t shim_MokSBState_name[] = L"MokSBStateRT";
|
||||
|
||||
static efi_status_t get_var(efi_char16_t *name, efi_guid_t *vendor, u32 *attr,
|
||||
unsigned long *data_size, void *data)
|
||||
|
|
@ -43,8 +43,8 @@ enum efi_secureboot_mode efi_get_secureboot(void)
|
|||
|
||||
/*
|
||||
* See if a user has put the shim into insecure mode. If so, and if the
|
||||
* variable doesn't have the runtime attribute set, we might as well
|
||||
* honor that.
|
||||
* variable doesn't have the non-volatile attribute set, we might as
|
||||
* well honor that.
|
||||
*/
|
||||
size = sizeof(moksbstate);
|
||||
status = get_efi_var(shim_MokSBState_name, &shim_guid,
|
||||
|
|
@ -53,7 +53,7 @@ enum efi_secureboot_mode efi_get_secureboot(void)
|
|||
/* If it fails, we don't care why. Default to secure */
|
||||
if (status != EFI_SUCCESS)
|
||||
goto secure_boot_enabled;
|
||||
if (!(attr & EFI_VARIABLE_RUNTIME_ACCESS) && moksbstate == 1)
|
||||
if (!(attr & EFI_VARIABLE_NON_VOLATILE) && moksbstate == 1)
|
||||
return efi_secureboot_mode_disabled;
|
||||
|
||||
secure_boot_enabled:
|
||||
|
|
|
|||
|
|
@ -516,6 +516,13 @@ efi_status_t __efiapi efi_pe_entry(efi_handle_t handle,
|
|||
hdr->ramdisk_image = 0;
|
||||
hdr->ramdisk_size = 0;
|
||||
|
||||
/*
|
||||
* Disregard any setup data that was provided by the bootloader:
|
||||
* setup_data could be pointing anywhere, and we have no way of
|
||||
* authenticating or validating the payload.
|
||||
*/
|
||||
hdr->setup_data = 0;
|
||||
|
||||
efi_stub_entry(handle, sys_table_arg, boot_params);
|
||||
/* not reached */
|
||||
|
||||
|
|
|
|||
|
|
@ -41,14 +41,12 @@
|
|||
* struct ftgpio_gpio - Gemini GPIO state container
|
||||
* @dev: containing device for this instance
|
||||
* @gc: gpiochip for this instance
|
||||
* @irq: irqchip for this instance
|
||||
* @base: remapped I/O-memory base
|
||||
* @clk: silicon clock
|
||||
*/
|
||||
struct ftgpio_gpio {
|
||||
struct device *dev;
|
||||
struct gpio_chip gc;
|
||||
struct irq_chip irq;
|
||||
void __iomem *base;
|
||||
struct clk *clk;
|
||||
};
|
||||
|
|
@ -70,6 +68,7 @@ static void ftgpio_gpio_mask_irq(struct irq_data *d)
|
|||
val = readl(g->base + GPIO_INT_EN);
|
||||
val &= ~BIT(irqd_to_hwirq(d));
|
||||
writel(val, g->base + GPIO_INT_EN);
|
||||
gpiochip_disable_irq(gc, irqd_to_hwirq(d));
|
||||
}
|
||||
|
||||
static void ftgpio_gpio_unmask_irq(struct irq_data *d)
|
||||
|
|
@ -78,6 +77,7 @@ static void ftgpio_gpio_unmask_irq(struct irq_data *d)
|
|||
struct ftgpio_gpio *g = gpiochip_get_data(gc);
|
||||
u32 val;
|
||||
|
||||
gpiochip_enable_irq(gc, irqd_to_hwirq(d));
|
||||
val = readl(g->base + GPIO_INT_EN);
|
||||
val |= BIT(irqd_to_hwirq(d));
|
||||
writel(val, g->base + GPIO_INT_EN);
|
||||
|
|
@ -221,6 +221,16 @@ static int ftgpio_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_chip ftgpio_irq_chip = {
|
||||
.name = "FTGPIO010",
|
||||
.irq_ack = ftgpio_gpio_ack_irq,
|
||||
.irq_mask = ftgpio_gpio_mask_irq,
|
||||
.irq_unmask = ftgpio_gpio_unmask_irq,
|
||||
.irq_set_type = ftgpio_gpio_set_irq_type,
|
||||
.flags = IRQCHIP_IMMUTABLE,
|
||||
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
||||
};
|
||||
|
||||
static int ftgpio_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
|
|
@ -277,14 +287,8 @@ static int ftgpio_gpio_probe(struct platform_device *pdev)
|
|||
if (!IS_ERR(g->clk))
|
||||
g->gc.set_config = ftgpio_gpio_set_config;
|
||||
|
||||
g->irq.name = "FTGPIO010";
|
||||
g->irq.irq_ack = ftgpio_gpio_ack_irq;
|
||||
g->irq.irq_mask = ftgpio_gpio_mask_irq;
|
||||
g->irq.irq_unmask = ftgpio_gpio_unmask_irq;
|
||||
g->irq.irq_set_type = ftgpio_gpio_set_irq_type;
|
||||
|
||||
girq = &g->gc.irq;
|
||||
girq->chip = &g->irq;
|
||||
gpio_irq_chip_set_chip(girq, &ftgpio_irq_chip);
|
||||
girq->parent_handler = ftgpio_gpio_irq_handler;
|
||||
girq->num_parents = 1;
|
||||
girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
|
||||
|
|
|
|||
|
|
@ -63,6 +63,14 @@ static void ixp4xx_gpio_irq_ack(struct irq_data *d)
|
|||
__raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS);
|
||||
}
|
||||
|
||||
static void ixp4xx_gpio_mask_irq(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
|
||||
irq_chip_mask_parent(d);
|
||||
gpiochip_disable_irq(gc, d->hwirq);
|
||||
}
|
||||
|
||||
static void ixp4xx_gpio_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
|
|
@ -72,6 +80,7 @@ static void ixp4xx_gpio_irq_unmask(struct irq_data *d)
|
|||
if (!(g->irq_edge & BIT(d->hwirq)))
|
||||
ixp4xx_gpio_irq_ack(d);
|
||||
|
||||
gpiochip_enable_irq(gc, d->hwirq);
|
||||
irq_chip_unmask_parent(d);
|
||||
}
|
||||
|
||||
|
|
@ -149,12 +158,14 @@ static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type)
|
|||
return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
|
||||
}
|
||||
|
||||
static struct irq_chip ixp4xx_gpio_irqchip = {
|
||||
static const struct irq_chip ixp4xx_gpio_irqchip = {
|
||||
.name = "IXP4GPIO",
|
||||
.irq_ack = ixp4xx_gpio_irq_ack,
|
||||
.irq_mask = irq_chip_mask_parent,
|
||||
.irq_mask = ixp4xx_gpio_mask_irq,
|
||||
.irq_unmask = ixp4xx_gpio_irq_unmask,
|
||||
.irq_set_type = ixp4xx_gpio_irq_set_type,
|
||||
.flags = IRQCHIP_IMMUTABLE,
|
||||
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
||||
};
|
||||
|
||||
static int ixp4xx_gpio_child_to_parent_hwirq(struct gpio_chip *gc,
|
||||
|
|
@ -263,7 +274,7 @@ static int ixp4xx_gpio_probe(struct platform_device *pdev)
|
|||
g->gc.owner = THIS_MODULE;
|
||||
|
||||
girq = &g->gc.irq;
|
||||
girq->chip = &ixp4xx_gpio_irqchip;
|
||||
gpio_irq_chip_set_chip(girq, &ixp4xx_gpio_irqchip);
|
||||
girq->fwnode = g->fwnode;
|
||||
girq->parent_domain = parent;
|
||||
girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq;
|
||||
|
|
|
|||
|
|
@ -533,8 +533,10 @@ static int __init gpio_mockup_register_chip(int idx)
|
|||
}
|
||||
|
||||
fwnode = fwnode_create_software_node(properties, NULL);
|
||||
if (IS_ERR(fwnode))
|
||||
if (IS_ERR(fwnode)) {
|
||||
kfree_strarray(line_names, ngpio);
|
||||
return PTR_ERR(fwnode);
|
||||
}
|
||||
|
||||
pdevinfo.name = "gpio-mockup";
|
||||
pdevinfo.id = idx;
|
||||
|
|
@ -597,9 +599,9 @@ static int __init gpio_mockup_init(void)
|
|||
|
||||
static void __exit gpio_mockup_exit(void)
|
||||
{
|
||||
gpio_mockup_unregister_pdevs();
|
||||
debugfs_remove_recursive(gpio_mockup_dbg_dir);
|
||||
platform_driver_unregister(&gpio_mockup_driver);
|
||||
gpio_mockup_unregister_pdevs();
|
||||
}
|
||||
|
||||
module_init(gpio_mockup_init);
|
||||
|
|
|
|||
|
|
@ -169,6 +169,7 @@ static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
|
|||
|
||||
switch (flow_type) {
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
|
||||
gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR,
|
||||
gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR)
|
||||
|
|
|
|||
|
|
@ -112,6 +112,8 @@ mediatek_gpio_irq_unmask(struct irq_data *d)
|
|||
unsigned long flags;
|
||||
u32 rise, fall, high, low;
|
||||
|
||||
gpiochip_enable_irq(gc, d->hwirq);
|
||||
|
||||
spin_lock_irqsave(&rg->lock, flags);
|
||||
rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
|
||||
fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
|
||||
|
|
@ -143,6 +145,8 @@ mediatek_gpio_irq_mask(struct irq_data *d)
|
|||
mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
|
||||
mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
|
||||
spin_unlock_irqrestore(&rg->lock, flags);
|
||||
|
||||
gpiochip_disable_irq(gc, d->hwirq);
|
||||
}
|
||||
|
||||
static int
|
||||
|
|
@ -204,6 +208,16 @@ mediatek_gpio_xlate(struct gpio_chip *chip,
|
|||
return gpio % MTK_BANK_WIDTH;
|
||||
}
|
||||
|
||||
static const struct irq_chip mt7621_irq_chip = {
|
||||
.name = "mt7621-gpio",
|
||||
.irq_mask_ack = mediatek_gpio_irq_mask,
|
||||
.irq_mask = mediatek_gpio_irq_mask,
|
||||
.irq_unmask = mediatek_gpio_irq_unmask,
|
||||
.irq_set_type = mediatek_gpio_irq_type,
|
||||
.flags = IRQCHIP_IMMUTABLE,
|
||||
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
||||
};
|
||||
|
||||
static int
|
||||
mediatek_gpio_bank_probe(struct device *dev, int bank)
|
||||
{
|
||||
|
|
@ -238,11 +252,6 @@ mediatek_gpio_bank_probe(struct device *dev, int bank)
|
|||
return -ENOMEM;
|
||||
|
||||
rg->chip.offset = bank * MTK_BANK_WIDTH;
|
||||
rg->irq_chip.name = dev_name(dev);
|
||||
rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask;
|
||||
rg->irq_chip.irq_mask = mediatek_gpio_irq_mask;
|
||||
rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask;
|
||||
rg->irq_chip.irq_set_type = mediatek_gpio_irq_type;
|
||||
|
||||
if (mtk->gpio_irq) {
|
||||
struct gpio_irq_chip *girq;
|
||||
|
|
@ -262,7 +271,7 @@ mediatek_gpio_bank_probe(struct device *dev, int bank)
|
|||
}
|
||||
|
||||
girq = &rg->chip.irq;
|
||||
girq->chip = &rg->irq_chip;
|
||||
gpio_irq_chip_set_chip(girq, &mt7621_irq_chip);
|
||||
/* This will let us handle the parent IRQ in the driver */
|
||||
girq->parent_handler = NULL;
|
||||
girq->num_parents = 0;
|
||||
|
|
|
|||
|
|
@ -419,11 +419,11 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
|
|||
goto out;
|
||||
} else {
|
||||
bank->toggle_edge_mode |= mask;
|
||||
level |= mask;
|
||||
level &= ~mask;
|
||||
|
||||
/*
|
||||
* Determine gpio state. If 1 next interrupt should be
|
||||
* falling otherwise rising.
|
||||
* low otherwise high.
|
||||
*/
|
||||
data = readl(bank->reg_base + bank->gpio_regs->ext_port);
|
||||
if (data & mask)
|
||||
|
|
|
|||
|
|
@ -307,6 +307,8 @@ static int tqmx86_gpio_probe(struct platform_device *pdev)
|
|||
girq->default_type = IRQ_TYPE_NONE;
|
||||
girq->handler = handle_simple_irq;
|
||||
girq->init_valid_mask = tqmx86_init_irq_valid_mask;
|
||||
|
||||
irq_domain_set_pm_device(girq->domain, dev);
|
||||
}
|
||||
|
||||
ret = devm_gpiochip_add_data(dev, chip, gpio);
|
||||
|
|
@ -315,8 +317,6 @@ static int tqmx86_gpio_probe(struct platform_device *pdev)
|
|||
goto out_pm_dis;
|
||||
}
|
||||
|
||||
irq_domain_set_pm_device(girq->domain, dev);
|
||||
|
||||
dev_info(dev, "GPIO functionality initialized with %d pins\n",
|
||||
chip->ngpio);
|
||||
|
||||
|
|
|
|||
|
|
@ -1986,7 +1986,6 @@ static int lineevent_create(struct gpio_device *gdev, void __user *ip)
|
|||
ret = -ENODEV;
|
||||
goto out_free_le;
|
||||
}
|
||||
le->irq = irq;
|
||||
|
||||
if (eflags & GPIOEVENT_REQUEST_RISING_EDGE)
|
||||
irqflags |= test_bit(FLAG_ACTIVE_LOW, &desc->flags) ?
|
||||
|
|
@ -2000,7 +1999,7 @@ static int lineevent_create(struct gpio_device *gdev, void __user *ip)
|
|||
init_waitqueue_head(&le->wait);
|
||||
|
||||
/* Request a thread to read the events */
|
||||
ret = request_threaded_irq(le->irq,
|
||||
ret = request_threaded_irq(irq,
|
||||
lineevent_irq_handler,
|
||||
lineevent_irq_thread,
|
||||
irqflags,
|
||||
|
|
@ -2009,6 +2008,8 @@ static int lineevent_create(struct gpio_device *gdev, void __user *ip)
|
|||
if (ret)
|
||||
goto out_free_le;
|
||||
|
||||
le->irq = irq;
|
||||
|
||||
fd = get_unused_fd_flags(O_RDONLY | O_CLOEXEC);
|
||||
if (fd < 0) {
|
||||
ret = fd;
|
||||
|
|
|
|||
|
|
@ -1728,7 +1728,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
|
|||
add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
|
||||
|
||||
if (user_addr) {
|
||||
pr_debug("creating userptr BO for user_addr = %llu\n", user_addr);
|
||||
pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
|
||||
ret = init_user_pages(*mem, user_addr, criu_resume);
|
||||
if (ret)
|
||||
goto allocate_init_user_pages_failed;
|
||||
|
|
|
|||
|
|
@ -2365,8 +2365,16 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
|
|||
}
|
||||
adev->ip_blocks[i].status.sw = true;
|
||||
|
||||
/* need to do gmc hw init early so we can allocate gpu mem */
|
||||
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
|
||||
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) {
|
||||
/* need to do common hw init early so everything is set up for gmc */
|
||||
r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
|
||||
if (r) {
|
||||
DRM_ERROR("hw_init %d failed %d\n", i, r);
|
||||
goto init_failed;
|
||||
}
|
||||
adev->ip_blocks[i].status.hw = true;
|
||||
} else if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
|
||||
/* need to do gmc hw init early so we can allocate gpu mem */
|
||||
/* Try to reserve bad pages early */
|
||||
if (amdgpu_sriov_vf(adev))
|
||||
amdgpu_virt_exchange_data(adev);
|
||||
|
|
@ -3052,8 +3060,8 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev)
|
|||
int i, r;
|
||||
|
||||
static enum amd_ip_block_type ip_order[] = {
|
||||
AMD_IP_BLOCK_TYPE_GMC,
|
||||
AMD_IP_BLOCK_TYPE_COMMON,
|
||||
AMD_IP_BLOCK_TYPE_GMC,
|
||||
AMD_IP_BLOCK_TYPE_PSP,
|
||||
AMD_IP_BLOCK_TYPE_IH,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -38,6 +38,7 @@
|
|||
#include <linux/pci.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <drm/drm_crtc_helper.h>
|
||||
#include <drm/drm_damage_helper.h>
|
||||
#include <drm/drm_edid.h>
|
||||
#include <drm/drm_gem_framebuffer_helper.h>
|
||||
#include <drm/drm_fb_helper.h>
|
||||
|
|
@ -496,6 +497,7 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,
|
|||
static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {
|
||||
.destroy = drm_gem_fb_destroy,
|
||||
.create_handle = drm_gem_fb_create_handle,
|
||||
.dirty = drm_atomic_helper_dirtyfb,
|
||||
};
|
||||
|
||||
uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
|
||||
|
|
|
|||
|
|
@ -486,11 +486,14 @@ static int psp_sw_fini(void *handle)
|
|||
release_firmware(psp->ta_fw);
|
||||
psp->ta_fw = NULL;
|
||||
}
|
||||
if (adev->psp.cap_fw) {
|
||||
if (psp->cap_fw) {
|
||||
release_firmware(psp->cap_fw);
|
||||
psp->cap_fw = NULL;
|
||||
}
|
||||
|
||||
if (psp->toc_fw) {
|
||||
release_firmware(psp->toc_fw);
|
||||
psp->toc_fw = NULL;
|
||||
}
|
||||
if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
|
||||
adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
|
||||
psp_sysfs_fini(adev);
|
||||
|
|
@ -753,7 +756,7 @@ static int psp_tmr_init(struct psp_context *psp)
|
|||
}
|
||||
|
||||
pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
|
||||
ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
|
||||
ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_ALIGNMENT,
|
||||
AMDGPU_GEM_DOMAIN_VRAM,
|
||||
&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
|
||||
|
||||
|
|
|
|||
|
|
@ -36,6 +36,7 @@
|
|||
#define PSP_CMD_BUFFER_SIZE 0x1000
|
||||
#define PSP_1_MEG 0x100000
|
||||
#define PSP_TMR_SIZE(adev) ((adev)->asic_type == CHIP_ALDEBARAN ? 0x800000 : 0x400000)
|
||||
#define PSP_TMR_ALIGNMENT 0x100000
|
||||
#define PSP_FW_NAME_LEN 0x24
|
||||
|
||||
enum psp_shared_mem_size {
|
||||
|
|
|
|||
|
|
@ -1811,7 +1811,8 @@ static void amdgpu_ras_log_on_err_counter(struct amdgpu_device *adev)
|
|||
amdgpu_ras_query_error_status(adev, &info);
|
||||
|
||||
if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) &&
|
||||
adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) {
|
||||
adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) &&
|
||||
adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) {
|
||||
if (amdgpu_ras_reset_error_status(adev, info.head.block))
|
||||
dev_warn(adev->dev, "Failed to reset error counter and error status");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -390,6 +390,7 @@ union amdgpu_firmware_header {
|
|||
struct rlc_firmware_header_v2_1 rlc_v2_1;
|
||||
struct rlc_firmware_header_v2_2 rlc_v2_2;
|
||||
struct rlc_firmware_header_v2_3 rlc_v2_3;
|
||||
struct rlc_firmware_header_v2_4 rlc_v2_4;
|
||||
struct sdma_firmware_header_v1_0 sdma;
|
||||
struct sdma_firmware_header_v1_1 sdma_v1_1;
|
||||
struct sdma_firmware_header_v2_0 sdma_v2_0;
|
||||
|
|
|
|||
|
|
@ -380,6 +380,7 @@ static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev,
|
|||
WREG32_PCIE(smnPCIE_LC_CNTL, data);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCIEASPM
|
||||
static void nbio_v2_3_program_ltr(struct amdgpu_device *adev)
|
||||
{
|
||||
uint32_t def, data;
|
||||
|
|
@ -401,9 +402,11 @@ static void nbio_v2_3_program_ltr(struct amdgpu_device *adev)
|
|||
if (def != data)
|
||||
WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
|
||||
{
|
||||
#ifdef CONFIG_PCIEASPM
|
||||
uint32_t def, data;
|
||||
|
||||
def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
|
||||
|
|
@ -459,7 +462,10 @@ static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
|
|||
if (def != data)
|
||||
WREG32_PCIE(smnPCIE_LC_CNTL6, data);
|
||||
|
||||
nbio_v2_3_program_ltr(adev);
|
||||
/* Don't bother about LTR if LTR is not enabled
|
||||
* in the path */
|
||||
if (adev->pdev->ltr_path)
|
||||
nbio_v2_3_program_ltr(adev);
|
||||
|
||||
def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3);
|
||||
data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
|
||||
|
|
@ -483,6 +489,7 @@ static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
|
|||
data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
|
||||
if (def != data)
|
||||
WREG32_PCIE(smnPCIE_LC_CNTL3, data);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void nbio_v2_3_apply_lc_spc_mode_wa(struct amdgpu_device *adev)
|
||||
|
|
|
|||
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