mmc: dw_mmc: Support voltage changes
For UHS cards we need the ability to switch voltages from 3.3V to 1.8V. Add support to the dw_mmc driver to handle this. Note that dw_mmc needs a little bit of extra code since the interface needs a special bit programmed to the CMD register while CMD11 is progressing. This means adding a few extra states to the state machine to track. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Doug Anderson
Ulf Hansson
Родитель
51da224090
Коммит
0173055842
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@ -29,6 +29,7 @@
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#include <linux/irq.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/mmc/sd.h>
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#include <linux/mmc/sdio.h>
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#include <linux/mmc/dw_mmc.h>
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#include <linux/bitops.h>
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@ -234,10 +235,13 @@ err:
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}
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#endif /* defined(CONFIG_DEBUG_FS) */
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static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
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static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
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{
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struct mmc_data *data;
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struct dw_mci_slot *slot = mmc_priv(mmc);
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struct dw_mci *host = slot->host;
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const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
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u32 cmdr;
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cmd->error = -EINPROGRESS;
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@ -253,6 +257,34 @@ static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
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else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
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cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
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if (cmd->opcode == SD_SWITCH_VOLTAGE) {
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u32 clk_en_a;
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/* Special bit makes CMD11 not die */
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cmdr |= SDMMC_CMD_VOLT_SWITCH;
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/* Change state to continue to handle CMD11 weirdness */
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WARN_ON(slot->host->state != STATE_SENDING_CMD);
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slot->host->state = STATE_SENDING_CMD11;
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/*
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* We need to disable low power mode (automatic clock stop)
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* while doing voltage switch so we don't confuse the card,
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* since stopping the clock is a specific part of the UHS
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* voltage change dance.
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*
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* Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
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* unconditionally turned back on in dw_mci_setup_bus() if it's
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* ever called with a non-zero clock. That shouldn't happen
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* until the voltage change is all done.
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*/
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clk_en_a = mci_readl(host, CLKENA);
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clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
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mci_writel(host, CLKENA, clk_en_a);
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mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
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SDMMC_CMD_PRV_DAT_WAIT, 0);
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}
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if (cmd->flags & MMC_RSP_PRESENT) {
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/* We expect a response, so set this bit */
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cmdr |= SDMMC_CMD_RESP_EXP;
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@ -775,11 +807,15 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
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unsigned int clock = slot->clock;
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u32 div;
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u32 clk_en_a;
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u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
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/* We must continue to set bit 28 in CMD until the change is complete */
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if (host->state == STATE_WAITING_CMD11_DONE)
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sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
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if (!clock) {
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mci_writel(host, CLKENA, 0);
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mci_send_cmd(slot,
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SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
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mci_send_cmd(slot, sdmmc_cmd_bits, 0);
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} else if (clock != host->current_speed || force_clkinit) {
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div = host->bus_hz / clock;
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if (host->bus_hz % clock && host->bus_hz > clock)
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@ -803,15 +839,13 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
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mci_writel(host, CLKSRC, 0);
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/* inform CIU */
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mci_send_cmd(slot,
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SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
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mci_send_cmd(slot, sdmmc_cmd_bits, 0);
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/* set clock to desired speed */
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mci_writel(host, CLKDIV, div);
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/* inform CIU */
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mci_send_cmd(slot,
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SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
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mci_send_cmd(slot, sdmmc_cmd_bits, 0);
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/* enable clock; only low power if no SDIO */
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clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
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@ -820,8 +854,7 @@ static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
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mci_writel(host, CLKENA, clk_en_a);
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/* inform CIU */
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mci_send_cmd(slot,
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SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
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mci_send_cmd(slot, sdmmc_cmd_bits, 0);
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/* keep the clock with reflecting clock dividor */
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slot->__clk_old = clock << div;
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@ -897,6 +930,17 @@ static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
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slot->mrq = mrq;
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if (host->state == STATE_WAITING_CMD11_DONE) {
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dev_warn(&slot->mmc->class_dev,
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"Voltage change didn't complete\n");
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/*
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* this case isn't expected to happen, so we can
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* either crash here or just try to continue on
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* in the closest possible state
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*/
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host->state = STATE_IDLE;
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}
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if (host->state == STATE_IDLE) {
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host->state = STATE_SENDING_CMD;
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dw_mci_start_request(host, slot);
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@ -973,6 +1017,9 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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/* Slot specific timing and width adjustment */
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dw_mci_setup_bus(slot, false);
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if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
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slot->host->state = STATE_IDLE;
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switch (ios->power_mode) {
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case MMC_POWER_UP:
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if (!IS_ERR(mmc->supply.vmmc)) {
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@ -1016,6 +1063,59 @@ static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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}
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}
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static int dw_mci_card_busy(struct mmc_host *mmc)
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{
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struct dw_mci_slot *slot = mmc_priv(mmc);
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u32 status;
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/*
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* Check the busy bit which is low when DAT[3:0]
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* (the data lines) are 0000
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*/
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status = mci_readl(slot->host, STATUS);
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return !!(status & SDMMC_STATUS_BUSY);
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}
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static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct dw_mci_slot *slot = mmc_priv(mmc);
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struct dw_mci *host = slot->host;
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u32 uhs;
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u32 v18 = SDMMC_UHS_18V << slot->id;
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int min_uv, max_uv;
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int ret;
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/*
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* Program the voltage. Note that some instances of dw_mmc may use
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* the UHS_REG for this. For other instances (like exynos) the UHS_REG
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* does no harm but you need to set the regulator directly. Try both.
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*/
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uhs = mci_readl(host, UHS_REG);
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if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
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min_uv = 2700000;
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max_uv = 3600000;
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uhs &= ~v18;
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} else {
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min_uv = 1700000;
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max_uv = 1950000;
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uhs |= v18;
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}
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if (!IS_ERR(mmc->supply.vqmmc)) {
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ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
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if (ret) {
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dev_err(&mmc->class_dev,
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"Regulator set error %d: %d - %d\n",
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ret, min_uv, max_uv);
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return ret;
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}
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}
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mci_writel(host, UHS_REG, uhs);
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return 0;
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}
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static int dw_mci_get_ro(struct mmc_host *mmc)
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{
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int read_only;
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@ -1158,6 +1258,9 @@ static const struct mmc_host_ops dw_mci_ops = {
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.get_cd = dw_mci_get_cd,
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.enable_sdio_irq = dw_mci_enable_sdio_irq,
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.execute_tuning = dw_mci_execute_tuning,
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.card_busy = dw_mci_card_busy,
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.start_signal_voltage_switch = dw_mci_switch_voltage,
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};
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static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
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@ -1181,7 +1284,11 @@ static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
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dw_mci_start_request(host, slot);
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} else {
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dev_vdbg(host->dev, "list empty\n");
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host->state = STATE_IDLE;
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if (host->state == STATE_SENDING_CMD11)
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host->state = STATE_WAITING_CMD11_DONE;
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else
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host->state = STATE_IDLE;
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}
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spin_unlock(&host->lock);
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@ -1292,8 +1399,10 @@ static void dw_mci_tasklet_func(unsigned long priv)
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switch (state) {
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case STATE_IDLE:
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case STATE_WAITING_CMD11_DONE:
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break;
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case STATE_SENDING_CMD11:
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case STATE_SENDING_CMD:
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if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
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&host->pending_events))
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@ -1894,6 +2003,14 @@ static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
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}
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if (pending) {
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/* Check volt switch first, since it can look like an error */
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if ((host->state == STATE_SENDING_CMD11) &&
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(pending & SDMMC_INT_VOLT_SWITCH)) {
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mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
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pending &= ~SDMMC_INT_VOLT_SWITCH;
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dw_mci_cmd_interrupt(host, pending);
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}
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if (pending & DW_MCI_CMD_ERROR_FLAGS) {
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mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
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host->cmd_status = pending;
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@ -1999,7 +2116,9 @@ static void dw_mci_work_routine_card(struct work_struct *work)
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switch (host->state) {
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case STATE_IDLE:
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case STATE_WAITING_CMD11_DONE:
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break;
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case STATE_SENDING_CMD11:
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case STATE_SENDING_CMD:
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mrq->cmd->error = -ENOMEDIUM;
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if (!mrq->data)
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@ -99,6 +99,7 @@
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#define SDMMC_INT_HLE BIT(12)
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#define SDMMC_INT_FRUN BIT(11)
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#define SDMMC_INT_HTO BIT(10)
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#define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */
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#define SDMMC_INT_DRTO BIT(9)
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#define SDMMC_INT_RTO BIT(8)
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#define SDMMC_INT_DCRC BIT(7)
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@ -113,6 +114,7 @@
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/* Command register defines */
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#define SDMMC_CMD_START BIT(31)
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#define SDMMC_CMD_USE_HOLD_REG BIT(29)
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#define SDMMC_CMD_VOLT_SWITCH BIT(28)
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#define SDMMC_CMD_CCS_EXP BIT(23)
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#define SDMMC_CMD_CEATA_RD BIT(22)
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#define SDMMC_CMD_UPD_CLK BIT(21)
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@ -130,6 +132,7 @@
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/* Status register defines */
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#define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
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#define SDMMC_STATUS_DMA_REQ BIT(31)
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#define SDMMC_STATUS_BUSY BIT(9)
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/* FIFOTH register defines */
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#define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 | \
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((r) & 0xFFF) << 16 | \
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@ -150,7 +153,7 @@
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#define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
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/* Card read threshold */
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#define SDMMC_SET_RD_THLD(v, x) (((v) & 0x1FFF) << 16 | (x))
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#define SDMMC_UHS_18V BIT(0)
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/* All ctrl reset bits */
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#define SDMMC_CTRL_ALL_RESET_FLAGS \
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(SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)
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@ -26,6 +26,8 @@ enum dw_mci_state {
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STATE_DATA_BUSY,
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STATE_SENDING_STOP,
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STATE_DATA_ERROR,
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STATE_SENDING_CMD11,
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STATE_WAITING_CMD11_DONE,
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};
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enum {
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