drm: dp helper: extract drm_dp_clock_recovery_ok
radeon and intel use the exact same definition. Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Acked-by: Dave Airlie <airlied@gmail.com> v2: Kill 2 more helpers in intel_dp.c that I've missed. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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01916270b8
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@ -1695,31 +1695,6 @@ intel_dp_signal_levels_hsw(uint8_t train_set)
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}
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}
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static uint8_t
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intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int s = (lane & 1) * 4;
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uint8_t l = link_status[lane>>1];
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return (l >> s) & 0xf;
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}
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/* Check for clock recovery is done on all channels */
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static bool
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intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
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{
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int lane;
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uint8_t lane_status;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = intel_get_lane_status(link_status, lane);
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if ((lane_status & DP_LANE_CR_DONE) == 0)
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return false;
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}
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return true;
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}
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static bool
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intel_dp_set_link_train(struct intel_dp *intel_dp,
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uint32_t dp_reg_value,
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@ -1885,7 +1860,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
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break;
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}
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if (intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
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if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
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DRM_DEBUG_KMS("clock recovery OK\n");
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clock_recovery = true;
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break;
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@ -1967,7 +1942,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
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break;
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/* Make sure clock is still ok */
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if (!intel_clock_recovery_ok(link_status, intel_dp->lane_count)) {
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if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
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intel_dp_start_link_train(intel_dp);
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cr_tries++;
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continue;
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@ -294,29 +294,6 @@ static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
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return link_status[r - DP_LANE0_1_STATUS];
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}
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static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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{
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int i = DP_LANE0_1_STATUS + (lane >> 1);
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int s = (lane & 1) * 4;
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u8 l = dp_link_status(link_status, i);
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return (l >> s) & 0xf;
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}
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static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count)
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{
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int lane;
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u8 lane_status;
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for (lane = 0; lane < lane_count; lane++) {
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lane_status = dp_get_lane_status(link_status, lane);
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if ((lane_status & DP_LANE_CR_DONE) == 0)
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return false;
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}
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return true;
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}
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static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane)
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@ -811,7 +788,7 @@ static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
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break;
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}
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if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
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if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
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clock_recovery = true;
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break;
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}
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@ -326,5 +326,7 @@ i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
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#define DP_LINK_STATUS_SIZE 6
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bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count);
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bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
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int lane_count);
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#endif /* _DRM_DP_HELPER_H_ */
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