Qualcomm ARM64 Updates for v4.11 Part 2
* Add CoreSight nodes for MSM8916 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYkRzYAAoJEFKiBbHx2RXVPJEQAJ/lgJ0kBgf8Q8iWULy1/hWK +zpSR7f4pRG99pXfwpcl9DEOSTH56gSioJ14lBxkn/Bj2gpLbAstLvykWAr5WLi+ ocxDS7yugy11qCL64tjU2/bP9ijRnb+JKmpCxUtSMRB5JgOQQG3beD2YMF7vf2fv B31mzDvWiORGgVNGeNBc59Lb+4bhUEri5oJX77GLQ5oM8oN8OU8+yGbeUIE2QSol zHGHW1UI/Z5Wl9DX/eoQ7PUhcwzByBnfS8NyWMORnqRQE0dL2iTWoMkmQF2eyihV COg+gmWwFieiZ75I9QkYt8Skd/dPSUKDGb+kWwwcagxOFbrPQoGWxShYK4Gpq7LQ emKPCoDBfkTwf/RbDWe8bwgt0m/3K3Us9uJ6PydJoQrvpUVfeSBob98ko8sB+0bV 1nnFxR50O1lCG3z2eSU7pQUGtnoKw5/+0mKWujYyjPKdNSM6daXyKyHSLOF/bX8/ ypEfEGHEH26klKOgLapN8Zv9DBgJO5pdrUNXseEZ4EhLOjsqL+ocGAhW0tyZzlxE klzXImdSMHtwwGGZwsBtWusQOQQD+vuEN4K6poczBCfuv5gUC3SlT2A/5tfscUbd Us0aTAyNlEDPEpnjqIklAN8GZqPfKYjAbiZAtvWoJ5VSuY9shDQFWzT/c2QgByqP Izx0Cknwc1e9TLqpifzS =GQ+w -----END PGP SIGNATURE----- Merge tag 'qcom-arm64-for-4.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64 Pull "Qualcomm ARM64 Updates for v4.11 Part 2" from Andy Gross: * Add CoreSight nodes for MSM8916 * tag 'qcom-arm64-for-4.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: arm64: dts: qcom: Add msm8916 CoreSight components
This commit is contained in:
Arnd Bergmann
Коммит
01a9c7b7ee
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@ -927,6 +927,246 @@
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};
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};
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};
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tpiu@820000 {
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compatible = "arm,coresight-tpiu", "arm,primecell";
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reg = <0x820000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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port {
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tpiu_in: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out1>;
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};
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};
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};
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funnel@821000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0x821000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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/*
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* Not described input ports:
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* 0 - connected to Resource and Power Manger CPU ETM
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* 1 - not-connected
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* 2 - connected to Modem CPU ETM
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* 3 - not-connected
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* 5 - not-connected
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* 6 - connected trought funnel to Wireless CPU ETM
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* 7 - connected to STM component
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*/
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port@4 {
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reg = <4>;
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funnel0_in4: endpoint {
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slave-mode;
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remote-endpoint = <&funnel1_out>;
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};
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};
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port@8 {
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reg = <0>;
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funnel0_out: endpoint {
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remote-endpoint = <&etf_in>;
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};
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};
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};
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};
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replicator@824000 {
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compatible = "qcom,coresight-replicator1x", "arm,primecell";
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reg = <0x824000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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replicator_out0: endpoint {
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remote-endpoint = <&etr_in>;
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};
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};
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port@1 {
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reg = <1>;
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replicator_out1: endpoint {
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remote-endpoint = <&tpiu_in>;
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};
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};
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port@2 {
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reg = <0>;
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replicator_in: endpoint {
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slave-mode;
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remote-endpoint = <&etf_out>;
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};
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};
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};
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};
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etf@825000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x825000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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etf_out: endpoint {
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slave-mode;
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remote-endpoint = <&funnel0_out>;
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};
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};
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port@1 {
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reg = <0>;
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etf_in: endpoint {
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remote-endpoint = <&replicator_in>;
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};
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};
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};
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};
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etr@826000 {
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compatible = "arm,coresight-tmc", "arm,primecell";
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reg = <0x826000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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port {
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etr_in: endpoint {
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slave-mode;
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remote-endpoint = <&replicator_out0>;
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};
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};
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};
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funnel@841000 { /* APSS funnel only 4 inputs are used */
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compatible = "arm,coresight-funnel", "arm,primecell";
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reg = <0x841000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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funnel1_in0: endpoint {
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slave-mode;
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remote-endpoint = <&etm0_out>;
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};
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};
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port@1 {
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reg = <1>;
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funnel1_in1: endpoint {
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slave-mode;
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remote-endpoint = <&etm1_out>;
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};
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};
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port@2 {
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reg = <2>;
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funnel1_in2: endpoint {
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slave-mode;
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remote-endpoint = <&etm2_out>;
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};
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};
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port@3 {
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reg = <3>;
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funnel1_in3: endpoint {
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slave-mode;
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remote-endpoint = <&etm3_out>;
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};
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};
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port@4 {
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reg = <0>;
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funnel1_out: endpoint {
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remote-endpoint = <&funnel0_in4>;
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};
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};
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};
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};
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etm@85c000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x85c000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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cpu = <&CPU0>;
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port {
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etm0_out: endpoint {
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remote-endpoint = <&funnel1_in0>;
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};
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};
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};
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etm@85d000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x85d000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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cpu = <&CPU1>;
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port {
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etm1_out: endpoint {
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remote-endpoint = <&funnel1_in1>;
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};
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};
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};
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etm@85e000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x85e000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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cpu = <&CPU2>;
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port {
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etm2_out: endpoint {
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remote-endpoint = <&funnel1_in2>;
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};
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};
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};
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etm@85f000 {
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compatible = "arm,coresight-etm4x", "arm,primecell";
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reg = <0x85f000 0x1000>;
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clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
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clock-names = "apb_pclk", "atclk";
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cpu = <&CPU3>;
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port {
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etm3_out: endpoint {
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remote-endpoint = <&funnel1_in3>;
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};
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};
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};
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};
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smd {
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