cpufreq: s3c24xx: split out registers
Each of the cpufreq drivers uses a fixed set of register bits, copy those definitions into the drivers to avoid including mach/regs-clock.h. [krzk: Fix build by copying also S3C2410_LOCKTIME] Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Link: https://lore.kernel.org/r/20200806182059.2431-34-krzk@kernel.org Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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@ -20,11 +20,18 @@
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/regs-clock.h>
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#include <plat/cpu.h>
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#include <plat/cpu-freq-core.h>
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#include <mach/map.h>
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#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
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#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
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#define S3C2410_CLKDIVN_PDIVN (1<<0)
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#define S3C2410_CLKDIVN_HDIVN (1<<1)
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/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
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static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
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@ -23,12 +23,30 @@
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/s3c2412.h>
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#include <plat/cpu.h>
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#include <plat/cpu-freq-core.h>
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#include <mach/map.h>
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#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
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#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
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#define S3C2412_CLKDIVN_PDIVN (1<<2)
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#define S3C2412_CLKDIVN_HDIVN_MASK (3<<0)
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#define S3C2412_CLKDIVN_ARMDIVN (1<<3)
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#define S3C2412_CLKDIVN_DVSEN (1<<4)
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#define S3C2412_CLKDIVN_HALFHCLK (1<<5)
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#define S3C2412_CLKDIVN_USB48DIV (1<<6)
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#define S3C2412_CLKDIVN_UARTDIV_MASK (15<<8)
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#define S3C2412_CLKDIVN_UARTDIV_SHIFT (8)
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#define S3C2412_CLKDIVN_I2SDIV_MASK (15<<12)
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#define S3C2412_CLKDIVN_I2SDIV_SHIFT (12)
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#define S3C2412_CLKDIVN_CAMDIV_MASK (15<<16)
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#define S3C2412_CLKDIVN_CAMDIV_SHIFT (16)
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/* our clock resources. */
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static struct clk *xtal;
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static struct clk *fclk;
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@ -24,11 +24,31 @@
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <mach/regs-clock.h>
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#include <plat/cpu.h>
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#include <plat/cpu-freq-core.h>
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#include <mach/map.h>
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#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
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#define S3C2410_CLKDIVN S3C2410_CLKREG(0x14)
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#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
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#define S3C2440_CLKDIVN_PDIVN (1<<0)
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#define S3C2440_CLKDIVN_HDIVN_MASK (3<<1)
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#define S3C2440_CLKDIVN_HDIVN_1 (0<<1)
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#define S3C2440_CLKDIVN_HDIVN_2 (1<<1)
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#define S3C2440_CLKDIVN_HDIVN_4_8 (2<<1)
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#define S3C2440_CLKDIVN_HDIVN_3_6 (3<<1)
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#define S3C2440_CLKDIVN_UCLK (1<<3)
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#define S3C2440_CAMDIVN_CAMCLK_MASK (0xf<<0)
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#define S3C2440_CAMDIVN_CAMCLK_SEL (1<<4)
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#define S3C2440_CAMDIVN_HCLK3_HALF (1<<8)
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#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
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#define S3C2440_CAMDIVN_DVSEN (1<<12)
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#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5)
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static struct clk *xtal;
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static struct clk *fclk;
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static struct clk *hclk;
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@ -28,9 +28,12 @@
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#include <plat/cpu.h>
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#include <plat/cpu-freq-core.h>
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#include <mach/regs-clock.h>
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#include <mach/map.h>
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/* note, cpufreq support deals in kHz, no Hz */
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#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
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#define S3C2410_LOCKTIME S3C2410_CLKREG(0x00)
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#define S3C2410_MPLLCON S3C2410_CLKREG(0x04)
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static struct cpufreq_driver s3c24xx_driver;
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static struct s3c_cpufreq_config cpu_cur;
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