drm/radeon: set PIPE_CONFIG for 1D and linear tiling modes on CIK
This fixes fast color clear with 1D-tiled single-sample surfaces and Hyper-Z corruption with 1D-tiled depth surfaces. Even though it seems it is not needed for 1D tiling, CMASK and HTILE are always 2D-tiled, thus the hw needs to know the actual pipe configuration for CMASK and HTILE addressing no matter what the tiling mode of the surface is. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com>
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ab8f1a2a0a
Коммит
020ff54676
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@ -2029,6 +2029,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 5:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
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break;
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case 6:
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@ -2049,6 +2050,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 9:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
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break;
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case 10:
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@ -2071,6 +2073,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 13:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
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break;
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case 14:
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@ -2093,6 +2096,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 27:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
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break;
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case 28:
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@ -2247,6 +2251,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 5:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
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break;
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case 6:
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@ -2267,6 +2272,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 9:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
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break;
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case 10:
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@ -2289,6 +2295,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 13:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
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break;
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case 14:
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@ -2311,6 +2318,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 27:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
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break;
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case 28:
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@ -2467,6 +2475,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 5:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
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break;
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case 6:
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@ -2487,6 +2496,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 9:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
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break;
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case 10:
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@ -2509,6 +2519,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 13:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
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break;
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case 14:
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@ -2531,6 +2542,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 27:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_16x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
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break;
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case 28:
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@ -2593,6 +2605,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 5:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
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break;
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case 6:
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@ -2613,6 +2626,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 9:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
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break;
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case 10:
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@ -2635,6 +2649,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 13:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
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break;
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case 14:
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@ -2657,6 +2672,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 27:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P4_8x16) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
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break;
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case 28:
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@ -2813,6 +2829,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 5:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
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break;
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case 6:
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@ -2828,11 +2845,13 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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TILE_SPLIT(split_equal_to_row_size));
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break;
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case 8:
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gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
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gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
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PIPE_CONFIG(ADDR_SURF_P2);
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break;
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case 9:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
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MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P2));
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break;
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case 10:
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gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
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@ -2854,6 +2873,7 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 13:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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PIPE_CONFIG(ADDR_SURF_P2) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
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break;
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case 14:
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@ -2876,7 +2896,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
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break;
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case 27:
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gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
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MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
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MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
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PIPE_CONFIG(ADDR_SURF_P2));
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break;
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case 28:
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gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
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@ -79,7 +79,8 @@
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* 2.35.0 - Add CIK macrotile mode array query
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* 2.36.0 - Fix CIK DCE tiling setup
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* 2.37.0 - allow GS ring setup on r6xx/r7xx
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* 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN)
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* 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
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* CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
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*/
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#define KMS_DRIVER_MAJOR 2
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#define KMS_DRIVER_MINOR 38
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